JPS6339074B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic musical instrument such as an electronic organ. As is well known, electronic musical instruments include a large number of key switches for detecting key operations and a large number of tone lever switches (or tone levers) for detecting the operation status of tone control operators (tone levers). It is provided. When musical tones are generated, the operating states of the above-mentioned switches and the like are constantly scanned, and musical tones are formed based on the results of this scanning. Incidentally, the scanning of the above-mentioned key switches takes more time as the number of switches increases. Therefore, the more keys and tone levers an electronic musical instrument has, the more efficient it becomes to scan the switches in a short time. Therefore, the present invention provides an electronic musical instrument that can efficiently scan key switches and the like in a short time, so that changes in the operating state of the tone lever take a much longer time than changes in the operating state of the keys. Focusing on the phenomenon that occurs in
It is characterized in that the time interval from one scan to the next scan is larger than the scan interval of the key switch. More specifically, the present invention provides: a plurality of keys, a plurality of timbre control operators, and a plurality of timbre control operators provided in common to the plurality of keys and the plurality of timbre control operators; A first process of scanning the plurality of timbre control operators to obtain key status indicating the key depression status of each key, and a second process of scanning the plurality of timbre control operators to obtain operator information indicating the operation status of each operator. The process is selectively executed, and the first process is repeatedly executed at a first timing of the process, and the second process is repeatedly executed at a second timing that is longer than the interval between the first timings. and processing means for repeatedly executing the process described above, and the pitch and timbre of musical tones are controlled based on the key information and the operator information. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an electronic organ (electronic musical instrument) according to the present invention.The electronic organ shown in this diagram can be roughly divided into keyboard circuit 1.
1, an assigner 12, and a tone generator 13. The assigner 12 is the controller 1
4, a calculation control unit 19 including a calculation unit 15, an interrupt control circuit 16, a pulse generator 17, and a data port 18; a ROM (read only memory) 20;
It is composed of a RAM (random access memory) 21 and a first storage section 23 having a register 22, and the musical tone generating section 13 is a wave generator (hereinafter referred to as WG) having 32 channels.
25, an envelope generator 26 that sends envelope information to this WG 25, and a D/A
It is composed of a (digital/analog) conversion circuit 27, an amplifier 28, and a speaker 29. In addition,
The control section 14 and calculation section 15 described above are usually constructed using a microcomputer. Furthermore, the above-mentioned envelope is the envelope of the musical tone signal. That is, a normal musical tone signal has an envelope consisting of three states: a rising state (attack state) B1, a sustaining state B2, and a falling state (decay state) B3, as indicated by the symbol B in FIG. . This electronic organ operates under program control, and its program is composed of a processing program stored in the ROM 20 and various microprograms stored in the microprogram memory 45 in the control section 14. Also,
Various tone data and frequency data necessary for forming musical tone signals (digital signals) in the WG 25 are stored in the ROM 20. Based on the above processing program and microprogram, the system operates as follows. That is, when a key is pressed, the keyboard circuit 11 first
supplies key switch information corresponding to the pressed key to the assigner 12 via the data bus 30. The assigner 12 outputs frequency data and tone data corresponding to the supplied key switch information.
Read from ROM20 and transfer the read data to WG2
Allocate to multiple channels of 5. WG2
Each of the channels 5 forms a musical tone signal (digital signal) based on data assigned to the channel and envelope information supplied from the envelope generator 26. The musical tone signals formed by these channels are converted into analog signals by the D/A converter 27, and are emitted as musical tones from the speaker 29 via the amplifier 28. The outline of this electronic organ has been described above, and now the details of this electronic organ will be explained. First, the keyboard circuit 11 includes an address decoder 34,
Buffer bus driver 35, matrix circuit 3
Consists of 6. The address decoder 34 decodes the switch address signal supplied via the address bus 37.
Each of these output terminals is connected to each column line of the matrix circuit 36, respectively. The matrix circuit 36 is a matrix of 12 rows and 5 columns, and at each intersection of this matrix,
The contacts of each switch of the tone lever (a lever for setting tones such as "Violin" and "Flute") 38 and the contacts of each key switch of the keyboard key 39 are connected together with diodes as shown by symbol A in the figure. It is inserted. In this embodiment, for convenience of explanation, it is assumed that the tone lever 38 consists of six tone levers, and each tone lever can adjust the volume in four stages (therefore, the information regarding each tone lever is It is represented by 2 bits, and corresponding to these 2 bits, two tone lever switches are set for each tone lever.
12 keys in total), and the keyboard keys 39 are composed of 4 octaves (12×4=48 keys). The switches of each tone lever are arranged in one row on the left side of the matrix circuit 36 (in the figure) (the two switches surrounded by broken lines in the figure are one row).
(corresponds to two tone levers), and keyboard key 3.
Nine key switches are arranged in four columns on the right side of the matrix circuit 36. The buffer bus driver 35 is a bus driver for outputting on/off information of each of the switches to the data bus 30, and has 12 input terminals and an output terminal, and the input terminal is connected to each row line of each matrix circuit 36. The output terminal is connected to the data bus 30. The control unit 14 includes an instruction register 4
2, an instruction decoder 43, a microprogram/address sequencer 44, a microprogram memory 45 (second storage section), and a pipeline register 46. The instruction register 42 temporarily stores each instruction of the processing program read from the ROM 20, and the instructions temporarily stored in the instruction register 42 are transferred to the instruction decoder 4.
3 and supplied to the microprogram address sequencer 44. The microprogram address sequencer 44 specifies the address of the microprogram memory 45 based on the output of the instruction decoder 43, and as a result, the processing program temporarily stored in the instruction register 42 is transferred from the microprogram memory 45. The microprogram corresponding to the instruction is read and the pipeline register 4
6. The calculation unit 15 includes a microfunction decoder (hereinafter abbreviated as MFD) 48 and a calculation circuit 4.
9, etc., and decodes each instruction of the microprogram supplied from the control unit 14 and executes a predetermined process. That is, MFD4
8 decodes each instruction of the microprogram supplied from the pipeline register 46, and based on the decoding result, register group 50, multiplexers 51, 52, arithmetic circuit 49, memory address register 53, data register 54, output Control signals are output to buffers 55 and 56, respectively. The register group 50 is a working register used in the process of processing each instruction of the microprogram, and the output of the arithmetic circuit 49 is read by the control signal from the MFD 48. is supplied to the input end of The multiplexer 51
The input terminal of is connected to the data bus 30, the third input terminal is connected to the output terminal of the data register 54, and the first to third input terminals are connected to the output terminal of the data register 54.
The data obtained at the third input terminal is selectively outputted to the arithmetic circuit 49. multiplexer 5
2 has its first input terminal connected to the data bus 30 and its second input terminal connected to the output terminal of the data register 54, respectively, and selectively transmits data obtained at these first and second input terminals. It is output to the arithmetic circuit 49. The arithmetic circuit 49 receives various data supplied from the multiplexers 51 and 52 (this data includes address data specifying the address of each memory in the first storage section 23 and data used when allocating the above-mentioned keys to channels). ) is calculated based on the control signal from the MFD 48, and the calculation result is supplied to the memory address register 53 or data register 54. The memo address register 53 temporarily stores address data supplied from the arithmetic circuit 49.
The output of No. 3 is output to the address bus 37 via the output buffer 55. data register 5
4 temporarily stores data supplied from the arithmetic circuit 49 (data used when assigning keys to channels), and the output of this data register 54 is output to the data bus 30 via an output buffer 56. Ru. The interrupt control circuit 16 performs various processes when an interrupt occurs. Here, the interrupt signal of this electronic organ will be explained. This electronic organ has three interrupt signals INTR1, INTR2, and INTR3. Interrupt signal INTR1 is pulse generator 1
Based on the output of 7, the interrupt control circuit 16
This is an interrupt signal that is periodically generated every sec, and when this interrupt signal INTR1 is generated, on/off information of each key switch of the keyboard keys 39 is read into the RAM 21. The interrupt signal INTR2 is an interrupt signal generated by frequency-dividing the output of the pulse generator 17 by a frequency divider in the interrupt control circuit 16, and has a frequency of several 100 msec.
Occurs periodically. And this interrupt signal
When INTR2 occurs, on/off information for each switch of the tone lever 38 is read into the RAM 21. Note that the period of interrupt signal INTR2 is the interrupt signal
The reason why the cycle is much larger than that of INTR1 is that normally each key is operated frequently, but
This is because each tone lever is not operated as frequently as each key. The interrupt signal INTR3 is an interrupt signal supplied from the WG 25, and is generated when the musical tone signal formed in each channel within the WG 25 becomes 0. Note that this interrupt signal
INTR3 will be described later. And these interrupt signals INTR1 to INTR3
When any of the above occurs, the control unit 14 detects this, reads the interrupt instruction into the instruction register 42, and decodes it when the currently executing microprogram module is completed.
The priorities of the interrupt signals INTR1 to INTR3 are determined in the interrupt control circuit 16 as INTR3>INTR1>INTR2. As mentioned above, the ROM 20 stores processing programs, frequency data, tone data, etc., and is supplied with an address signal from the output buffer 55 via the address bus 37, and read out using the same address signal. Each instruction or various data of the processing program is transferred to the data bus 3.
Output to 0. The RAM 21 stores various data tables, data files, etc. used in channel assignment, and is supplied with address signals from the output buffer 55, and its input/output ends are connected to the data bus 30. . The register 22 stores various statuses or commands (described later), and is supplied with an address signal from an output buffer 55, and its input end is connected to the data bus 30. Data port 18 is connected to frequency data, tone data stored in ROM 20, and register 2.
This is a register for outputting various commands stored in WG 25 and envelope generator 26 to WG 25 and envelope generator 26. Addresses are supplied from output buffer 55, and its input end is connected to data bus 30. In addition, the above
The contents stored in the ROM 20, RAM 21, register 22 and data port 18 are shown in FIG. Next, the operation of the electronic organ shown in FIG.
The explanation will be based on the flowchart shown in the figure. In the following description, "1" indicates a binary logic level "1" signal, and "0" indicates a binary logic level "0" signal. FIG. 2A is a flowchart showing the flow of the program, and FIG. 2B is an interrupt processing routine. As shown in this figure, the program of this electronic organ consists of eight main routines R1 to R8 and three interrupt processing routines I1 to I3. Each routine is converted into a plurality of microprogram modules and stored in the microprogram memory 45, and macro instructions for calling these microprogram modules are stored in the ROM 20 as processing programs.
Each of the above routines will be sequentially explained below. (1) Initial Reset Routine R1 When power is turned on in this electronic organ, the program first enters this initial reset routine R1, and initial resets of each part are performed. (2) Tone lever on/off detection routine I1 This interrupt processing routine
This is executed every time the interrupt signal INTR2 occurs at an interval of 100 msec, and detects the on/off state of each tone lever switch in the keyboard circuit 11 at the time the interrupt signal INTR2 occurs. That is, in the interrupt control circuit 16, the interrupt signal INTR2
When this occurs, a switch address signal is supplied to the address decoder 34, and each tone lever switch is turned on/off based on this switch address signal.
Off information is read into register 22 via buffer bus driver 35 and data bus 30. Based on the read tone lever switch on/off information, a new tone lever status table (hereinafter abbreviated as NTS) 60 shown in FIG. 3 is created in the register 22. In this case, in this NTS60,
The volume setting of each tone lever 1-6 is indicated by a binary number. That is, in the example shown in the figure, tone levers 1, 4, 5, and 6 request a volume of "0", and tone lever 2 requests a volume of "3".
, the tone lever 3 requests a volume of "2". (3) Tone lever position and change detection routine R2 When the above-mentioned initial reset routine R1 is completed, the program advances to this routine R2.
This routine R2 specifies that the current contents of NTS60 are the same as when this routine R2 was executed last time.
This is to detect whether the contents are different from the contents of the NTS60 and the contents of the old tone lever status table (hereinafter referred to as OTS; see Figure 3) 61 created in the RAM21. The above detection is performed by comparing the . Note that OTS61 indicates the contents of NTS60 at the time when this routine R2 was executed last time, and is created in routine R3, which will be explained next. If the result of executing routine R2 is "YES" (change), the program proceeds to routine R3, and if "NO" (no change), the program proceeds to routine R4. (4) Tone lever processing routine R3 This routine R3 processes the tone request file 6 shown in FIG. 3 based on the contents of the above NTS60.
2 is created in the RAM 21. In this electronic organ, the tone data in the ROM 20 is stored based on the tone request file 62 created in this routine R3.
It is now assigned to each channel of WG25. That is, as shown in FIG. 3, the ROM 20 contains a volume table 63, a tone lever index table 64, and a tone data bank 6 in advance.
5 is provided. And the volume table 63
In the tone data bank 65, volume coefficients (each channel of WG 25 sets the volume based on this volume coefficient) corresponding to the volume "1" to "3" set by the tone lever are stored in advance. stores a plurality of tone data, namely tone data i-1, tone data i, tone data i+1, tone data i+2, etc., and the tone lever index table 64 stores:
Tones corresponding to each tone lever 1 to 6
An address pointer of tone data for configuring the tone data is stored. In this case, to explain the example shown in the figure, the tone corresponding to tone lever 1 is composed of tone data i-1 and i, and therefore the slot corresponding to tone lever 1 of tone lever index table 64 is (Storage area) 64a stores the respective leading addresses of tone data i-1 and i in tone data bank 65, that is, address A and address B, and the tone corresponding to tone lever 2 is composed of tone data i+2. Therefore, the address D is stored in the slot 64b, and the tone corresponding to the tone lever 3 is the tone data i,
i+1 and therefore slot 64c
Address B and address C are stored in .
In this embodiment, the maximum number of tone data constituting the tone corresponding to each tone lever is two, but it is possible to have a plurality of pieces of tone data, and there is no need to limit the number to two. When the program enters this tone lever processing routine R3 (a flowchart of this routine R3 is shown in FIG. 4), first, the tone lever 1 volume information stored in the NTS60 (FIG. 3) in the register 22 is the register group 5 of the calculation unit 15
Read within 0. However, since the volume is "0" in this case, no processing is performed.
Then, the volume information of the tone lever 2 is read into the register group 50. In this case, volume "3" is specified. Therefore, the address pointer in slot 64b of tone lever index table 64 (i.e., address D) is first written into area 62c of tone request file 62, and then corresponds to volume "3" in volume table 63. The volume coefficient "1111111" is the area 62 above.
c (see Figure 3). Next, the volume information of the tone lever 3 is read into the register group 50. In this case, volume "2" is specified,
Therefore, first, the slot 64c of the table 64
The first address pointer (that is, address B) in the tone request file 62 is written in the area 62d, and then the volume coefficient ("0100000") corresponding to the volume "2" is written in the same area 62d. The second address pointer in slot 64c (i.e., address c) is then placed in area 62.
Then, the volume coefficient ("0100000") corresponding to the volume "2" is written in the same area 62e. In this way, the volume information of each tone lever in the NTS 60 is sequentially read out and processed.
Finally, the number of address pointers written in the tone request file 62, that is, the number of tone data registered in the tone request file 62, is written in the header (i.e., area 62a) of the tone request file 62. , the creation of the tone request file 62 is completed. After the creation of the tone request file 62 is completed, the contents of the NTS 60 are transferred to the OTS 61, and the program exits from this routine R3. In this way, in this electronic organ, a tone request file 62 as shown in FIG. 3 is created in this routine R3. In this case, each tone lever corresponds only to the address pointer of the tone lever index table 64, so by changing the address pointer of this table 64, arbitrary tone data (timbre) can be made to correspond to each tone lever. be able to. Note that in this tone request file 62, information for tone processing common to this file 62, such as vibrato frequency, vibrato depth, decay length, etc., is stored in area 62b. In other words, although detailed explanation is omitted,
Information for these tone processing is stored in ROM20 in advance.
By storing tone processing information in the ROM 20 and registering it in this file 62 according to the operation position of the tone processing lever,
It becomes possible to perform timbre processing on musical tone signals formed in each of the 25 channels. By the way, in the process of creating the tone request file 62 described above, the number of address pointers written in the header 62a is normally detected by providing a counter called a tone request counter in the register 22, and detecting the number of address pointers written in the header 62a every time an address pointer is written in the file 62. This is done by incrementing this tone request counter and finally referring to the count result of this tone request counter. In addition, in the above process, sequential reading of the contents of the NTS 60, sequential reading of address pointers in each slot of the tone lever index table 64, sequential writing to each area in the tone request file 62, etc. are normally performed by following the corresponding pointers. The contents of this pointer are advanced each time one process is completed, and execution is performed based on the contents of this pointer. For example, when writing an address pointer to the tone request file 62,
First, the entry address (address E) of the area 62c is set in a pointer called the tone request file pointer, and the entry address (address E) of the area 62d is written based on this tone request file pointer. Proceed to F) and write in area 62d based on this entry address (address F)...
It is done as follows. However, these treatments are quite common in this industry, and therefore, description of these treatment steps is omitted in this specification. (5) Key on/off detection routine I2 This interrupt processing routine I2 uses the interrupt signal INTR1
This is executed every time the interrupt signal INTR1 occurs at an interval of several milliseconds, and turns on/off each key switch in the keyboard circuit 11 at the time the interrupt signal INTR1 occurs.
This detects the off state. That is, when the interrupt signal INTR1 is generated in the interrupt control circuit 16, a switch address signal is supplied to the address decoder 34, and based on this switch address signal, key switch on/off information is transmitted to the buffer bus driver 35 and the data bus 30. The new keyboard status shown in FIG.
A table (hereinafter abbreviated as NKS) 70 is created. In the NKS70 shown in this figure, "1" means that the key corresponding to this "1" is the interrupt signal.
This shows that it was pressed at the time of INTR1 occurrence. In other words, in this example, the current C note, E note in the first octave, D# note in the second octave,
This indicates that keys corresponding to the F# note in the third octave and the A note in the fourth octave are being pressed. Note that in this figure, no mark indicates "0". (6) Pressed key position/change detection routine R4 When tone lever processing routine R3 is completed,
The program advances to this routine R4. This routine R4 indicates that the current state of NKS70 is the NKS at the time when this routine R4 was executed last time.
The above detection is performed by comparing the contents of the NKS 70 and the contents of the old keyboard status table (hereinafter abbreviated as OKS) 71 shown in FIG. 5. . In this case, OKS71 indicates the state of the key switch at the time when this routine R4 was executed last time.
6. And this routine R
If the result of executing step 4 is "YES" (change), the program proceeds to routine R5, and if "NO" (no change), the program returns to routine R2. (7) Key-on request file creation routine R5 This routine R5 detects a key that should generate a new musical tone, in other words, a newly pressed key, and based on this detection result, creates a key-on request as shown in FIG. A file (hereinafter abbreviated as ON.RQ) 72 is created on the RAM 21. In this routine R5, first OKS71
An exclusive OR is taken between each bit of the NKS 70 and the corresponding bit of the NKS 70 (OKS
NKS). As a result, only the bit corresponding to the key switch whose state has changed becomes "1". Next, the above calculation result and each bit of NKS 70 are ANDed. [(NKS∧(OKSNKS)]. As a result, only the bit where the key switch is newly turned on becomes “1”.Finally, the OR between the result of the above AND operation and each bit of ON/RQ72 is determined. and the result is newly written to ON・RQ72. ON・RQ=ON・RQ∨{NKS∧(OKSNKS)}...(1) Here, we will explain the meaning of the last OR operation.This electronic The organ is a key-on organ, which will be explained later.
In the channel assignment routine R7, a process is executed to assign keys for generating musical tones to each channel of WG25 based on the ON・RQ72 created here, and when this assignment process is completed, “1” of ON・RQ72 is executed. ``It's supposed to erase bits. By the way, at the time this routine R5 is executed, all the "1" bits written in ON-RQ72 when the routine R5 was executed last time are not necessarily erased, and the "1" bits that should be processed for channel allocation are not always cleared. ``There may be some bits left. The final OR operation is performed to leave unprocessed "1" bits on the ON.RQ 72. In Figure 5, the first
The circle marked on the octave C note indicates this processing bit. (8) Key-off request file creation routine R6 This routine R6 detects a key that should stop generating musical tones, that is, a key that has been released, and based on this detection result, creates a key-off request file (hereinafter referred to as (abbreviated as OF・RQ) 73
It is created on the RAM21. In this routine R6, first the routine R
5, the following operation is performed between the corresponding bits of OKS71, NKS70, and OF・RQ3: OF・RQ=OF・RQ∨{∧(OKSNKS)} ……(2) The result of this operation is OF・RQ73.
written inside. Note that in this formula, is
This means the inversion of each bit of NKS70. Furthermore, the meaning of the OR operation is the same as in routine R5. Next, the contents of NKS 70 are written into OKS 71. In other words, through this process, the table used as NKS this time will be used in the next routine R4~
It will be used as OKS71 in R6 processing. (9) Key-on channel assignment routine R7 This routine R7 generates the frequency data corresponding to the newly pressed key based on the ON-RQ72 created in routine R5 and the tone request file 62 created in routine R3. It executes the process of allocating tone data to an empty channel of WG25. Hereinafter, with reference to FIGS. 6 to 8, this routine R
The execution process of step 7 will be explained. In addition, in Figure 6
ON.RQ72 is the same as ON.RQ72 in FIG. When the program enters this routine R7, it first proceeds to step S1 shown in FIG.
Detection of the "1" bit on 72 is performed. This detection is performed by first moving the slot corresponding to the first octave of ON・RQ72 to the left (in Figure 6).
Shift by bit, then shift the slot corresponding to the second octave to the left by 1 bit,
This is then carried out by sequentially shifting the slots corresponding to the third and fourth octaves to the left, and when a "1" bit is detected (step S2), the program proceeds to step S3. In the example shown in Figure 6, first, the first octave
Since the "1" bit of the C note is detected, the program advances to step S3 at this point. In step S3, frequency data corresponding to the first octave C note is read from the frequency table written in the ROM 20 and transferred to the frequency data area 75 (preset) in the register 22. Next, proceeding to step S4,
The entry address (address be done. Note that the busy key table 76 is the RAM 21
There are 48 slots 76a, 76b, 76c provided corresponding to each key.
It consists of... Next, in step S5, an empty area in the channel assignment table (hereinafter abbreviated as CAT) 77 is detected. Here, CAT77 will be explained. This CAT77 is prepared in advance in the RAM21, and is composed of 15 areas E1, E2...E15, and these areas E
1, E2...E15 are three slots a1, b1, c1, a2, b2, c each consisting of 16 bits.
It is composed of 2,... This CAT77 is
This table shows which channel the musical tone currently being produced (including musical tones in decay state) is assigned to.As explained below, when the musical tone corresponding to a certain key is assigned, each area E1 , E2, . . . E15, that is, the entry addresses of the busy key table 76 representing the corresponding keys are registered in the headers of slots a1, a2, a3... Channels used are now being registered. In this case, each bit of slots b and c corresponds to 32 channels of WG 25, and "1" is registered in the bit corresponding to the channel to which the sound is assigned. Now, when the program advances to step S5, an empty area is detected by searching the header of each area of CAT77. For example, if area E2 is detected as an empty area, the entry address (address Y) of area E2 is stored in the register 22, and the process proceeds to step S6. In step S6, the number of "0" bits in the busy status register 78 provided in the register 22 is calculated. This busy status register 78 is 32
This is a bit register, each bit corresponding to 32 channels, and "1" is registered in the bit corresponding to the channel in use. Therefore, the number of "0" bits calculated in step S6 is equal to the current number of empty channels. When the number of "0" bits (the number of empty channels) of the busy status register 78 is calculated in step S6, the program proceeds to step S7.
Then, the calculated number of "0" bits and the number of tone data registered in the tone request file 62 (see FIG. 3) (that is, the number stored in the header 62a of the tone request file 62) are calculated. are compared. In this case, if the number of "0" bits is greater than or equal to the number of tone data (YES), the program proceeds to step S8. In step S8, the channel number of the empty channel is detected by searching the "0" bit in the busy status register 78. In the example of Fig. 6, first, slot 7
The second bit of 8a is searched for "0", thereby detecting that the second channel is an empty channel. Note that the busy status register 78
In the slot 78a, the 1st to 16th bits correspond to the 1st to 16th channels, respectively, and the 1st to 16th bits of the slot 78b correspond to the 17th to 32nd channels, respectively. When an empty second channel is detected, the program proceeds to step S9, where the channel number "2" is stored in the channel register 79. Next, in step S10, the tone data in the ROM 20 is transferred to the tone data area 80 in the register 22 based on the tone request file 62. That is, to explain the example of FIG. 3, first, the address D stored in the area 62c is read out into the register group 50, then tone data i+2 in the ROM 20 is read out based on this address D, and the tone data area 80
will be forwarded to. Next, the volume coefficient in area 62c is transferred to area 80. The program then proceeds to step S11, where the tone data is modified (timbre processing). This modification of the tone data is performed based on the information for timbre processing stored in the area 62b of the tone request file 62, and by this modification, the tone data is subjected to timbre processing (for example, addition of vibrato). Ru. and,
The program advances to step S12. In step S12, the data port 18 (see FIG.
The entry address of the area corresponding to the second channel is calculated. Next, proceeding to step S13 (FIG. 8), the frequency data in the frequency data area 75, the tone data in the tone data area 80, and the volume coefficient are output to the corresponding area of the data port 18 based on the entry address. . Next, when the program advances to octave S14, "1" is set to the bit corresponding to the second channel of the 32-bit start command register 81 provided in the register 22 (the second bit of the slot 81a), and then this bit is set to "1". The contents of start command register 81 are transferred to data port 18. In this way, data port 18
The frequency data, tone data, volume coefficient, and start command transferred to the WG25 are supplied to the corresponding channel (second channel), and this causes the corresponding channel (second channel) of the WG25 to start. A musical tone signal is formed based on frequency data, tone data, etc. supplied from the data port 18. Next, the program proceeds to step S15, and based on the channel number "2" stored in the channel register 79, "1" is written to the second bit of slot b2 in area E2 detected in step S5. . (The second bit of this slot b2 corresponds to the second channel.) Next, the process advances to step S16, and based on the channel number "2" in the channel register 79, the slot 78a of the busy status register 78 is selected. "1" is written to the second bit. Then, the process advances to step S17. In step S17, it is determined whether all the tone data registered in the tone request file 62 has been allocated to a channel. In this case, since only the tone data registered in area 62c (FIG. 3) has been assigned, the determination result is "NO", and the program returns to step S8. Then, the process of steps S8 to S16 described above is repeated again.
That is, the fourth channel is detected as an empty channel in step S8, the channel number "4" is stored in the channel register 79 in step S9, and the fourth channel is detected as an empty channel in step S10 based on the address B stored in the area 62d of the tone request file 62. Tone data i is successively outputted from the tone data bank 65 and transferred to the tone data area 80, the volume coefficient in the area 62d is transferred to the tone data area 80, the tone data is modified in step S11, and the tone data is modified in step S12. The area entry address corresponding to the fourth channel of the data port 18 is calculated, and the frequency data in the frequency data area 75 and the tone data and volume coefficient in the tone data area 80 are output to the data port 18 in step S13.
In step S14, "1" is set in the bit corresponding to the fourth channel of the start command register 81, and as a result, the fourth channel of WG25 is started, and in steps S15 and S16, CAT is started.
77, the fourth bit of slot b2 and the fourth bit of slot 78a of the busy status register 78 are written with "1".
Proceed to 7. In step S17, it is determined again whether all tone data has been allocated, but in this case, the area 62 of the tone request file 62 is still
Since the assignment of the tone data corresponding to the address C stored in c has not been completed, the judgment result is "NO", and therefore the program returns to step S8 again and the process of steps S8 to S16 is repeated. executed. And this step S8
When the steps from ~S16 are executed, the tone data i+1 corresponding to the address C stored in the area 62e of the tone request file 62 is
Channel 5 of WG25 has started, and slot b of CAT77 has started.
2 and the fifth bit of slot 78a of busy status register 78 are each set to “1”.
is written. In this way, the channel assignment of the first octave/C note is completed, and the speaker 29 outputs three tones at the pitch of the C note of the first octave and corresponding to tone data i, i+1, and i+2, respectively.
Different types of musical tones are sounded at the same time. Furthermore, at this point, "1" is registered in the bits corresponding to the second, fourth, and fifth channels of the busy status register 78 and start command register 81, and furthermore, "1" is registered in the bits corresponding to the second, fourth, and fifth channels of the busy status register 78 and the start command register 81. Fourth,
"1" is also registered in the bit corresponding to the fifth channel. The program then proceeds to step S17, but the judgment result at this step is naturally "YES".
Therefore, the program proceeds to step S18.
Proceed to. In this step S18, the entry address (address
written to. Next, when the process advances to step S19, the entry address (address Y) of the area E2 is stored in the slot 76 of the busy key table 76.
written in a. The process then proceeds to step S20, where the "1" bit corresponding to the first octave C tone of ON.RQ72 is set to "0". In this way, all assignment processing based on the first octave/C note is completed. Next, the program returns to step S1 again.
A "1" bit on ON.RQ 72 is detected. In this case, in the example shown in FIG.
A "1" bit corresponding to the octave D# tone is detected (step S2), and the program therefore advances to step S3, where the assignment process is performed in exactly the same way as in the case described above. Then, when the second octave/D# note assignment process is completed,
A "1" bit on the ON/RQ 72 is detected, and then an assignment process corresponding to the detected "1" bit (third octave/F# note) is performed. When all the "1" bits on the ON.RQ 72 are processed in this manner, the determination result at step S2 becomes "NO" and all processing in routine R7 is completed. Next, step S21 in FIG. 7 will be explained. In the above explanation, step S7
Although the explanation has been given assuming that the judgment result in step 2 is ``YES'', this may also be ``NO''. In other words, the busy status register 78 is “0”
If the number of bits is less than the number registered in the header 62a of the tone request file 62, in other words, if tone data cannot be assigned to a channel due to the small number of empty channels, then step S7 is performed. The judgment result is “NO” and the program moves to step S.
Proceed to 21. In step S21, the channel number of the channel in the decay state is loaded into the dump command register 85 (see FIG. 9), which will be described later.
By outputting the contents of 5 to the data port 18, the channel in the decay state in the WG 25 is forcibly stopped. Then, the routine exits from R7. If you do this kind of processing,
In the WG termination processing routine I3, the corresponding "1" bit of the busy status register 78 is set to "0", thereby increasing the number of empty channels and making it possible to allocate tone data. The meaning of this processing is that the sounding of the musical tone corresponding to the newly pressed key is given priority over the sounding of the musical tone in the decay state. Also,
To perform this process, a decay status register 82 provided within the register 22 and storing the channel number of the decay state is utilized. Next, the sixth bit "1" (marked with a circle) of slot b2 of CAT77 will be explained.
This 6th bit “1” is the 1st octave.
It is not assigned when the C key was pressed, but was assigned when the same key was pressed last time. In other words, when the previously pressed key is released, the generation of the musical tone signal stops after a predetermined decay time in each channel to which that key is assigned (note that the generation of musical tone signals does not necessarily stop at the same time for each channel). (No), CAT77 corresponding to the channel where musical tone signal generation has stopped.
However, if the decay time of a certain assigned channel is long, the previous musical tone signal may continue to be generated in that channel until the moment the same key is pressed this time. In this case, when the same key is pressed again, the slot 76a of the busy key table 76 is filled with CAT77.
The entry address (address Y) of area E2 is registered, and "1" remains in the bit (sixth bit of slot b2) corresponding to the channel in which musical tone signals continue to be generated. . Therefore, the channel assignment for the key pressed this time is registered in area E2, and furthermore, the sixth bit "1" of slot b2 is also left as is in area E2. (For processing when the generation of musical tone signals stops, please refer to interrupt processing routine I3 described later.) In this embodiment, a channel is started for each tone data in the tone request file 62. However, it is also possible to start all channels at the same time. (10) Key-off channel management routine R8 This routine R8 includes the OF・RQ73 created in routine R6 and the busy key table 76 and CAT77 created in routine R7.
Based on this, the musical tone corresponding to the released key (key whose pressed state is released) is erased.
The execution process of this routine R6 will be explained below with reference to FIGS. 9 and 10. In addition, in Fig. 9
OF.RQ73 is the same as OF.RQ73 in FIG. When the program enters this routine R8, it first proceeds to step S1 shown in FIG.
Detection of the "1" bit on 73 is performed. Note that this detection is “1” on ON・RQ72 mentioned above.
The process is carried out in exactly the same manner as in the case of bit detection (step S1 in FIG. 7). In the example shown in FIG. 9, the "1" bit of the first octave A# note is first detected (step S2), and the program proceeds to step S3. In step S3, the position of the detected “1” bit (OF・RQ7
3) based on the busy key table 7
The entry address (referred to as address V) of slot 76m corresponding to the first octave A# note of No. 6 is calculated. Next, in step S4, the contents of the slot 76m are read out based on the calculated entry address (address V) and transferred into the register group 50. In this case, the content of the slot 76m is the entry address (address U) of the area En, assuming that the channel assignment for the first octave/A# note is registered in the area En of the CAT 77. Next, when proceeding to step S5, the contents of slot 76m (address U)
The contents of slots bn and cn of area En are read out based on , and loaded into either Decay command register 84 or dump command register 85 . Note that which one is loaded is controlled by a changeover switch provided in the operating section of this electronic organ. Then, when proceeding to step S6,
In step S5, the contents of the register 84 or 85 loaded with the contents of the area En are output to the data port 18, and the channel to which the tone corresponding to the A# note of the first octave is assigned (see Fig. 9) is outputted to the data port 18. In the example shown in , the generation of musical tone signals of the first, seventh, and eighth channels is stopped. In this case, if the musical tone is loaded into the decay command register 84 in step S5, the musical tone is gradually erased as it decays, and if it is loaded into the dump command register 85, the musical tone is erased immediately. Next, when the program proceeds to step S7, the "1" bit of the first octave A# note on the OF.RQ 73 is erased, and the program returns to step S1 again. Then, when the "1" bit of the third octave F note is detected in step S1, the judgment result in step S2 is "YES".
As in the above case, steps S3 to S
Step 6 is executed, and the musical tone signal of the channel to which the third octave/F note is assigned is stopped or put into a decay state. Then, in step S7, the third octave F note "1"
The bit is erased and the process returns to step S1. In this way, when all the "1" bits on the OF.RQ 73 are processed, the determination result in step S2 becomes "NO" and the processing in this routine R8 is completed. (11) WG end processing routine I3 This interrupt processing routine I3 is executed based on the interrupt signal INTR6 generated from WG 25 when the generation of musical tone signals in the channel of WG 25 has completely stopped (when the decay state has ended). Its main purpose is to set the bit corresponding to the channel in the busy status register 78 (Figs. 6 and 11) to "0", thereby making the same channel an empty channel and using it as a new key. The object of the present invention is to make it possible to allocate the occurrence of a musical tone corresponding to a musical tone. That is, in response to one pressed key,
Musical sound signals generated in multiple channels (three channels in the examples shown in Figures 3 and 6 above) do not necessarily stop at the same timing; for example, in the case of percussive sounds, the key is It may stop even though it is pressed. In such a case, if a channel whose musical tone signal has already stopped is made to wait until all musical tone signals of other channels corresponding to the same key have stopped, the efficiency of channel use will be extremely poor. Taking these points into consideration, this electronic organ is provided with this interrupt processing routine I3 so that the channel in which musical tone generation has stopped can be immediately released to other keys. The execution process of this interrupt processing routine I3 will be explained below with reference to FIGS. 11 and 12. In the following description, it is assumed that the generation of musical tone signals has now stopped in the seventh channel, and that this seventh channel is registered in area E6 of the CAT77. When the generation of musical tone signals stops in the seventh channel and an interrupt signal INTR3 is generated from the WG 25, the program first proceeds to step S1 shown in FIG. 12. And this step S
1, the seventh bit (corresponding to the seventh channel) of the slot 78a of the busy status register 78 is set to "0", and the process then proceeds to step S2. This step S2 and the next step S3
is for erasing the seventh channel registered in CAT77, specifically, erasing "1" in the seventh bit of slot b6 corresponding to the seventh channel of area E6. The reason why this process must be performed is as follows. For example, the musical tone signal that has been generated until now in the seventh channel is a percussive musical tone signal, and at the time when the generation of the musical tone signal has stopped, the key corresponding to the musical tone signal (referred to as the first key) is still Assume that the button remains pressed down. Then, when the musical tone signal stops, the bit corresponding to the seventh channel of the busy status register 78 is set to "0" (step S1).
It is possible that the occurrence of a musical tone corresponding to a newly pressed key (referred to as the next key) before the first key is released is assigned to this seventh channel. If the above-mentioned process is not performed in such a case, when the first key is released, the contents of the CAT77 area corresponding to the first key are transferred to, for example, the Decay command register 84, and then this The contents of the Decay command register 84 are output to the data port 18, and the seventh channel, which is assigned to generate the musical tone corresponding to the next key, is also shifted to the Decay state. In order to eliminate such inconvenience, step S2
and processing by S3 is required. Now, when the program advances to step S2
CAT77 area E1 header (slot a
It is determined whether or not 1) is "0". In this case, for example, if the answer is "NO" (not "0"), the program proceeds to step S3. Step S
3, a logical AND is first performed between each bit in slots b1 and c1 of area E1 and the corresponding bit in busy status register 78, and then the result of this operation is stored in slots b1 and c1. As a result, if "1" is found in the seventh bit of slot b1, that "1" is erased.
In this example, slot b in area E6
Since “1” is in the 7th bit of 6, area E6
The 7th bit of slot b1 is not "1". Therefore, the result of the AND operation is the same as the content of area E1 before the operation. When the execution of step S3 is completed, step S4
Proceed to. In this step S4, area E1
It is determined whether the contents of (the contents of slots b1 and c1) are all "0". In this case, area E
Since "1" remains in "1", the judgment result is "NO" and the program proceeds to step S6. In this step S6, the above-mentioned step S3
It is determined whether the processing in step 1 has been performed in all areas E1 to E15 whose headers are not "0". In this case, since only area E1 has been processed, the determination result is "NO" and the program returns to step S2 again. In step S2, it is determined whether or not the header (slot a2) of area E2 is "0".
In this case, if the header is set to "0"("YES"), the program proceeds to step S6.
The result of the determination at step S6 is "NO", and the program proceeds to step S2 again, where the header of area E3 is examined. It is assumed that the areas E1, E2, . In this case, the determination result in step S2 is "NO" and the process advances to step S3. Then, in step S3, the logic between the contents of the busy status register 78 and the contents of slots b6 and c6 in area E6 is determined.
By performing the AND operation, "1" in the seventh bit of slot b6 is erased (set to "0"). Next, when proceeding to step S4, the contents of slots b6 and c6 of area E6 are all "0".
In this case, it is still “1”.
If there remains, the program goes to step S6.
Proceed to. In this way, when the processing for all areas E1 to E15 is completed, the program exits from this interrupt processing routine I3. Next, for example, the 8th channel has just ended, and this 8th channel is in area E7 of CAT77.
A case will be explained in which the decay time of the musical tone signal generated in the eighth channel is relatively long. When the interrupt signal INTR3 is generated and the program proceeds to step S1, "1" in the eighth bit (corresponding to the eighth channel) of the slot 78a of the busy status register 78 is erased. Then,
After areas E1 to E6 are processed in the same manner as in the case described above, in step S3, "1" in the 8th bit of slot b7 of area E7 is erased.
Then, the process advances to step S4. Here, it is assumed that because the decay time of the musical tone signal of the eighth channel was relatively long, all other "1" bits in area E7 had been erased by the time the eighth channel ended. In this case, by executing step S3, the determination result in step S4 becomes "YES", and the program proceeds to step S5. In step S5, first, based on the entry address of the busy key table 76 (see FIG. 9) stored in the header of the area E7, the slot of the busy key table 76 specified by the entry address is selected. The contents are erased, and then the header of area E7 is erased. In other words, the connection between the area and the busy key table is released. Through this process, area E7 is released for other keys. For reference, the ROM2 explained so far
0, RAM 21 The contents of each register 22 are summarized in FIG. Finally, the encoder switch used as the tone lever 38 shown in FIG. 1 will be explained using the principle diagram shown in FIG. 14. On the substrate 38a, there are contacts 38b, in which conductors (indicated by diagonal lines in the figure) are formed continuously between the four regions a, b, c, and d shown in the figure.
Point 38 where conductors are formed in areas a and c and insulators (indicated by white areas in the figure) are formed in areas b and d.
c, conductors are formed in areas a and b, and areas c and d
Contacts 38d each having an insulator formed thereon are disposed, and each of these contacts 38b, 38c, 38d
These contact points 38b are connected to each area a, b, c, d above.
A contact slider 38e made of a conductor is provided so as to be able to slide in the direction of the arrow e or f in the figure while contacting the contact point slider 38e. The contacts 38b, 38c, and 38d are connected to corresponding terminals 38f, 38g, and 38h, respectively. Furthermore, a scan strobe signal is applied to the terminal 38f. On the other hand, the terminals 38g and 38h are connected to the cathodes of the corresponding diodes D0 and D1, respectively, and the anodes of the diodes D0 and D1 are connected to the corresponding buffer amplifiers B0 and B, respectively.
It is connected to the input terminal of 1. Furthermore, one end of each anode of the diodes D0 and D1 is connected to the power supply +
It is also connected to the other ends of resistors R0 and R1 connected to Vcc, and is configured so that a signal BIT<0> or BIT<1> is output from the output ends of the buffer amplifiers B0 and B1. The scan strobe signal is a signal for scanning the encoder switch described above, and in this embodiment is output from the address decoder 34 of FIG. 1 when the switch address signal is supplied to the address decoder 34 of FIG. Since the encoder switch is constructed as described above, for example, when the encoder switch shown in FIG. 14 is used as the tone lever 1 in FIG. It is set at the position of area d shown by. In other words, each area d of the contacts 38c and 38d is the contact point 38b.
Therefore, even if a scan strobe signal is input to the terminal 38f, the anodes of the diodes D0 and D1 are at the voltage level of the power supply +Vcc, and therefore the buffer amplifiers B0 and B
The output levels of the output signals BIT<0> and BIT<1> of 1 are both the binary logic level "0". Therefore, the tone lever 1 is in a request state with a volume of 0. Although the encoder switch described above is used for changing the volume in four stages using a 2-bit binary code, it can easily be used for changing the volume in multiple stages using a binary code such as 3-bit or 4-bit. Furthermore, as an encoder switch, not only binary code but also other codes such as Gray code can be used. As explained above, according to the present invention, the scan interval of the tone lever switch is made larger than the scan interval of the key switch, so the time required for the switch scan is longer than when the scan of the tone lever switch is performed at the same time as the scan of the key switch. can be shortened. As a result, especially in an electronic musical instrument using a microcomputer, there is a large amount of time required for tasks other than switch scanning, so various processes can be performed in this time, which has a great practical effect.

[Brief explanation of the drawing]

1 to 13 are diagrams showing one embodiment of the electronic organ according to the present invention, in which FIG. 1 shows the overall configuration, FIG. 2A is a flowchart showing the flow of the program, and FIG. B is a diagram showing the interrupt processing routine, and FIG. 3 is related to the execution of the tone lever processing routine R3 shown in FIG.
4 is a flowchart of the routine R3, and FIG. 5 is a diagram showing the execution of the key-on request file creation routine R5 and the key-off request file creation routine R6 shown in FIG. 2. FIG. 6 is a diagram showing the stored contents of the RAM 21 and registers 22 that are relevant at the time of execution of the key-on channel assignment routine R7 shown in FIG. 2. FIG. , FIG. 8 both show the above routine R.
7, the flowchart in FIG. 9 shows the RAM 21 and register 22 involved when the key-off channel management routine R8 shown in FIG. 2 is executed.
FIG. 10 is a flowchart of the above routine R8, and FIG. 11 is related to the execution of the WG termination processing routine I3 shown in FIG.
Diagram showing the contents of RAM 21 and register 22, 1st
Figure 2 is a flowchart of the above routine I3, the first
Figure 3 shows ROM20, RAM21, register 22,
FIG. 14 is a diagram illustrating the contents stored in the data port 18, and is a diagram illustrating the configuration of an encoder switch used as a tone lever. 11... Keyboard circuit, 14... Control section, 15...
Arithmetic unit, 16...Interrupt control circuit, 17...Pulse generator, 38...Tone lever, 39...Keyboard key.

Claims (1)

[Scope of Claims] 1. A plurality of keys, a plurality of tone control operators, and a device provided in common to the plurality of keys and the plurality of tone color control operators, and configured to scan the plurality of keys. a first process to obtain a key state indicating a key depression state of each key, and a second process to scan the plurality of timbre control operators to obtain operator information indicating an operating state of each operator. It is selectively executed, and the first process is repeatedly executed at a first timing of the process, and the second process is executed at a second timing at a longer interval than the first timing. 1. An electronic musical instrument, characterized in that the electronic musical instrument is equipped with a processing means for repeatedly executing the above, and controls the pitch and timbre of musical tones based on the key information and the operator information.