JPS6337890A - Mos memory device - Google Patents

Abstract

PURPOSE:To improve sense sensitivity and to facilitate a pattern layout by sharing only one conduction type sense amplifier out of a C-MOS shared sense amplifiers and making an I/O gate adjacent to a column decoder. CONSTITUTION:In the constitution of a shared sense amplifier 100, a bit line and an inverted bit line are split into bit line pairs 8, 8' and 10, 10'. Further, each bit line is connected directly to n-channel sense amplifiers 11, 13. A p- channel sense amplifier 12a provided between transfer gates 20a, 20b splitting the bit and inverted bit lines. Moreover, an I/O gate 16 receiving an output signal phiv of a column decoder 14 and transferring data is provided between the amplifier 13 and the decoder 14. Then the amplifier 100 is constituted of the amplifiers 11, 13 and 12a. Thus, the wire for the signal phiv is not led between bit lines and formed without using other wiring materials, the sense sensitivity is improved and the pattern layout is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS memory device, particularly a CMOS dynamic RAM, and relates to a novel configuration of a sense amplifier thereof.

[Conventional technology]

Figure 4 is from the magazine "Electronic Materials J, January 1986 issue, p.41"
Figure 4 of 42. 6 is a diagram showing a configuration method of the conventional shared sense amplifier shown in FIG. 5. In the diagram, 1°1' is a bit line, 7.7' is a bit line, and 2.2' is a 1st. Second
3 is a column decoder, and 4.4' is an I/O line. Further, Ml and M2 are memory cells, which include a transistor Ql, a capacitor 1tc1, and a transistor Q2 . It is composed of a capacitor C2.

Figure 5 shows M when using the sense amplifier configuration shown in Figure 4.
This figure shows the Chisop architecture of the OS dynamic RAM.

In the figure, 5 is a sense amplifier circuit (transistor Ql).

~QI7) 5a, I/O gate (transistor Q,
.

Q4) 5b and a bit line precharge circuit (transistors Q, to Q++) 5c are shown, 3 is a column decoder, and 6 is a row decoder.

The shared sense amplifier uses bit line pairs 1.7 and 1', 7.
' When divided into two bit lines, one sense amplifier is shared and used without providing a sense amplifier for each bit line.
It is characterized by the ability to reduce chip size and help reduce power consumption.

Next, the operation will be explained using FIGS. 4 and 5.

There are two types of operation modes for the shared sense amplifier: a mode when memory cells in the A block (farthest from the column decoder) are accessed, and a mode when the B block (closest to the column decoder) is accessed. Mode 2
It is a kind.

First, a case where memory cell M1 of block A is accessed will be described. First, bit line pair 1°1', 7.7'
The transistors Q%, Qh, Q, Qs forming the transfer gate between the and the sense amplifier circuit 5a are all on, and the bit lines 1, 7.1' and 7' are connected to each other, that is, the gate signal φ1 ．． φ, I are at high level, sense amplifier activation signal φ, AP is at high level, φSAW is at low level, sense amplifier circuit 5a is inactive, and column address signal φ is at low level. It is assumed that transistors Q3 and Qa are off, and the bit line and I/O line are disconnected.

At this time, precharge signal φ2. Transistor Qq
, Q+. , Q, is turned on, bit line pair 1°1',
7.7' potential is constant voltage Vmt (usually (l/2)
Vcc).

Then, φ, C goes low level, and transistors Qq,
Q+o+ Q++ is turned off, and φG+ becomes low level, and the bit line of the non-selected block B is connected to the transistor Qs.
, Qh are turned off, thereby disconnecting from the sense amplifier circuit. Thereafter, word line 2 is accessed, transistor Q is turned on, and data in memory cell M+ is read onto bit line 1'.

After that, φ51. Transistor QIZ+ by φ and □
The Q/O is turned on, the sense amplifier is activated, and the data in the memory cell M1 is amplified onto the bit line 1.1'.

After that, when φ7 becomes high level, transistor Q3,
Qa is turned on and the data on the bit line is Ilo, I/O!
151.

Also, rewriting the opposite data to the data read from the I/O line 1/O'ia is done by the transistor Qs,
This is done by transmitting the l/OvA, I/O line notator to the sense amplifier circuit through Q4 and inverting the flip-flop of the sense amplifier circuit. The data to be read into the memory cell M1 is amplified and written into the memory cell M1.

When memory cell M2 of block B is accessed, data is read to Ilo and I/O lines in a similar operation.

The same applies to the write operation mode.

[Problem that the invention seeks to solve]

Since the conventional shared sense amplifier device is configured as described above, the output signal φV of the column decoder 3 must be connected from the column decoder 3 to the I/O gate included in the circuit section 5. Therefore, it was necessary to pass φ7 between the bit lines using the same wiring material as the bit lines, or to connect φ7 using a different wiring material. Also this φV
Since the signal line forms a capacitance with respect to the bit line, it is necessary to configure the signal line so as not to cause imbalance in the bit line capacitance.

This invention was made in order to solve the above-mentioned problems, and it is possible to form the wiring for the column decoder output signal φ without passing it between the bit lines or using another wiring material. The object of the present invention is to obtain a MOS memory device having a shared sense amplifier with high sensitivity.

[Means for solving problems]

The MOS memory device according to the present invention shares only either the p-ch or n-ch sense amplifier,
The I/O gate is provided at the end of the divided bit line on the side where the column decoder is provided.

[Effect]

In the shared sense amplifier according to the present invention, only one of the p-ch and n-ch sense amplifiers is shared, each divided bit line has a sense amplifier for the other channel, and the I/O Since the gate is provided at the end of one of the divided bit lines on the side where the column decoder is provided, there is no need to provide wiring for the column decoder output signal between the bit lines, and the I/O gate is provided at the end of the bit line. It has a sufficient data amplification function even though it is in the middle of the market, and can transfer data to the I/O line. Also, in terms of pattern layout, the chip area is almost the same compared to the conventional example, and the power consumption is higher than that of the conventional example.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a MOS memory device according to an embodiment of the present invention,
In the figure, 8.8', /O. 1O' is a bit line, bit line (first and second divided bit line pair), 15.15' is a third. 4th word line, 14 column decoder, 9.9
' is l/OvA.

l/OvA.

Figure 2 shows the MO when the sense amplifier shown in Figure 1 is configured.
1 shows a block diagram of an S dynamic RAM. The configuration of the shared sense amplifier is such that the bit lines are divided into 8.8', /O, and /O', respectively.

Also, each bit line is a transistor Q. ,q,,,
n-ch sense amplifier 1 composed of q, , Q/O
1 and 13 (first and second flip-flops). Also, the transistor Q divides the bit lines. ＋Q! ? l Q311 0
Transfer gates 20a and 20b are configured by sz.

Each bit line, transfer gate 2 that divides the bit line
Between 0a and 20b (corresponding to 12) is a transistor Q.
There is one p-ch sense amplifier (third flip-flop) 12a composed of transistors Q*, Q3°, and precharges the bit line and bit line composed of transistors Q*, Q+o, and Q+direct. A precharge circuit 12b is present.

Also, I receives the output signal φ of the column decoder 14 and transfers the bit line data to Ilo and I/O line.
/O gate (transistor Q,,,Q,.

) is located between the n-ch sense amplifier 13 and the column decoder 14 (16 is shown).

In this embodiment, the above n-ch sense amplifier 11.
13 and the p-ch sense amplifier 12a constitute a shared sense amplifier/O0.

Next, the operating mode of the device of this embodiment will be described.

There are two operating modes of this device: one when the memory cell M3 of the A' block is accessed, and the other when the memory cell M4 of the B' block is accessed.

FIG. 3 shows a timing chart of each clock, where the solid line shows when the B' block is accessed and the broken line shows when the A' block is accessed.The following explanation will be made along this timing chart.

(L) At time txto when the A' block is accessed, the bit line, bit line 8°8', /O./O' are both precharged to the VIIL level.txt
, φG+ becomes low level and the bit line, bit line /O.
/O' is φ2. becomes low level, and the precharging and equalization of the bit lines 8 and 8' are completed. 1-1. Word vA15
rises and data in memory cell M3 is read out.

1=14 and φ8. N! becomes a high level, activating the n-ch sense amplifier 11, and almost at the same time, ψ3AP becomes a low level, activating the p-ch sense amplifier 12a, and the data of the memory cell is transferred to the bit lines 8 and 8'. 0
(Vcc Vth) 0 then 1-1. φGl becomes high level, the amplified data is transmitted to the bit line, bift '41A/O. through transistors Qzh, Q, . /O'. 1-1. The N-ch sense amplifier 13 is activated by φSAM+, and the bit line, bit line /O. Data is also expanded to 0■ and (Vcc V) on /O'. Then 1=1. Φ7 becomes high level and Ilo, I/O line 9
．． Data is transferred to 9'.

(2) When the B' block is accessed 1-/O is the same as when the A' block mentioned above is accessed. At t''t, Φ goes low and the bit line 77TIs.

8' is separated. txt, φI becomes low level and the bit line, bit line /O. /O' precharge and equalization are completed. At 1-13, the word line 15' rises and the data in the memory cell M4 is read out. 1=14
So Φ! AN+ becomes high level and n-ah sense amplifier 1
3 is activated, and Φ3AF becomes low level at the same time p
-ch sense amplifier 12a is also activated, bit line, bit vA/O. Memory cell data is 0■ and (
Vcc Vc,,) is amplified to V. Then 1=1.
ΦV becomes high level, and data is transferred to Ilo and I/O line 9.9'.

Since the present invention is configured and operates as described above, it has the following effects.

Since the transfer gate 16 to the Ilo and I/O lines is configured in contact with the column decoder, the column address selection signal Φ,
There is no need to provide wiring between bit lines or use another wiring layer, and the data read from the memory cell is first directly amplified by the N-ch sense amplifier 11.13. In contrast, in the conventional example, once the transfer gate, that is, the transistors Qy, Qs, or Qs, Qb
, the sense sensitivity is improved in the present invention.

Since the I/O gate of the present invention is located in the B' block, it must pass through the transfer gate twice when the A' block is selected, but this is not disadvantageous at all since the sense amplifier 13 functions effectively. It won't happen.

Furthermore, since the sense amplifiers for p-ch and n-ch are separated from each other in terms of pattern layout, the pattern layout is easy from the standpoint of latch amplifiers, etc.

Also, the high level of the bit line is exactly the same as the conventional example (■cC
In addition, in the present invention, as mentioned above, the p-ch sense amplifier and the n-ch sense amplifier are separated from each other in terms of the pattern layout, and the transfer gate transistor is interposed between them. The through current between the p-ch sense amplifier and the n-ch sense amplifier during sensing is greatly improved compared to the conventional example, and there is a great effect on power cutting.

Further, in the present invention, since the bit line and the I/O line do not intersect, it is also possible to form both in the same wiring layer.

Furthermore, in the present invention, the number of n-ch sense amplifiers is twice as large as that of the conventional example, but transistors Q, , , Q, .

Since the size of Q, .

In addition, in the present invention, the bit line precharge level is (Vcc Vth) / 2 = VIL as in the conventional example, which is the potential (OV or Vth) of the cell Tr), and the sensitivity of the sense is 1 by successfully reading the dummy level! Since it can be set almost in the center of the load, it has good sensitivity and is resistant to soft errors.

Note that in the above embodiment, only the p-ch sense amplifier section is shared, and two flip-flops are used in the n-ch sense amplifier section.
However, conversely, only the n-ch sense amplifier section may be shared and two flip-flops of the p-ch sense amplifier section may be provided, and the same effect as in the above embodiment can be obtained.

In addition, although the configuration of the 0MO3 shared sense amplifier is shown in the above embodiment, it can also be an NMO3 shared sense amplifier, in which the p-ah sense amplifier section is configured with a booster circuit consisting only of n-ch transistors. This can be realized by using an active restore circuit that has a

〔Effect of the invention〕

As described above, according to the MOS memory device according to the present invention, only one conductivity type sense amplifier among the CMOS shared sense amplifiers is shared, and the I/O gate is provided adjacent to the column decoder. Various effects such as improved sense sensitivity, easier pattern layout, and resistance to soft errors can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a sense amplifier according to an embodiment of the present invention, FIG. 2 is a block diagram of a memory array when the sense amplifier of FIG. 1 is used, and FIG. 3 is a timing diagram of the sense amplifier of FIG. 1. 4 is a circuit diagram of a conventional sense amplifier, and FIG. 5 is a block diagram of a memory array when the sense amplifier of FIG. 4 is used. In the figure, Qzq, Q3° are p-ch transistors, 12a is a p-ch sense amplifier (third flip-flop), Q33. Qsa is an n-ch transistor, 11 is an n-ch sense amplifier (first flip-flop), Qzs, Q14 is an n-ch transistor, 1
3 is an n-ch sense amplifier (second flip-flop)
, 14 is a column decoder, 15.15' is a word line, 8
．． 8' is the first divided bit line pair, /O. /O' is the second divided bit line pair. 16 is an I/O gate, 20a, 20b
is a transfer gate, and /O0 is a column decoder.

Claims (2)

[Claims] (1) In a MOS dynamic RAM that is formed on a semiconductor substrate and has a configuration in which each bit line pair is divided via a plurality of gates, each bit line pair is composed of a first conductivity type MOS transistor,
and first and second flip-flops connected to the second divided bit line pair, and a second conductivity type MOS transistor connected to the first and second divided bit line pairs via the plurality of sets of gates. a third flip-flop connected to the MOS transistor, and a shared sense amplifier is configured by the first to third flip-flops.
memory device. (2) An I/O gate for transferring bit line data to the data input/output line according to the decoder output is connected to the one closer to the decoder of the first or second divided bit line pair. 2. A MOS memory device according to claim 1, characterized in that: