JPS6337790A - Still picture recording device - Google Patents

Abstract

PURPOSE:To minimize the disorder of a monitor image by providing a correcting means which is connected to the output of a time base correcting means and corrects video signal data outputted by the time base correcting means according to correction conditions. CONSTITUTION:A whole control part 24 determines values of correcting parameters according to photographic conditions, e.g. the gradation characteristics of a camera in use and a lighting state and sets them in a correction part 38 through a control line 40. While a picture element signal is collected, a video signal is read out of one memory array of the time base correction part 18 to an output part 22 through the correction part 38 and this is outputted and displayed on the video monitor device 56 of the output part 22. The display image on the video monitor device 56 is frozen in an image stored in the other memory array during said period. Consequently, the display image on the monitor 56 is not disordered even during the picture data collection.

Description

[Detailed description of the invention] Technical field unfinished 11 is a still image recording device, especially an input video signal.
The present invention relates to a still image recording device that outputs a stable video signal by correcting the time axis of the image.

For example, there is a still image recording device that receives a video signal read out from a video signal recording medium such as a video floppy disk or video tape, and generates a self-portrait on an image recording medium such as photographic paper. Proposed.

For example, in a business-use device that prints negative film or video floppy entrusted by a customer onto color photographic paper, the color and gradation are corrected according to the conditions under which the image to be recorded is taken, making the final image a natural image. It is required to be played as . To this end, it is safe to extract the state of the image to be recorded and collect data for image correction.

In prior art still image recording devices, prior to image recording, several pixel signals of one frame of image are sampled, and the state of the image is determined from these sample data.
Accordingly, there is a method in which image correction conditions or correction parameters such as color and gradation correction are determined, and all corrections of the video signal to be recorded on photographic paper are performed in accordance with these conditions. The determination of this correction condition is performed by a processing system, such as a microprocessor, within the still image recording device.

In a static subjective recording device, the state of the image to be recorded is determined by P2f.
Preferably, it can be monitored with a t-monitor device, but
With conventional devices, when recording on photographic paper, if the recorded image is monitored using a video monitor device, the monitored image may be distorted due to sampling of pixel data for image correction. there were. That is, since the video signal is taken into the processing system in order to collect pixel data from the video signal, the supply of the video signal to the monitor device is interrupted during that time, and the monitor portrait may be temporarily blanked out.

By the way, video signals are input to the still image recording device from various I2 signal sources, for example, a magnetic disk +1
) In the main device, etc., the 211i & signal whose time axis fluctuates due to uneven rotation of the magnetic disk may be manually input. Therefore, a still image recording device is equipped with a time axis correction circuit that absorbs such time axis fluctuations of the input video signal and outputs a single image signal according to a stable reference frequency clock. The time axis correction circuit has a pair of video memories, and while a video signal is being input into one of them, it is inputting a video signal from the other. The present invention reads out the I' mound signal and repeats it alternately between a pair of 111 memory. Monitor image due to collection ^L
Minimize the

Therefore, it is an object of the present invention to provide a still image recording device that eliminates the drawbacks of the prior art and minimizes disturbances in a monitor image when recording an image and collecting pixel signals. .

According to IJJ, which has not yet been disclosed, it has a pair of storage means each capable of storing at least l fields of data of a raster scan video signal representing a still image,
! a time axis correction means for stabilizing the time axis of the video signal by constantly reading out the two-image signal at a predetermined speed; , an output means for outputting the data read from the storage means as a visible image, and the processing means:
When reading or writing video signal data from the processing means to either one of a pair of storage means, data is read from the other storage stage to it. A still image recording device for controlling the time axis correction means so as to repeatedly read out the accumulated video signal data and supply it to the output means. An embodiment of the image recording device will be described in detail.

Referring to FIG. 2, there is shown an embodiment in which the present invention is applied to a still image recording apparatus that generates 14 video signals from a floppy disk. The still image recording apparatus of this embodiment has an input section 10, which has a function of reading a PIL image signal recorded therein from a magnetic disk, that is, a video floppy disk as a video signal recording medium. Instead of a magnetic disk, it may be a device that generates video signals from a video tape, or it may be a device that receives video signals from a communication line or broadcast waves.

In this embodiment, the input section 10 rotates the magnetic disk steadily at a predetermined speed, reads these video signals, and outputs them to the output 12. It also has a Ja tiger that separates the synchronization signal and supplies it to the input control section 14. These synchronization signals are also supplied from the input control section 14 to the overall control section 24. The video signal outputted from the output 12 of the input section 10 is an analog signal VIN, which is input to an analog-to-digital conversion circuit (ADC) 1B and converted into video signal data old N in the form of a digital signal. In this embodiment, this video signal data is supplied to the input 20 of the time axis correction section 18.

This video signal is output from the output section 22 into the a channel as a video signal with a stable time axis. The output unit 22 may be an output device that outputs the I2 image signal as a visible image,
For example, in this embodiment, an optical system including a color separation filter is used to record a three-color separated image projected on a black and white high-brightness CRT. Advantageously, a method is employed in which one image of each color is recorded on the photographic paper 58 by sequentially forming images of each of the three separated colors on the photographic paper 58.

The output unit 22 also includes a video monitor device 56 that displays the video signal as a soft copy. This monitor device 56
may be, for example, a color CRT.

In this embodiment, the time axis correction unit 18 has a capacity of 1 for temporarily storing video signals of l fields or l frames.
It has a pair of memory arrays 100 (FIG. 1), and their read and write operations are controlled by an overall control section 24. Instruction (return enable) signal RE
It outputs control signals such as a write instruction (write enable) signal WE, and also has a device 17 for writing -I into the time axis correction section 18 for data 1ii2B and transferring data to be read from this.

Various control signals such as a memory address (ADR), a clock, and a read/write timing signal of the time axis correction unit 18 are controlled by the output 30 of the input control unit 14, the output 34 of the output control unit 32, and the overall control unit 24. 26. The control g# line 2B from the overall control unit 24 is also applied to the address I)J detection circuit 10 in the time axis correction unit 18, which will be described later.
4 and a switching signal for switching the shift clock switching circuit 112 is also transferred.

In the case of a video signal recording medium such as a magnetic tape or a magnetic tape, the video signal outputted from the output 12 of the input section 1O has the possibility of containing jitter due to its nature.

Therefore, the time axis correction unit 18 stores the video signal data LO IN of the input 20 in one of the memory arrays 100 in synchronization with the pixel clock responsive to the water cycle signal separated from the video signal by the human power unit IO. In this case, the output 3611 is output at a pixel clock speed synchronized with the stable reference clock of the output 1uj control unit 32 during this period, and the image at the output 36 (the output speed of the No. 8 data DOUT is Achieves a stabilizing time axis modification function.

This time axis correction a fE is realized as follows.
When reading a video signal from the human power section 10 into the time axis correction section 1B, the overall control section 24 controls the YJ conversion circuits 104 and 112 so that the writing operation of the time axis correction section 18 can be read from the human power section 11jl to the control section 14. Be controlled. In other words, the synchronization signal -J- included in the video signal inputted to the input section 10 is separated at the input section 10, and the manual control section 14 synchronizes with this signal to generate address, clock, +': inclusive timing signals, etc. A control signal is output to output 30 to control the write operation of time base correction 81118.

When reading video signal data from the time axis correction section 18 and outputting it to the output section 22, the overall control section 24 controls the switching circuits 104 and 112 so that the read operation of the time axis correction section 18 is controlled from the output control section 32. M control. The output control unit 32 outputs memory addresses, memory addresses, etc. according to a stable frequency clock generated by an internal reference generator.
Control signals such as a clock and a read timing signal are outputted to the output 34 to prompt and control the read operation of the time axis correction unit 18.

PIL image signal data DO of output 36 of time axis correction unit 1B
UT is input to the correction section 38. The correction unit 38 receives correction parameters for color and gradation according to the conditions under which the video signal was formed, such as the gradation characteristics of the camera used and the lighting condition, which are set from the overall control unit 24 through a control line 40. It is added. The correction section 38 is a function fE section that corrects the 7000 video signal data according to the correction parameter 11 and outputs the video signal whose color and gradation have been appropriately corrected to its output 42.

Output 42 is digital-to-analog conversion circuit (DAC) 4
4, is converted into a corresponding analog signal, and is output from output 46 to output af122 as, for example, a TV related video signal V[lUT.

Output; ljl '11 The unit 32 has a quasi-oscillator (which generates a reference signal with a stable frequency), and its control line 34 has a quasi-oscillator.

It outputs various timing signals and addresses for extracting Ia'f, & signal data from the memory array 100. Similarly, a timing signal for operating the Digimol analog converter 44 is output to the control line 48.

In addition, i[jJ '8 k 50 to the output unit 22 is
Outputs the nail surface synchronization signal VSYNG, water cycle signal 1 (SYNC, vertical 5IJ line erase signal "-'; VBLK, wood loop erase signal HBLK, etc.) for operating the recording and monitor CRTs. These The signal 1 is also supplied from the control line 52 to the entire ruIu section 24, of which the blanking signal for use -; VBLK is.

It is connected to ;a and 1-inclusive end f- of the CPU of the control unit 24. It should be noted that the synchronization of the ljl 91 section 14 is performed manually by one cycle starting from the output IJ 11 section 32. Therefore, the multiple normal blanking function of the input i1W section 14 is the output i
This corresponds to the one-t direct blanking signal VBLK of the u control section 32.

Each of these parts of this device is controlled by an overall control section 24. The overall control unit 24 includes a video signal recording and correction unit 38.
It has an operation display section for inputting instructions necessary for the stage weight of correction parameters, etc., and displaying the system status. The overall control unit 24 is composed of a processing device such as a microprocessor, and controls the operation of the entire device.
jl at a predetermined pixel position (plurality) of lW image signal data, for example. It also has an image processing function for determining the state of the original image by performing j elemental samples, and for determining color and gradation correction parameters in the correction section 38.

The systematic structure of the time+fb correction i'1l18 will be explained with reference to FIG. Each of the pair of memory arrays 100 is a RAM having a capacity capable of storing l fields or l frames worth of video signal data, and loading and reading thereof are performed by corresponding shift registers 102. be called.

Addresses of memory array 100 are selectively given by address νj conversion circuit 104. The address switching circuit 104 includes a CPυPuless CPU ADR received from the overall control unit 24 via the control edge 2B, a video write address VGA AllR1 received from the input control unit 14 via the 1r7J control line 30, and a video received from the output control unit 32 via the control line 34. Read address VRA[1Rt-i
Select fl and output to the corresponding memory array 100 from lOG! This is an address selection circuit. For example, 10,000 parts 1 of the memory array 100 are occupied by video signals 7
,! If the other side 2 is a read-out island j of the 12-image signal, the address switching circuit 104 supplies the video code address VW ADR to the former, and the video read address VRADR to the latter. The same applies to the CPU address CPU ADR.

Each of l pairs of shift registers 102 has 1ull'
f4: %I The video signal t'j inputted in series from the data input 108 is sequentially received in response to the shift clock, and this is read into the corresponding memory array 100 as parallel data, or from now on in parallel. la' read out in
This is a shift register circuit that outputs image signal data to an output 110 as serial data in response to a shift clock. The shift clock is supplied from the shift clock switching circuit 112 to the clock manual 114 .

Data transfer between memory array 100 and shift register 102 is performed during both reading and writing while water synchronization signal (ISYNC) is at a low level. Further, this transfer is not performed during the vertical retrace period, and no data is outputted to the shift register 102 during the water MO synchronization signal period and the following period, which is considered as the water motion retrace period.

The shift clock switching circuit 112 receives the CPU clock CPUCLK from the overall control unit 24 via the control line 2B.
, a video write clock vw C:LK received from the input control section 14 via the control line 30, and the output control section 3.
2 is a clock selection circuit that selects the video read clock VRCLK received from the control line 34 and supplies it to the corresponding memory array 100 from the output 114. For example, if one memory l of the memory array 100 is in a writing state when receiving a video signal, and the other memory array t2 is in a video signal reading state,
The shift clock switching circuit 112 supplies the video write clock VW CLK to the +iij terminal, and the video read clock VRCLK to the latter terminal. c.
The same applies to the CPU CLK.

A single signal data line 20 from the analog-to-digital conversion circuit 16 and a data line 28 from the overall control section 24
As shown in the figure, is connected to the data terminal 10B of the shift register 102 via the changeover switch 11[i. A data line 28 from the overall control section 24 is also connected to a changeover switch 122 of a changeover circuit 120. Further, the data outputs 110 of the two shift registers 102 are respectively connected in parallel to the two yJ switching switches 122 and 124 of the yJ switching circuit 120 as shown in the figure, and the data outputs 110 of the two shift registers 102 are connected in parallel to the two yJ switching switches 122 and 124 of the yJ switching circuit 120. It is connected to the.

ν) Changeover switch 116. and yJ 4+E circuit 1
20, its operation is iDJ g# by the shift clock conversion circuit 112. The two Y/N change switches 122 and 124 of the Y/N change circuit 120 can operate independently of each other, and each can selectively take the illustrated connection state and the opposite connection state. As a result, data can be read out alternately from the two memory arrays 100 via the two shift registers 102,
- Writing and reading data from the CPU of the overall control unit 24 to the 10,000 memory arrays 100 via the shift register 102 via the data line 28, while data is written from the other memory array 100 via the shift register 102. A frozen image can be read out to the output section 22.

These shift clock detection circuits 112 and address switching circuits 104 perform address and shift clock switching circuits 116 and 120.
In normal cases, the selection of yJ change is set from the overall DIM unit 24 in accordance with a synchronization signal from the manual control unit 14 or the output control unit 32. This allows memory array +0
When one of 0, for example, 1, contains old video value data from the analog to digital conversion circuit 16, the video signal data is read out from the other, in this case, s2. and is output to the iE section 38. When video signal data is written and read during the l field period, the address and shift clock selection states! The calm changes, and in the next one field period, the PII image signal data from the analog-to-digital conversion circuit 16 is input into one memory array, @2 in this example, and the image data is input from the input port 1. The signal data is read out and output to the correction section 38. This is repeated alternately in one field period.

As a result, time axis correction and rank noise reduction are performed on the video signal.

In other words, a video signal representing a still 1-image inputted from the input unit 10 is continuously supplied to the time axis correction all 18, and is alternately read into a pair of memory arrays 100 and read from them alternately. Output, ultimately the output FiIII
22 and the same image is repeatedly recorded on photographic paper, ie, the recording medium 58, it becomes possible to record the image on the recording medium 58 with the noise reduced to a certain extent.

Explain the operation. The image recording medium 58 is output by the output unit 22.
When recording a portrait on the recording medium 58, the input section 10 repeatedly reads the same frame's 9 [signal] from the magnetic disk, and the output section 22 repeatedly overwrites the same frame on the recording medium 58.

The read operation of the input section 1O is approximately synchronized with the synchronization signal generated by the output control section 32. The overall control unit 24 initializes the system, and the address switching circuit 104 supplies the video address VW ADR generated by the manual control unit H to the memory array lOO as the write address of the memory array 100. The shift clock switching circuit 112 controls the switch 11B to convert the analog/digital conversion circuit 16.
The signal line 20 from the input 108 of the shift register 102
and supplies a shift clock VW CLK to one of the shift registers 102, for example sl. The shift clock switching circuit 112 also. ! , I.J.
The switching circuit 120 is connected to the other shift register key 2. Therefore, when the vertical synchronization signal of the input 12 image signals falls, the overall control section 24 activates the write enable signal WE on the control line 26 to instruct 3 loading into the memory array ICO. As a result, writing to the memory array 100 is controlled by the input control unit 14.

Input unit lO from the video signal read from the magnetic disk
The input control unit 14 outputs control signals such as a clock and a 1-inclusive timing signal in synchronization with the synchronization signal separated by the
0 to the time axis correction i'1l18, and also generates the write address VW ADR of the memory array 100 in response to the water rotation signal and the vertical rotation signal. 104 to the memory array 100.

Therefore, the video signal VI appearing at the output 12 of the human power section IO
N is converted into digital signal data DIH by the analog/digital converter 24, and sequentially written into the memory array 1. In this way, one field of video signal data is written into the memory array s1.

The shift clock switching circuit 112 has a shift register s1.
Shift clock VRCLK is supplied to. Shift clock switching circuit 112 also connects switch 124 to output 110 of shift register cloud 1. As a result, the readout of the time axis correction unit 18 is controlled by the output control unit 32, and the readout of accumulated data from the storage area for one field of the memory array sl is limited to only seven times.

In accordance with the stable J, 1 wave number clock generated by the reference generator, the output control unit 32 outputs control signals such as clocks and read timing signals from the output 34 to the time axis correction unit 1B, and also causes the vertical synchronization signal VSYNC to rise. When the voltage drops, read addresses for the memory array 100 are sequentially generated in response to the water flow and the vertical synchronizing signal, and these are outputted to the memory array s1 by the address switching circuit 104.

In this way, video signal data is sequentially read out from the memory array Ill using the raster scanning method.
At step 8, the color and gradation are finalized. The corrected video signal is digital/analog variable 4! F! The signal is converted into an analog signal by the converter 32 and provided to the output section 22. This light is output to the CR7 screen of the output section 22 and exposed onto the recording medium 58 via the optical system.

In this way, video signal data for one field per field is sequentially read out from the time axis correction unit 18 over one field period from the vertical blanking signal, and is finally exposed onto the recording medium 58.

This read operation is performed until the next vertical cycle signal VSYNG falls. During this time, the video signal data from the input section 10 is input into the other memory array 2 in the same manner as described above. In other words, the shift clock switching circuit 112 switches the shift clock VW to the shift register port 2.
GLK is supplied and the switch 11B is connected to the shift register @2.

By the way, in this embodiment, the values of the color and gradation correction parameters set in the correction section 38 are determined based on the values at some sample points of the video signal data stored in one of the memory arrays 100 of the time axis correction section 18. The Lj elementary signal is taken into the CPU of the overall control unit 24 and the state of the original image is converted to τ1.
It is determined by The overall control section 24 determines the value of the correction parameter according to the photographing conditions, for example, the gradation characteristics of the camera used and the illumination condition, and sets the value in the correction section 38 through the cap 10. During acquisition of this pixel signal, the other memory array 100 of the time axis correction unit 18
A video signal is read from the output unit 22 through the correction unit 38, and is output and displayed on the PI image monitor device 56 of the output unit 22. In other words, during this time, the displayed video on the video monitor device 56 is
Frozen in a statue. Therefore, the displayed image on the monitor device 56 is not disturbed even during this pixel data collection.

Referring to FIG. 3, control edge 52 from output control section 32
When the vertical blanking signal VBLK rises to F (time 10), the CPU of the overall control section 24 is interrupted. The control unit 24 monitors the horizontal synchronization signal HSYNC from the input control unit 14 in response to this interrupt interruption, that is, within the vertical blanking period, and when it detects the fall (time tl), controls the A frame fixing signal or freeze signal is output to the edge 26. As a result, the write enable signal -E is erased and the occupancy of the memory array 100 is stopped.

7 trace switching circuit +04 is connected to one memory array 10.
0. For example, as the preemption address of Lu 1, the overall control unit 2
The detection circuit 112 controls the switch 11B to shift the data bus 28 from the overall control unit 24 in the - direction. register s1 man power 1
08 and supplies the shift clock CPU CLK to the shift register Il. As a result, the memory array Ill is occupied by the overall control unit 24.
From now on, it will be controlled. Therefore, for example, data representing a desired portrait, such as a test pattern image, can be generated by the CPU of the overall control unit 24, and the image data can be loaded into the memory array s1.

When reading from memory array lo 1, whole system 1 part 24
is the shift clock y) yJ switching W by the detection circuit 112
8120 (7) Sui-/su122 e ;uln
L, total+ljl '8 Fm 24 or connect the runo data path 28 to the output 110 of the shift register 11. The overall control unit 24 generates a read enable signal RE for the memory 7 array Il and an address CPU ADR of the sampling square in the memory array cloud I on the control line 26. The read address CPUADR is supplied to the memory array 111 by the address switching circuit 104, and the pixel data at the designated address is read from the memory array cloud I to the shift register H. This is serially outputted from the shift register 81 in response to the shift clock CPU CLK, and outputted to the data bus 28 through the switch 122.

The overall control unit 24 determines the correction parameter A1 according to the shooting conditions of the original image using the pixel data collected from the 12 image signal data of the memory array exposure 1, and sets this to the correction unit 38 through the control line 40. do. During this pixel signal collection, the shift clock switching circuit 112 of the time axis correction unit 18 connects the switch 124 of the switching circuit 120 to the output 110 of the other shift register 2, and
The read a clock VW_CLK from s2 is supplied to the shift register s2. Then, a video signal is read out from the memory array $2 through the correction section 38 to the output section 22, and is output and displayed on the video monitor device 56 of the output section 22.

The two memory arrays 100 are connected at the timing as described above.
When switching between writing and reading, on the reading side, the switching occurs during the vertical blanking period, so the monitor image of the output section 22 is not disturbed. Because of this, there is a blanking period after the end of data transfer to the memory array 100, and no data is lost.

When the overall control unit 24 sets the value of the correction parameter in the correction unit 38, the overall control unit 24 returns to the memory array 10 at the aforementioned timing.
Unfreeze 0. As a result, the video signal from the input section 10 is read into the pair of memory arrays 100 of the time axis correction section 18 in an alternating manner and read out alternately, and the time axis is corrected.

The correction unit 38 compensates the video signal data DOUT read out from the memory array 100 according to the correction parameters set by the overall control unit 24 in this way. This is converted into a corresponding analog signal by the digital/analog conversion circuit 44 and sent to the video monitor device 5 of the output section 22.
B or recording CRT.

Effects As described above, according to the present invention, the two memory buffers of the time axis correction circuit are used to freeze the output video to the video monitor 'A using one of the buffers, while the output video to the video monitor 'A is frozen. By accessing the buffer from the processing system, p-image signal data can be acquired without disturbing the displayed image on the video monitor. Further, using this, a desired image such as a test pattern can be loaded from the processing system into the memory buffer.

[Brief explanation of the drawing]

FIG. 1 is a machine block diagram showing the time axis correction section in the embodiment shown in FIG. 2, especially the part related to the end 1J, and FIG. 2 is a schematic diagram showing the embodiment of the still image recording device according to the present invention. Block Diagram. FIG. 3 is a timing diagram showing timing waveforms for explaining the operation of the device shown in FIG. m1. Explanation of symbols of main parts 14 Input control section 1B, Time axis correction section 24, Overall control g# section 32, Output control section 38, Correction section 5B, Monitor device 100 , ,Memory 7 Ray 104 , ,Address switching circuit +12 . ,,Shift clock! IIJ conversion circuit 11B,,
, Gino change switch +20. , , Gino Replacement Circuit Patent Applicant '7'l' Togushin Film Co., Ltd.
Rito Satori Furikumaru+l+ Takao

Claims (1)

[Claims] 1. A pair of storage means each capable of storing at least one field of data of a raster scan video signal representing a still life image, and the video signal stored in the storage means is stored at a predetermined speed. a time axis correction means for stabilizing the time axis of the video signal by regularly reading it; a processing means for controlling the time axis correction means and processing the video signal data; and data read from the storage means. and an output means for outputting the video signal data as a visible image, and when reading or writing video signal data from the processing means into one of the pair of storage means, the processing means reads the video signal data from the other one of the pair of storage means. A still image recording device characterized in that the time axis correction means is controlled so as to repeatedly read out video signal data stored therein from the storage means and supply it to the output means. 2. A still image recording device according to claim 1, wherein the output means includes a video monitor device that displays the visible image as a soft copy. 3. The apparatus according to claim 1, further comprising a correction means connected to the output of the time axis correction means and correcting the video signal data output from the time axis correction means according to correction conditions. The processing means reads the video signal data stored therein from one of the storage means, determines the correction condition based on the read video signal data, and applies the determined correction condition to the correction condition. A still image recording device characterized by being set as a correction means. 4. The apparatus according to claim 1, wherein the processing means writes data of a test pattern image into one of the storage means as a visible image to be outputted to the output means. Recording device. 5. The apparatus according to claim 1, wherein the processing means performs switching between reading and writing of the pair of storage means within a vertical blanking period of the screen video signal. Still image recording device.