JPS6336700B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiver for communication using frequency spread technology, and particularly to a receiver used in a communication system that uses communication satellites to exchange data or messages intermittently.

Conventionally, when transmitting data using communication satellites, it has been common practice to allocate specific lines for data in advance, and recently demand assignment methods, in which allocation is made in response to requests, have been put into practical use. However, data handled in data transmission generally requires a short time for one transmission unlike voice signals, and although it relies on a demand assignment system, it is uneconomical to monopolize a line for a certain period of time. However, when transferring files between computers, a large amount of data may be continuously transmitted for a considerable period of time, but this case is excluded from the purpose of the present invention.

On the other hand, a wireless packet method can be applied to satellite communication as a data transmission method. The simplest wireless packet method is called the Aloha method, in which data is sent randomly in the form of packets, and if the data overlaps in time with other packets using the same frequency band (collision), retransmission is repeated. be. This method is excellent in that it matches the characteristics of the data signal mentioned above and the equipment is simple, but the line throughput is low (about 18% at most) due to burst collisions and retransmissions, and it is difficult to use for satellite communication. However, since the distance between the earth and the satellite is approximately 40,000 km, it takes time to detect and retransmit collisions, which may limit transmission capacity or complicate data processing on the receiving side. It's also big. The slotted Aloha method, which is an improved version of the Aloha method, can improve throughput by up to two times, but since the distance between the earth and the satellite changes from moment to moment, the problem is how each station maintains the "slot". The problems associated with collisions and retransmissions are the same as with the Aloha method.

In order to solve the above-mentioned problems, various methods called reservation methods have recently been proposed, but all of them have the disadvantage of complicating the transmitter/receiver device.

In order to avoid the above-mentioned problems in data transmission using communication satellites, it has been proposed to use a frequency spreading method. For example, Masamura et al. ``Configuration and characteristics of microwave small-capacity station communication system using satellite'' IEICE Technical Report CS80-62, or Yokoyama et al. ``Digitalized SSRA device for satellite communication'' IEICE Technical Report CS80-106. There are examples.

Although the frequency spread method has problems in terms of effective use of the transmission path, it is not that inferior compared to the low throughput of the Aloha method, and since it is a method based on the fact that signals overlap in the same frequency band, This method is advantageous in that it eliminates the problems of collisions and retransmissions mentioned above, and furthermore, by matching the characteristics of the data signal mentioned above, a great effect can be expected in terms of effective use of the line.

The problem with implementing such a frequency spreading method is that since frequency spreading and despreading are performed on top of normal modulation and demodulation, the equipment, especially the receiving equipment, becomes complex, and the problem is that Since each signal must be spread with a different code sequence in order to identify the be.

Therefore, an object of the present invention is to realize a communication system using a frequency spread method using only a single or a small number of code sequences in order to communicate intermittent data or messages via a communication satellite. At the same time, it is an object of the present invention to obtain a receiving device that improves the expandability of the device and communication system and also realizes the simplification of the device.

That is, according to the present invention, a plurality of receiving circuits of the same type are used to establish reception synchronization for a signal frequency-spread by a certain specific code sequence (for example, A) and restore the despread original signal. Then, a certain receiving circuit among these receiving circuits receives a certain received signal (B
During the period when reception synchronization is established with respect to the signal B, other receiving circuits spread the frequency of signal B using code sequence A that has a phase that is identified as the same as the phase of code sequence A that is frequency-spreading the signal B. A frequency spread signal receiving apparatus having means for prohibiting reception synchronization with respect to a spread signal is obtained.

In the receiving device as described above, the N receiving circuits can simultaneously receive N different signals frequency-spread using the same code sequence A.
Therefore, any station that wishes to access a station having the receiving device of the present invention may use code sequence A, and the number N of receiving circuits can be expanded arbitrarily as long as line conditions permit. Not subject to restrictions. Being able to use the same code sequence helps simplify equipment, especially when using SAW in receiving equipment.
When using a matched filter using a surface acoustic wave (surface acoustic wave) element, there is no need to make the filter programmable and only one filter is required, which has a great advantage.

Next, the communication system targeted by the present invention will be explained as follows.

The first is a communication system consisting of one central station and many small stations. This corresponds to a form in which a large computer connected to the central station is shared with terminals connected to the small stations, and the small stations are always connected only to the central station.
Alternatively, the small stations may communicate via the central station, and the small stations may not communicate directly with each other. In this case, communication using the frequency spread method is applied only to data going from the small station to the central station, and in the opposite direction, a normal communication method using a broadcasting format (for example, time division multiplexing) may be used. The invention therefore applies to a central office receiving device.

The second consists of multiple big picture and many small picture,
A small station is a communication system that can communicate with any large station. The communication form between the large station and the small stations is the same as in the first system, but different code sequences are used instead of addresses to access each large station. However, if there is sufficient number of reception devices in a global station, it is possible for different global stations to use the same code sequence, and in this case, the address needs to be included in the data. A broadcasting format using time division multiple access is also possible for communication from a large station to a small station, and this can also include data communication between large stations.

The third is a communication system consisting of a plurality of medium-sized stations. Medium-sized stations communicate with each other, but it is a communication system where there is a possibility of receiving signals from two or more stations at the same time.
In principle, each medium-sized station is accessed using a unique code sequence. In this case, the present invention is applied to the receiving device of each medium-sized station.

The fourth case is a combination of the above three. In other cases, for example, a data communication system in which a large number of small stations communicate with each other and each station communicates with only one station at a time is uneconomical to apply to satellite communication, and is not the subject of the present invention. It's outside.

Next, a detailed explanation will be given with reference to the drawings.

Before entering into a detailed explanation of the present invention, we will briefly touch on the principle of the frequency spreading method. Fundamentally, frequency spreading methods include direct spreading methods and frequency hopping methods. Although the present invention can be applied to either method, the former will be explained below.

FIG. 1 is a diagram showing the principle of the frequency spreading method used in the receiving apparatus of the present invention, and shows the transmitting side and the receiving side. On the transmitting side, a transmitting side code sequence generator 11 generates a binary code sequence consisting of "1" and "0", and a spreader 12 converts the transmission original signal a into a transmission spread signal b. The original transmission signal a is already
This is a signal modulated by FM, FSK, PSK, etc., or a baseband signal. In the former case, diffuser 1
2 becomes a two-phase PSK modulator, and if it is the latter, it becomes an exclusive OR logic circuit, and the transmitted spread signal b is used to modulate the carrier wave with two-phase PSK (not shown).

On the receiving side, the receiving side code sequence generator 1
3 generates the same code sequence as the transmitting side code sequence generator 11, and the despreader 14 despreads the received spread signal c to obtain the received original signal d.

The received spread signal c is considered to be a combination of many signals transmitted from other stations in addition to the transmitted spread signal b, but the phase of the code sequence generated by the receiving side code sequence generator 13 is the same as the received spread signal c. Only when the phase of the code sequence included in the desired signal in .
This is because a code sequence with strong autocorrelation and weak cross-correlation is usually selected as the code sequence used for spreading.Conversely, obtaining a large number of code sets with such properties is the key to frequency spread communication. This is one problem with the method.

In the frequency hopping method, the two code sequence generators 11 and 13 can be considered to be replaced by a circuit that generates a multi-value sequence and a frequency synthesizer whose output frequency is controlled by the value of the circuit.

Also, the receiving side can be replaced with a matching filter designed for the corresponding code sequence. As will be described later, the present invention can be used in conjunction with a matching filter to achieve greater effects, but for ease of explanation, the explanation will be continued assuming the form.

The simplest and most effective code sequence generator is a PN sequence generator.

FIG. 2 shows the configuration of the PN sequence generator. The PN sequence generator shown in FIG. 2 includes an N-stage shift register 15 whose final stage generates a PN sequence output e, the contents of appropriate stages other than the final stage of this shift register 15, and the final stage PN system output. It consists of an adder 16 which performs addition of MODULO2 of e and feeds back to the first stage of the shift register 15, and is driven by a clock f. Specifically, the adder 16 is an exclusive
It is an OR logic circuit. Various code sequences can be generated by appropriately selecting a feedback circuit, and among these, the sequence with the maximum repetition period is called the M sequence.
It has a repetition period of 2 ⁿ −1 chips.

FIG. 3 shows the autocorrelation characteristics of the M sequence of the PN sequence. In other words, two identical PN sequences are compared chip by chip while shifting their phases, and the difference between the number of matches and the number of mismatches is calculated and graphed. Of course, when the phases of the two match, it is 2 ⁿ -1. However, if the phase is shifted by one chip or more, the number of matches becomes almost equal to the number of mismatches, and the number of mismatches is greater by one. The reason why 2 ⁿ -1 coincidence is obtained again when the chip phase is shifted by 2 ⁿ -1 is due to the periodicity of the PN sequence. However, when n is 9 stages, only 48 types of such M sequences are obtained, and when n is 10 stages, only 60 types are obtained, and there is no guarantee that the mutual correlation is small. Therefore, as a means to obtain a large number of code sequences, a method such as combining two PN sequences of the same period (Gold code) is used.

When spreading an original signal using a code sequence such as the one described above, it is convenient for various reasons to make one bit of the original signal coincide with the period of the code sequence or an integral multiple thereof. In any case, the transmitting side can spread the information using a simple circuit like this.

However, the problem is on the receiving side. As shown in Figure 3, the PN sequence or similar code sequence is characterized in that the correlation becomes almost 0 if the phase is shifted by even one chip. Therefore, the despreading code sequence that should be prepared on the receiving side is The code sequence must be the same as the code sequence used in the first step, and must also completely match the phase when actually received. Therefore, it is essential to establish reception synchronization.

FIG. 4 shows the configuration of a delay-lock type discriminator that is commonly used as a conventional receiving circuit. This figure corresponds to that of FIG. The received spread signal g is branched into three parts and applied to despreaders 21, 22 and 23. These three despreaders are supplied with sequences h, i, and j whose phases are slightly shifted from the receiving side code sequence generator 24, and these are applied to, for example, the nth stage of the n-stage shift register 15 in FIG. ,
It may be considered that the contents of the n-1st and n-2nd rows are output.

The outputs of the despreaders 21, 22, 23 are passed through band filters 25, 25', 2 with bands suitable for the original signal.
5″ respectively.If the despreader 21,
If the phase of the code sequence added to 22 and 23 is correct, the despread result becomes a narrow band original signal and can pass through the band filter 25. However, if the phase of the code sequence is incorrect, the band It is impossible to pass because it remains wide.

Since the band filter 25' and the like are made to be suitable for the original signal, they have an integral effect on the code sequence over one period or an integral multiple thereof.
The amplitude of its output is similar to FIG. Therefore, the envelope detectors 26, 26', 26'' can obtain a DC output (including noise, interference components, etc.) having characteristics close to those shown in FIG.

Figure 5 shows the discriminator (fourth
FIG. 3 is a diagram showing the phase characteristics of the output of FIG. The output k of the envelope detector 26 is monitored by a level detector 27 having a threshold level TH as shown in the figure, and if the level of the output k exceeds the threshold, a synchronization establishment signal l is output and synchronization is established. The information is transmitted to the control circuit 28. Envelope detector 26' and 2
The outputs of the outputs 6'' and 26 have a phase that is about one chip different from each other, and exhibit characteristics as shown in FIG.
At this time, by combining the outputs of the detector 26' with opposite polarities, the output m can have discriminator characteristics symmetrical with respect to the origin 0 as shown in FIG. A clock signal r is added to the voltage controlled oscillator 31 and drives the code sequence generator 24 via the synchronization control circuit 28 and the signal q.
By configuring a phase-locked loop circuit that controls the frequency of , it operates so that the origin 0 of the graph of the characteristics of , shown in FIG. 5, is a stable point.

The contents of the n-stage shift registers in the code sequence generator 24 are monitored by the phase detector 32 as n parallel signals s, which detect a particular pattern, that is, a phase shift corresponding to a transition between bits of the original signal. When the pattern is established, a control pulse t is generated.

The synchronization control circuit 28 reduces the phase of the code sequence generated by the code sequence generator 24 by 1 by deleting one clock from the clock signal r every time the control signal t is applied until the synchronization establishment signal l is received. Delay chip by chip. That is, it is possible to sweep the phase of the despreading code with respect to the received spread signal and search for a point where the phases match.

When reception synchronization is established, the desired received original signal u is obtained from the output of the bandpass filter 25. however,
The signal u obtained here is an FM or PSK signal and not a baseband signal, so
Demodulation operation is required at the subsequent stage.

FIG. 6 shows a synchronous control circuit (fourth synchronous control circuit) related to the present invention.
It is a figure which shows the structure of 28) of a figure. The same symbols are attached to the same signals as in FIG. 4, which represent the signals. The synchronization control circuit is composed of various circuits, but its main functions are a sweep operation for establishing synchronization, determination of establishment of synchronization, and protection after establishment.

The sweep operation for establishing synchronization is performed as follows. The control signal t, which is the output of the phase detector (corresponding to 32 in Fig. 4; this number is shown in parentheses in the figure, and the same applies hereinafter), is output from the monostable monomulticircuit for each period of the code sequence. added to 34, 1
A prohibition signal v having a width equivalent to a chip is generated, and is supplied via a gate circuit 35 to a gate circuit 36 that gates a clock signal r generated from an oscillator (31 in FIG. 4), thereby deleting one cycle of clock. A clock signal w is generated. clock signal w
is reduced to a frequency of 1/M by the 1/M frequency divider 37 (however, M is a positive integer and may be 1) and becomes a signal q, which is sent to the code sequence generator (24 in Figure 4). . Therefore, the code sequence generator is shifted in the direction of phase lag by 1/M chips for each period of one code sequence.

Determination of establishment of synchronization and protection after establishment are performed as follows. When the level detector (27 in FIG. 4) generates the synchronization establishment signal l, the output x of the synchronization protection circuit 33 is converted to the inhibition signal y by the inverter 38.
Therefore, the gate circuit 35 is closed. As a result, the prohibition signal v to the clock gate circuit 36 is no longer supplied, and the clock signal r becomes the clock signal w, and as a result, the sweep is stopped, and the phase locked loop circuit shown in FIG. Fine phase adjustments are made to the point, and reception synchronization is finally established and protected.

The receiving circuit centered on the delay-lock type discriminator has been explained in some detail above, and the present invention will be explained based on this.

FIG. 7 is a block diagram showing the configuration of an embodiment of the present invention, in which the number N of receiving circuits is three.

The first receiving circuit 41 is a circuit that is supplied with a received spread signal (corresponding to g in FIG. 4), performs reception synchronization, and restores the despread received original signal (corresponding to u in FIG. 4). When a lock-type discriminator is used, the circuit shown in FIG. 4 corresponds to this. When this first receiving circuit 41 establishes synchronization of one of the signals included in the received spread signal g, it restores the received original signal u, and pulses corresponding to a specific phase of the synchronized code sequence are added to the period of the sequence. Correspondingly, it appears as control signal A. This signal is similar to the control signal t at the output of the phase detector 32 of FIG. 4, except that it appears only when synchronization is established.

The second and third receiving circuits 42 and 43 are identical in configuration to the first receiving circuit 41, and restore the received original signals u' and u'', respectively, and output control signals A' and A'' when synchronization is established. It has the function of If the received spread signal g contains only a single signal,
All three receiving circuits will attempt to establish synchronization on this signal, but in the present invention the first, second and third coincidence detectors 44, 44',
44'' is used to prevent this and only a single synchronization circuit is controlled to be allowed to establish synchronization.

If two signals are input, only two of the three receiving circuits will establish synchronization, and if three signals are input, each of the three receiving circuits will establish synchronization with a different signal. If three or more signals are input, only the three signals with which synchronization was established first are received, and the others are considered to be mere interference signals even if they use the same code sequence. Such control is carried out by the coincidence detection circuits 44, 44', 4.
This is done by control signals B, B', B'' which are the outputs of 4''. The details of this coincidence detection circuit will be explained next, and the priority order control circuit 45 and the three outputs C, C', and C'' will be explained later.

FIG. 8 shows a synchronization control circuit (28 in FIG. 4, that is, the circuit in FIG. 6) in the first receiving circuit (41 in FIG. 7) when a delay-lock discriminator is used as the receiving circuit in the present invention. 7) and a coincidence detector (corresponding to 44 in FIG. 7). FIG. The former is to the right of the dashed line,
The latter is located in front of the left hand side of the dashed line with the reference numerals 28 and 44 in parentheses. In FIG. 8, when the level detector (27 in FIG. 4) detects that the phases of the code sequences roughly match, the synchronization establishment signal l becomes "1", and the output x of the synchronization protection circuit 33 also becomes "1". 1" and the digital sweep operation is stopped as described above, but at the same time, the output x is applied to the gate circuit 51 and is the output pulse of the phase detector (32 in FIG. 4). control signal t
passes through to trigger the monostable monomulti circuit 52 and output the control signal A. The pulse width of control signal A is approximately 1 chip, but this has an important effect on determining whether this receiving circuit is synchronized to the same signal as other receiving circuits, so it is important to consider the operating conditions of the receiving device. It is necessary to set them carefully.

Control signals A' and A'' from other receiving circuits (42 and 43 in FIG. 7) are combined in an OR circuit 53 and compared with the control signal t output from the phase detector in an AND circuit 54 for coincidence detection. , if even some of them match in time, they are added to the retriggerable monomulti circuit 55, and generate an inhibit pulse B with a width slightly wider than one period of the code sequence.

Under the above conditions, there is a high possibility that the level detector (27 in Figure 4) sets the synchronization establishment signal l to "1", but the above-mentioned inhibit pulse B is used instead of the inverter 38 in Figure 6. In order to keep this output y' at "1", NAND gate circuit 35 remains open and the sweep operation continues.

That is, as long as the output pulse t from the phase detector (32 in FIG. 4) is close to the control signals A', A'' output from the other receiving circuits 42, 43, the judgment of the synchronization protection circuit 33 will be as follows. As a result, reception synchronization for signals frequency-spread by a code sequence whose phase is identified as identical to the phase of the code sequence with which the signal with which other receiving circuits have established synchronization is spread is ignored. It will be banned.

Returning to FIG. 7, the priority order control circuit 45 is a circuit for eliminating inconveniences when two or more receiving circuits coincidentally start from substantially the same state. In other words, in such a case, two or more receiving circuits simultaneously establish reception synchronization for one received signal, and as a result, synchronization establishment is prohibited at the same time by the action of the above-mentioned coincidence detector. This is because there is a possibility that it will be repeated. The priority order control circuit 45 monitors the control signals A, A', A'' of each receiving circuit, and if there are multiple receiving circuits for which synchronization has not been established, always puts only one in a state where synchronization can be established. The other is to generate control signals C, C', C'' that inhibit synchronization establishment operations. This control signal is applied to, for example, the synchronization protection circuit 33 shown in FIG.

A receiving device using a delay-lock type discriminator has been described above, and although this device achieves the purpose explained at the beginning, its drawback is that it takes a long time to establish synchronization. To improve this, a matching filter can be used for reception.

FIG. 9 is a diagram showing the basic configuration of a three-stage matching filter used in the receiving apparatus of the present invention. In the figure, the spread signal D is applied to a column of delay circuits 61, 61' corresponding to the chip length. The outputs of each stage are combined through weighting circuits 62, 62', and 62'', resulting in an output E. Considering a baseband multilevel code sequence as a spread signal, the weighting circuit has a weighted resistance corresponding to the multilevel value. (including a polarity conversion circuit in some cases), and is set so that when one cycle of the series is stored in the delay circuit array, they are all added to the composite output with the same polarity.Therefore, the output E is the series This is a pulse that occurs every cycle.

FIG. 10 is a diagram showing the waveform of the output E, and the output E is shown by a solid line. If this code sequence is modulated by the original signal in units of periods, the polarity is reversed according to the original signal as shown by the broken line in the figure, so that the original signal can be restored.

If the spread signal D is a spread signal based on frequency hopping, the weight circuit 62 is replaced by a synchronization circuit corresponding to the hopping frequency.

When processing spread signals in the baseband, the delay circuit array can be replaced with elements such as CCDs, but when processing in the IF band, these load circuits must also be built into the SAW element. Therefore, if multiple signals are to be received using the same code sequence as in the present invention, it is not necessary to create matching filters that correspond to different code sequences for each received signal, as in the conventional system. This is a major advantage in that one type of element can be used for all purposes.

When a large number of spread signals are input to such a matching filter, the outputs for each signal are combined and output. That is, a plurality of signals can be received by selecting peaks that appear at different phases and at a period equal to the sequence period from these outputs.

FIG. 11 is a diagram showing the configuration of an embodiment of the present invention when a matching filter is used. In the figure, a received spread signal D containing a large number of signals is applied to a matching filter 63 in this case, resulting in an output signal E which is a combination of pulses as shown in FIG.
receiving circuits 71, 72, and 73. The receiving circuit 71 and the coincidence detector 74 are shown with different numbers because their contents are different from those in the case where a delay-lock type discriminator is used, but the overall structure is almost the same as in FIG. 7 except for the addition of a matching filter 63. be.

FIG. 12 is a diagram showing in detail the matching filter 63, receiving circuit 71, and coincidence detector 74 of the device shown in FIG. 11 using a matching filter, which is another embodiment of the present invention. be. Note that areas 71 and 74 are distinguished by broken lines. In the figure, the output of the matched filter 63 passes through a gate circuit 75, a level detector 76 detects a peak exceeding a specific threshold, and passes through a gate 77 as a detection pulse F.
Then, the self-running counter 78 having the same period as the code sequence is reset. The counter 78 is driven by the clock synchronous circuit 79 and the clock of the output G of the oscillator 80, but its contents are controlled by the decoder 8.
1, and exactly one cycle after the counter is reset, the gate signal generator 82 generates a 1-bit wide gate signal H and applies it to the OR circuit 83.

On the other hand, the detection pulse F is applied to the synchronous control circuit 84, thereby changing the control output I, which has been kept at "1", to "0". As a result, gate circuit 75
After the detection pulse F is detected once, it will not open unless the gate signal H is supplied via the OR circuit 83. If the level detector 76 detects a peak exceeding the threshold level again when the gate signal H is supplied, the synchronization control circuit 84 assumes that synchronization has been established and continues to keep the control output I at "0". , on the other hand, opens the gate 85 and supplies the gate signal H as the control signal A to other receiving circuits.

Here, if the level detector 76 does not detect a peak, the control output I is immediately returned to "1" and another peak is searched for. If no peak is detected after synchronization is established, the situation is checked according to the synchronization protection conditions set in advance in the synchronization control circuit 84, and since no peak is detected continuously, it is determined that synchronization has been lost. Set the control output I to “1”,
Gate circuit 85 is closed.

While synchronization is established, the gate 75 periodically selects only the corresponding peak and supplies it to the subsequent circuit as the received original signal J (corresponding to u in FIG. 11), while the clock synchronization circuit 79 The frequency of the oscillator 80 is stabilized by extracting the clock component of the oscillator 80.

When the other receiving circuits establish synchronization, the gate signals being used are supplied as control signals A' and A'', which are combined by the NOR circuit 86 and used as the inhibition signal K to the gate circuit 77. As a result, this receiving circuit can avoid establishing synchronization overlapping peaks to which other receiving circuits are already synchronized.In other words, the coincidence detector 74 in FIG. 11 corresponds only to the NOR circuit 86 in FIG. are doing.

Here, the conditions of the communication system using the receiving device of the present invention will be clarified.

The first is that the phase of the code sequence used to spread the original transmission signal is random for each station. This should naturally occur under normal conditions, and if the phases of the code sequences of the received signals from two stations are the same, the received original signal after restoration will be impossible to demodulate and will not be received. It will be the same as if it were deleted. Only in this case is a retransmission due to collision similar to the Aloha method required. And in this case, retransmission needs to choose a different phase.

Second, as mentioned earlier, this communication system provides 1
The length of data transmitted each time is relatively short. When data continues over a long period of time, a slight difference in the transmission clock frequency between transmitting stations causes them to drift relative to each other, increasing the probability that their phases will overlap with other signals. In this case, due to the action of the coincidence detection circuit, both the receiving circuit for the overlapping signals and the receiving circuit for the overlapping signals become out of reception synchronization.

In other words, the communication method using the receiving circuit according to the present invention is similar to the Aloha method in that if the phases overlap (collide), communication is impossible and retransmission is required, but the probability of collision is greater than the code sequence. It has the characteristic that the longer it is, the more it decreases (the process gain as a frequency spreading method also increases), and can be ignored in practice.
Furthermore, if all the small stations had some standard for the clock and transmission timing for receiving signals transmitted from the large station in broadcast format, the above-mentioned problems would be largely eliminated.

Third, the method of the present invention considers satellite communication, and it is difficult to apply this method directly to a terrestrial wireless method. This is because on the ground, there are distance issues due to varying distances between stations, echoes due to reflections from ground structures, etc., and as mentioned above, it is often difficult to use the same code sequence repeatedly at different phases. This is because it seems that Furthermore, the autocorrelation characteristics shown in Figure 3 are for the case without modulation, and the correlation when the original signal is spread, that is, the correlation characteristics when the spreading code sequence is modulated by the original signal, is due to the cross-correlation. One of the reasons for the above-mentioned difficulty is that there is significant deterioration in

Although the above two embodiments have been described with reference to the case where there are three receivers, it goes without saying that the number of receivers may be N (plural) as usual.

As described in detail above, by using the receiving device of the present invention, it is possible to receive multiple spread signals using the same code sequence, and the receiving device can be greatly simplified, especially when a matching filter is used. can.

The device of the present invention is effectively applied when a data transmission communication system using a communication satellite is realized by a frequency spreading method, and the effects of the present invention are large.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle of the frequency spreading method used in the receiver of the present invention, Fig. 2 is a diagram showing the configuration of the PN sequence generator, and Fig. 3 is a diagram showing the configuration of the PN sequence generator.
Figure 4 is a diagram showing the autocorrelation characteristics in a series, Figure 4 is a diagram showing the configuration of a delay-lock type discriminator that has been commonly used as a receiving circuit in the past and is also related to the present invention, and Figure 5 is a diagram showing the configuration of a delay-lock type discriminator that has been commonly used as a receiving circuit in the past and is also related to the present invention. FIG. 6 is a diagram showing the phase characteristics of the output of the discriminator, FIG. 6 is a diagram showing the configuration of the synchronization control circuit of the discriminator in FIG. 4, FIG. 7 is a diagram showing the configuration of an embodiment of the present invention, FIG. 8 is a diagram showing a configuration example of a synchronization control circuit and a coincidence detector when a delay-lock type discriminator is used as a receiving circuit in the present invention, and FIG. 9 is a diagram showing a configuration example of a matching filter used in the receiving device of the present invention. A diagram showing an example of the basic configuration of
FIG. 10 is a diagram showing the output waveform of a matching filter, FIG. 11 is a diagram showing the configuration of an embodiment of the present invention when a matching filter is used, and FIG. 12 is a diagram showing a part of the device in FIG. 11. It is a diagram showing details. Explanation of symbols: 41, 42, 43 are receiving circuits, 4
4, 44', 44'' are coincidence detectors, 45 is a priority control circuit, 71, 72, 73 are receiving circuits, 74, 7
4' and 74'' are coincidence detectors, g and D are received spread signals, u and J are received original signals, and E is a matching filter output, respectively.

Claims (1)

[Claims] 1. A plurality of receiving circuits that establish reception synchronization for a signal frequency-spread by a certain specific code sequence A and restore the despread original signal, and a certain receiving circuit among these plurality of receiving circuits. During a period in which reception synchronization is established for a certain received signal B, another receiving circuit uses a code having a phase that is identified as the same as the phase of the code sequence A that is frequency-spreading the received signal B. A frequency spread signal receiving apparatus comprising: means for prohibiting reception synchronization for a signal frequency spread by series A.