JPS6336562A - Solid-state image sensing device - Google Patents
Solid-state image sensing deviceInfo
- Publication number
- JPS6336562A JPS6336562A JP61180404A JP18040486A JPS6336562A JP S6336562 A JPS6336562 A JP S6336562A JP 61180404 A JP61180404 A JP 61180404A JP 18040486 A JP18040486 A JP 18040486A JP S6336562 A JPS6336562 A JP S6336562A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- light
- solid
- output means
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000003384 imaging method Methods 0.000 claims description 28
- 230000005669 field effect Effects 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 abstract 3
- 238000012216 screening Methods 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 241000272201 Columbiformes Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は固体撮像装置、特に固体電荷転送素子いわゆる
ＣＴＤ構成を有する固体撮像装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device, and particularly to a solid-state imaging device having a solid-state charge transfer device, so-called CTD configuration.
本発明はＣＴＤ構成による固体撮像装置におけるその各
部の電極、配線、遮光性導電膜等の複数の導電膜を具備
する固体撮像装置において、その信号出力を取り出す出
力手段における特に少なくとも最終段の絶縁ゲート型電
界効果トランジスタ（以下ＭＯ３）ランジスタと略称す
る）すなわち大電流を取り扱うＭＯＳトランジスタにお
けるゲート電極を、上述した固体撮像装置における複数
種の導電層の積層によって構成してこのゲート電極にお
ける抵抗の存在による遅延の発生を効果的に回避する。The present invention relates to a solid-state imaging device having a CTD configuration, which is provided with a plurality of conductive films such as electrodes, wiring, and a light-shielding conductive film in each part of the solid-state imaging device. The gate electrode of a type field effect transistor (hereinafter abbreviated as MO3 transistor), that is, a MOS transistor that handles a large current, is constructed by laminating multiple types of conductive layers in the solid-state imaging device described above, and due to the presence of resistance in this gate electrode. Effectively avoid delays.
ＣＴＤを用いた固体撮像装置として第１図に示すように
半導体基板（１）、例えばシリコン基板上にＣＴＤ構成
による撮像手段（２）と同様にＣＴＤ構成により撮像手
段（２）によって受光量に応じて得てここにＮ禎された
信号電荷を順次転送する電荷転送手段（３）例えば水平
シフトレジスタとこれよりの信号電荷を電気的出力信号
として取り出す出力手段（４）を具備し、この出力手段
（４）が例えばフローティングデイフュージョン型等の
ように、その出力手段にＭＯＳを具備してなるものがあ
る。このような固体撮像装置においては、通常その表面
にアルミニウムＭ等の遮光性導電膜（５）が被覆され撮
像手段（２）の特に受光部となる部分に受光用開口部（
６）が穿設されてなる。また、このような固体撮像装置
におけるＣＴＤ構成を有する部分例えば電荷転送手段（
３）の作成は、第４図に示すように例えばシリコン半導
体基板（１）の−主面（１ａ）上に熱酸化によって５ｉ
０２よりなる所要の厚さの絶縁層すなわち誘電体層（７
）を形成し、これの上に例えば全面的に低比抵抗の第１
の多結晶シリコン半導体層を被着形成し、これをフォト
エツチングによって所定のパターンにエツチングして所
要の間隔を保持して転送方向にて第１の転送電極（８）
下における誘電体層（７）に比し厚さの大なる誘電体層
（７Ｆ）を形成する。その後各第１の転送電極（８）間
の厚い誘電体層（７Ｆ）上を含んで同様に低比抵抗の第
２の多結晶シリコン半導体層を被着し、これをフォトエ
ツチングして不要部分を排除して各第１の転送電極（８
）間の厚い誘電体層 （７Ｆ）上に第２の転送電極（９
）を形成する。As shown in FIG. 1, a solid-state imaging device using a CTD includes an imaging means (2) having a CTD configuration on a semiconductor substrate (1), for example, a silicon substrate, and an imaging means (2) having a CTD configuration according to the amount of light received. The output means includes a charge transfer means (3) for sequentially transferring the signal charges obtained and transferred here, for example, a horizontal shift register, and an output means (4) for extracting the signal charges from this as an electrical output signal. There is a type (4), such as a floating diffusion type, in which the output means is equipped with a MOS. In such a solid-state imaging device, the surface thereof is usually coated with a light-shielding conductive film (5) made of aluminum M or the like, and a light-receiving aperture (particularly in the part that becomes the light-receiving part) of the imaging means (2) is provided.
6) is drilled. In addition, a portion having a CTD configuration in such a solid-state imaging device, such as a charge transfer means (
3), for example, as shown in FIG.
An insulating layer, that is, a dielectric layer (7
), and on top of this, for example, a first layer of low resistivity is formed on the entire surface.
A polycrystalline silicon semiconductor layer is deposited and etched into a predetermined pattern by photo-etching to maintain a required spacing and form a first transfer electrode (8) in the transfer direction.
A dielectric layer (7F) is formed which is thicker than the underlying dielectric layer (7). After that, a second polycrystalline silicon semiconductor layer of low resistivity is similarly deposited on the thick dielectric layer (7F) between each first transfer electrode (8), and this is photoetched to remove unnecessary parts. are removed from each first transfer electrode (8
) on the thick dielectric layer (7F) between the second transfer electrodes (9F)
) to form.
これら第１の転送電極（８）と第２の転送電極（９）は
、隣り合う電極を組として相互に電気的に連結され、隣
り合う紐間に２層のクロック電圧φ１．φ２を印加する
ことによって電荷転送を行うようにしている。また、こ
の電荷転送手段（３）上等には、第１図で説明したよう
にＡＱ等の配線及び電極を形成しく図示せず）、更に同
様にＡＱ等の遮光性導電膜（５）が５ｉ０２等の絶縁層
（１０）を介して被着される。また、半導体基板（１１
の電荷転送手段（３）の出力側にｌ’ｌＯｓトランジス
タ等が形成されて出力手段（４）が構成される。この出
力手段（４）を構成する例えば最終段のＭＯＳ ｌ−ラ
ンジスタは、第４図及び第５図に示すようにドレイン領
域りと、これを挟んでその両側に所要の間隔を保持して
ソース領域Ｓが選択的に不純物のイオン注入あるいは拡
散等によって形成される。そしてドレイン領１５Ｄとそ
の両側のソース領域３間上に誘電体層（７）の被着と同
時に形成したゲート絶縁層（１１）が被着され、これの
上に例えば電荷転送手段（３）の第１の転送電極（８）
と同時に形成した低比抵抗の第１の多結晶シリコン層よ
り成るゲート電極（１２）が横型に被着形成されてなり
・その一端部（１２ａ）から所要のゲート電圧が供給さ
れるようになされる。また、各ドレイン領域りとソース
領域Ｓとにそれぞれ例えば鳩より成る電極（１３）及び
（１４）がオーミックに被着される。これら電極（１３
）及び（１４） 、と前述した遮光性導電膜（５）とは
夫々の工程でＡＱを全面に蒸着し、フォトエツチングに
よって所要のパターンに形成し得る。These first transfer electrodes (8) and second transfer electrodes (9) are electrically connected to each other as a pair of adjacent electrodes, and a two-layer clock voltage φ1. Charge transfer is performed by applying φ2. Further, on this charge transfer means (3), wiring and electrodes such as AQ (not shown) are formed as explained in FIG. It is deposited via an insulating layer (10) such as 5i02. In addition, a semiconductor substrate (11
An l'lOs transistor or the like is formed on the output side of the charge transfer means (3) to constitute an output means (4). For example, the final stage MOS l-transistor constituting this output means (4) has a drain region and a source with a required spacing on both sides of the drain region as shown in FIGS. 4 and 5. The region S is formed selectively by ion implantation or diffusion of impurities. Then, between the drain region 15D and the source regions 3 on both sides thereof, a gate insulating layer (11) formed at the same time as the deposition of the dielectric layer (7) is deposited, and on this, for example, the charge transfer means (3) is deposited. First transfer electrode (8)
A gate electrode (12) made of a first polycrystalline silicon layer of low resistivity formed at the same time is deposited horizontally, and a required gate voltage is supplied from one end (12a) of the gate electrode (12). Ru. Furthermore, electrodes (13) and (14) made of, for example, doves are ohmically attached to each drain region and source region S, respectively. These electrodes (13
) and (14), and the above-mentioned light-shielding conductive film (5) can be formed by depositing AQ on the entire surface in each step and forming a desired pattern by photo-etching.
（１５）はチャンネルストップ領域である。(15) is a channel stop area.
このような構成による固体撮像装置において、その出力
手段（４）のＭＯＳ Ｉ−ランジスタのゲート部の幅し
たがってゲート電極の幅Ｗは、電荷転送手段（３）のパ
ターン等の兼ね合いによって比較的大に選定される。こ
れがためその端部（１２ａ）からゲート、電圧を印加す
る場合、ゲート電極（１２）の抵抗が問題となり、高周
波取り扱いにおいて遅延が生じ出力波形がなまり、撮像
画像の鮮鋭度が低下する。In a solid-state imaging device having such a configuration, the width of the gate portion of the MOS I-transistor of the output means (4), and thus the width W of the gate electrode, is relatively large depending on the pattern of the charge transfer means (3), etc. Selected. Therefore, when applying a voltage to the gate electrode from its end (12a), the resistance of the gate electrode (12) becomes a problem, causing a delay in handling high frequencies, blunting the output waveform, and reducing the sharpness of the captured image.
本発明は、上述した固体撮像装置における出力手段の、
特に最終段におけるＭＯＳ ）ランジスタすなわち大電
流を取り扱う必要の生じて（るＭＯＳ トランジスタに
おいてそのゲート部の遅延の問題を解決するものである
。The present invention provides an output means in the solid-state imaging device described above.
In particular, it solves the problem of delay at the gate of a MOS transistor in the final stage, that is, a MOS transistor that needs to handle a large current.
本発明は第１図で説明したように、半導体基板（１）上
に撮像手段（２）とこの撮像手段（２）によって受光量
に応じて得た信号電荷を転送する電荷転送手段（３）と
この信号電荷に応じた信号出力をとり出す出力手段とを
有し、この出力手段（４）がＭＯＳ ｌ−ランジスタに
よって形成され、さらに撮像手段（２）の配置部上に受
光用開口部（６）が穿設された遮光性導電膜（５）が形
成された固体撮像装置において、第２図にその要部の断
面図を示し、第３図にそのさらに要部の平面図を示すよ
うに、出力手段（４）の少なくとも最終段のＭＯＳトラ
ンジスタのゲート電極（１２）を電荷転送手段（３）を
構成する例えば第１の転送電極（８）と同一工程で形成
された下層の電極（１２Ａ）と、これの上に他の電極例
えば第２の転送電極（９）、電極（１３） （１４）あ
るいは遮光性導電膜（５）または配線（図示せず）等の
他の導電膜による上層電極（１２Ｂ）との積層構造とす
る。そしてこれら下層の電極（１２Ａ） と上層の電極
（１２Ｂ）とは、少なくとも夫々その両端すなわち給電
端部（１２Ａ）側の部分Ａとこれとは反対側の各部Ｂと
において電気的に連結する。As explained in FIG. 1, the present invention includes an imaging means (2) on a semiconductor substrate (1) and a charge transfer means (3) for transferring signal charges obtained by the imaging means (2) according to the amount of light received. and an output means for taking out a signal output according to the signal charge, this output means (4) is formed by a MOS l-transistor, and a light receiving opening ( In a solid-state imaging device on which a light-shielding conductive film (5) with holes 6) is formed, FIG. 2 shows a cross-sectional view of the main part, and FIG. 3 shows a plan view of the main part. In addition, the gate electrode (12) of at least the last stage MOS transistor of the output means (4) is connected to a lower electrode ( 12A) and other electrodes such as the second transfer electrode (9), electrodes (13) (14), or light-shielding conductive film (5) or other conductive film such as wiring (not shown). It has a laminated structure with the upper layer electrode (12B). The lower layer electrode (12A) and the upper layer electrode (12B) are electrically connected at least at both ends thereof, that is, at a portion A on the power feeding end portion (12A) side and at each portion B on the opposite side.
上述したように本発明構成においては、出力手段（４）
のＭＯＳのゲート電極（１２）を２眉構造としたことに
よって遅延の問題を解消できる。すなわちゲート電極が
従来のように１層構造による場合のゲート電極に関わる
等価回路は、第６図Ａに示す、ようにゲート電極におけ
る抵抗をＲとし浮遊容量をＣとして与える場合の時定数
回路に比し、本発明のそれは第６図Ｂに示す等価回路と
なり、例えば従来構成の時定数τがτ＝ＣＩ？であった
ものが、Ｒ
本発明構成によればて＝□とじて与えられる。As described above, in the configuration of the present invention, the output means (4)
The problem of delay can be solved by making the gate electrode (12) of the MOS transistor have a bibrow structure. In other words, when the gate electrode has a conventional one-layer structure, the equivalent circuit related to the gate electrode is a time constant circuit when the resistance at the gate electrode is given as R and the stray capacitance is given as C, as shown in Figure 6A. In contrast, the equivalent circuit of the present invention is shown in FIG. 6B, where, for example, the time constant τ of the conventional configuration is τ=CI? is given by R=□ according to the configuration of the present invention.
したがって高周波応答が早く出力波形が崩れたり歪みが
生じたりする恐れが回避される。Therefore, the high frequency response is fast and the fear that the output waveform will be distorted or distorted can be avoided.
さらに第２図及び第３図を参照して本発明による固体撮
像装置の一例を説明するも、第２図及び第３図において
第４図及び第５図と対応する部分には同一符号を付して
重複説明を省略する。図示の例では、半導体基板（１）
上に設ける出力手段（４）の例えば最終段のＭＯＳトラ
ンジスタのゲート電極（１２）を、電荷転送手段（３）
の第１の転送電極（８）と同時に形成した下層の電極（
１２Ａ）と、これの上に例えば電極（８）上を覆って形
成する５ｉ０２等の絶縁層の形成と同時に下層の電極層
（１２Ａ）上に形成した絶縁層（誘電体層）（７）を介
して、これの上に例えばＡＱよりなる遮光性導電膜（５
）の形成と同時に形成したＭより成る上層の電極（１２
Ｂ）とが積層された構成とする。そして第３図に示すよ
うに横型状に形成されたゲート電極（１２）の両端Ａ及
びＢにおいて上層の電極（１２Ｂ）すなわち遮光性導電
膜（５）の形成前に絶縁層（７）に、部分Ａ及びＢにお
いて窓開けを行ってここにおいて下層の電極（１２Ａ）
に上層の電極（１２Ｂ）が連接、すなわち電気的に接触
するように遮光性導電膜（５）の形成と同時に電極（１
２Ｂ）の形成を行う。Further, an example of the solid-state imaging device according to the present invention will be explained with reference to FIGS. 2 and 3. In FIGS. 2 and 3, parts corresponding to those in FIGS. to omit redundant explanations. In the illustrated example, a semiconductor substrate (1)
For example, the gate electrode (12) of the final stage MOS transistor of the output means (4) provided above is connected to the charge transfer means (3).
The lower layer electrode (
12A) and an insulating layer (dielectric layer) (7) formed on the lower electrode layer (12A) at the same time as forming an insulating layer such as 5i02, which is formed to cover the electrode (8). A light-shielding conductive film (5
) was formed at the same time as the upper layer electrode (12
B) has a laminated structure. As shown in FIG. 3, at both ends A and B of the horizontally formed gate electrode (12), before forming the upper layer electrode (12B), that is, the light-shielding conductive film (5), an insulating layer (7) is applied. Window openings are made in sections A and B, where the lower electrode (12A)
At the same time as the light-shielding conductive film (5) is formed, the upper layer electrode (12B) is connected, that is, in electrical contact with the electrode (12B).
2B) is formed.
上述した例においては出力手段（４）の最終段のＭＯＳ
ｈランジスタに関してのゲート電極を多層構造とした
場合であるが、出力手段（４）を構成する全ＭＯＳに関
してのゲート電極を同様の構成とすることもできる。In the above example, the final stage MOS of the output means (4)
Although the gate electrode for the h-transistor has a multilayer structure, the gate electrodes for all MOSs constituting the output means (4) can also have a similar structure.
上述したように本発明においては出力手段の少なくとも
大出力を扱う最終段のＭＯＳ Ｉ−ランジスタ、のゲー
ト電極を多層構造としたことによって時定数の低減化を
図ったので冒頭に述べた遅延の問題による出力波形のな
まりや崩れ、歪みを効果的に回避し得るものであり、高
周波を取り扱う固体撮像装置においてその利益は大きい
。そして、上述したようにＭＯＳ ）ランジスクのゲー
ト電極を多層構造とするものではあるが、各層は、固体
撮像装置の他部の各層、例えば遮光性導電膜、配線、電
極等と同時に形成するので製造工程数が増加することが
ない。As mentioned above, in the present invention, the time constant is reduced by making the gate electrode of at least the final stage MOS I-transistor that handles high output of the output means have a multilayer structure, so that the delay problem mentioned at the beginning is solved. It is possible to effectively avoid rounding, collapse, and distortion of the output waveform due to the above, and this is of great benefit in solid-state imaging devices that handle high frequencies. As mentioned above, although the gate electrode of the MOS transistor has a multilayer structure, each layer is formed at the same time as the other layers of the solid-state imaging device, such as the light-shielding conductive film, wiring, electrodes, etc. The number of processes does not increase.
第１図は固体撮像装置の構成を示す模式図、第２図は本
発明による固体撮像装置の一例の要部の拡大断面図、第
３図はさらにその要部の拡大平面図、第４図は従来の固
体撮像装置の要部の拡大断面図、第５図はその要部の拡
大平面図、第６図Ａ及びＢは従来及び本発明装置のゲー
ト電極に関わる等価回路図である。
（１）は半導体基板、（２）は撮像手段、（３）は電荷
転送手段、（４）は出力手段、（５）は遮光性導電膜、
（６）は受光用開口部、（１２）は出力手段の絶縁ゲー
ト型電界効果トランジスタのゲート電極、（１２Ａ）及
び（１２Ｂ）はその下層及び上層の電極である。FIG. 1 is a schematic diagram showing the configuration of a solid-state imaging device, FIG. 2 is an enlarged sectional view of a main part of an example of a solid-state imaging device according to the present invention, FIG. 3 is an enlarged plan view of the main part, and FIG. 4 5 is an enlarged sectional view of the main part of a conventional solid-state imaging device, FIG. 5 is an enlarged plan view of the main part, and FIGS. 6A and 6B are equivalent circuit diagrams relating to gate electrodes of the conventional device and the device of the present invention. (1) is a semiconductor substrate, (2) is an imaging means, (3) is a charge transfer means, (4) is an output means, (5) is a light-shielding conductive film,
(6) is a light receiving opening, (12) is a gate electrode of an insulated gate field effect transistor serving as an output means, and (12A) and (12B) are electrodes of the lower layer and upper layer thereof.
Claims (1)
荷を転送する電荷転送手段と上記電荷を出力信号として
取り出す出力手段とを有し、該出力手段は絶縁ゲート型
電界効果トランジスタで構成されてなり、上記撮像手段
の配置部上に受光用開口部が形成されてなる遮光性導電
膜が配されてなる固体撮像装置において、 上記出力手段の少なくとも最終段の絶縁ゲート型電界効
果トランジスタのゲート電極を、上記電荷転送手段を構
成する電極と上記遮光性導電膜と配線の中から選択され
た少なくとも２層で積層形成したことを特徴とする固体
撮像装置。[Scope of Claims] It has an imaging means, a charge transfer means for transferring a signal charge obtained by the imaging means according to the amount of light received, and an output means for extracting the charge as an output signal, and the output means is of an insulated gate type. In a solid-state imaging device comprising a field effect transistor and having a light-shielding conductive film formed with a light-receiving aperture formed above the arrangement portion of the imaging means, an insulated gate at least in the final stage of the output means; A solid-state imaging device characterized in that a gate electrode of a type field effect transistor is formed by laminating at least two layers selected from an electrode constituting the charge transfer means, the light-shielding conductive film, and wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61180404A JP2508507B2 (en) | 1986-07-31 | 1986-07-31 | Solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61180404A JP2508507B2 (en) | 1986-07-31 | 1986-07-31 | Solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6336562A true JPS6336562A (en) | 1988-02-17 |
| JP2508507B2 JP2508507B2 (en) | 1996-06-19 |
Family
ID=16082651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61180404A Expired - Lifetime JP2508507B2 (en) | 1986-07-31 | 1986-07-31 | Solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2508507B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5019884A (en) * | 1989-04-07 | 1991-05-28 | Mitsubishi Denki Kabushiki Kaisha | Charge transfer device |
-
1986
- 1986-07-31 JP JP61180404A patent/JP2508507B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5019884A (en) * | 1989-04-07 | 1991-05-28 | Mitsubishi Denki Kabushiki Kaisha | Charge transfer device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2508507B2 (en) | 1996-06-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3973787B2 (en) | Liquid crystal display device and manufacturing method thereof | |
| EP0905792B1 (en) | Stacked-fringe integrated circuit capacitors | |
| US5939766A (en) | High quality capacitor for sub-micrometer integrated circuits | |
| JP3845605B2 (en) | Switching element for X-ray sensor and method for manufacturing the same | |
| US6225678B1 (en) | Layout technique for a matching capacitor array using a continuous top electrode | |
| KR100273070B1 (en) | Semiconductor device and method of manufacturing such a semiconductor device | |
| US5648663A (en) | Semiconductor structure having transistor and other elements on a common substrate and process for producing the same | |
| US4639940A (en) | Charge coupled device with meander channel and elongated, straight, parallel gate electrodes | |
| JPH01120858A (en) | Integrated circuit device | |
| JPH02166764A (en) | Semiconductor device with capacitance element and manufacture thereof | |
| US4965646A (en) | Thin film transistor and crossover structure for liquid crystal displays | |
| JPS6336562A (en) | Solid-state image sensing device | |
| US5637526A (en) | Method of making a capacitor in a semiconductor device | |
| JPH11251430A (en) | Method and system for mutually connecting conductive elements in integrated circuit | |
| US5326998A (en) | Semiconductor memory cell and manufacturing method thereof | |
| US5451802A (en) | Charge transfer device having a high-resistance electrode and a low-resistance electrode | |
| KR100209758B1 (en) | Solid-state image sensing device and fabricating method of the same | |
| US4133099A (en) | Method of manufacturing a charge transfer device | |
| JPH0828497B2 (en) | Solid-state imaging device | |
| JPH1065148A (en) | Semiconductor device and its manufacture | |
| JP2003161954A (en) | Method for manufacturing liquid crystal display device | |
| KR930009585B1 (en) | Method for manufacturing a capacitor | |
| JP2512902B2 (en) | Method for manufacturing semiconductor memory device | |
| KR0151185B1 (en) | A charge carrier device and its fabricating method | |
| JPS639157A (en) | Manufacture of thin film transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |