JPS6335170A - Power source device - Google Patents

Power source device

Info

Publication number
JPS6335170A
JPS6335170A JP17725586A JP17725586A JPS6335170A JP S6335170 A JPS6335170 A JP S6335170A JP 17725586 A JP17725586 A JP 17725586A JP 17725586 A JP17725586 A JP 17725586A JP S6335170 A JPS6335170 A JP S6335170A
Authority
JP
Japan
Prior art keywords
voltage
switching element
period
full
closing period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17725586A
Other languages
Japanese (ja)
Inventor
Tsutomu Shiomi
務 塩見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP17725586A priority Critical patent/JPS6335170A/en
Publication of JPS6335170A publication Critical patent/JPS6335170A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To permit the coincidence of the waveform of an input current with the waveform of an input voltage substantially with a simple constitution and stabilize an output voltage, by a method wherein the closing period of a switching element is determined by the value of a D.C. voltage or a load current while the opening period of the same is determined in accordance with the value of a full-wave rectifying voltage. CONSTITUTION:A commercial power source 1 is rectified by a full-wave rectifier 2 and the voltage of the commercial power source 1 is converted into a D.C. voltage by a chopper circuit 9 equipped with a switching element 7, thereafter, the voltage is supplied to a load 4. An ON period determining circuit 11, setting the closing period of the switching element 7, determines the closing period by a D.C. voltage Vo or a load current and an OFF period determining circuit 12 determines the opening period of the switching element 7 by a full-wave rectifying voltage Vi. When the D.C. voltage increases, the closing period is controlled so as to be shortened and when the instantaneous value of an input voltage increases, the opening period is controlled so as to be shortened.

Description

【発明の詳細な説明】[Detailed description of the invention] 【技術分野】【Technical field】

本発明は、商用電源を入力し直流定電圧を出力するチョ
ッパ装置を用いた電源装置に関する。
The present invention relates to a power supply device using a chopper device that inputs commercial power and outputs a constant DC voltage.

【背景技術】[Background technology]

商用電源を入力し、直流定電圧を得る方法は数多くある
が、特に商用電源の実効値と同程度の電圧、例えば50
V〜数100Vの電圧を出力する方法としては第6図に
示すようなシリーズレギュレータがある。即ち、第6図
で商用電源1を全波整流器2で整流し、電圧調整索子3
を介して負荷4に直流電圧を供給する。しかるに、この
ものにあっては電圧調整素子としてのトランジスタのロ
スが大きく、−最には用いられない、そこで、近年のス
イッチング素子の高速化に伴い、第7図のような高速チ
ョッパ方式の電源装置が広く用いられるようになってき
た。第7図で商用電源1を全波整流器2で整流し、イン
ダクタンス素子5、逆流防止ダイオード6を介して負荷
4に接続すると共に、スイッチング素子7を制御回路8
によって制御する。しかし、商用電源1は平滑コンデン
サC1に一度蓄積されるため、入力電流Isの波形は第
8図のようになり、高調波成分が多く、入力力率も低く
、且つ入力電流の実効値に対してピーク値が非常に高い
ため、全波整流器2の電流耐量も必要以上に大きくする
必要がある。 そこで、平滑コンデンサを無くすことにより、入力電流
波形を入力電圧波形に極力近づけることにより低歪、高
入力力率を実現するものとして第9図のものがある。第
9図に於いて、商用電源1を全波整流器2で全波整流し
、脈流電圧Viを得る。インダクタンス素子5、逆流防
止ダイオード6、平滑コンデンサC2及びスイッチング
素子7でチョッパ装置9を構成し、直流安定化電圧V0
に変換し負荷4に供給する。直流安定化電圧■。 を検出して周知のPWM制御回路10によりスイッチン
グ素子7のオン・オフ デユーティ−サイクルを調節し
て直流安定化電圧V。は安定になる。 C0は高周波成分を積分するコンデンサである。 チョッパ装置9の原理は第10図のようになる。 即ちスイッチング素子7がオンのとき、等価回路は同図
Aのようになり、インダクタンス素子5には、インダク
タンス素子5のインダクタンスをLとすると次のような
電流IQが流れる。 スイッチング素子7を時間tonだけオンした後、オフ
した時間のIQのピーク値はIpはとなり、これがイン
ダクタンス素子5に蓄積される。ここでViはVsを整
流したものであるからVi=Vplsinωltl  
((ALLはVsの角周波数)となり、時間的に変化す
る。一方、スイッチング素子7のスイッチング周波数f
、はωL/2πに比べて充分に高く、ILは平滑コンデ
ンサC1で積分されるため、入力電流Isの波形は結局
Ipの包路線に相当する。これらの波形は第11図(a
)〜(d)に示している。PWM制御回路10は■。の
大小に応じてスイッチング素子7のオン時間tonを可
変するが、Voは安定しているため、tonはViの全
区間に於いて略一定と見なせる。従って、IpはViに
比例し、l sinωLtlに比例するため、Isは略
sinωLtに一致する。インダクタンス素子5のエネ
ルギーはスイッチング素子7がオンのとき蓄積され、ス
イッチング素子7がオフすると負荷4、コンデンサC2
に放出するが、スイッチング素子7のオフ時間tof 
fが不充分であると、インダクタンス素子5の残留エネ
ルギーは次のスイッチング素子7オン時に加算され、こ
のときの1.、Isは第11図(elf)のようになっ
て、sinωltに一致しなくなるため、tof fの
考慮が必要となる。 スイッチング素子7がオフのときの等価回路は第10図
Bのようになり、インダクタンス素子5には次のような
IQが流れる。 スイッチング素子7のオフ期間tof fでインダクタ
ンス素子5のエネルギーが完全に放出するためには、上
式でI □(toff)≦0にすればよいので、となる
。従って、tof fがViのどの瞬間においても(1
)式を満足するようにPWM制御回路10の設定をすれ
ばよいが、 で昇圧比が低い場合、即ち■。がVpに近づくとtOf
fは大きくせざるを得ない。従って、上述の従来例には
次のような欠点がある。 即ち、tonに対してtoffは充分大きくする必要が
あり、Viの小さい時には不要な1.の休止区間が増大
し、そのため、コンデンサC1の積分能力が低下しIL
が正弦波になりにくい上、充分なエネルギーを伝達する
ためにはインダクタンス素子5のLを小さくする必要が
あるのでIpが高くなって、スイッチング素子7の耐量
が増加し、またスイッチング素子7のスピードの関係上
、tonの絶対値は小さくできず、結局fHを低くする
ことになり、極端な場合はfHが可聴域になりかねず、
更にこの対策上、スイッチング素子7にスピードの速い
ものを使うとコスト高になるという欠点を有する。 上述の欠点を補う方法として第12図に示す方法(英国
特許第2022943号明m書参照)がある、この方法
によればインダクタンス素子5の電流■乙念検出し、こ
れとViを分圧して得られる値とを比較してスイッチン
グ素子7のオフタイミングを決めているため、入力電流
Isは正弦波になり得る。更に■。を安定にするため、
■。を検出しこの値により先のViの分圧比を可変にし
て工りを制御している。しかし、Vi、■。はもとより
工りをも検出する必要があり、その制御は相当複雑にな
るという欠点がある上、Vlに19の包路線が合うため
、工sはどのような場合でも正弦波になるが、スイッチ
ング素子7のオン、オフ周波数を一定にしているためイ
ンダクタンス素子5のエネルギー残留が起こり得る欠点
を有している。
There are many ways to input a commercial power supply and obtain a constant DC voltage, but in particular, a voltage comparable to the effective value of the commercial power supply, for example 50
A series regulator as shown in FIG. 6 is available as a method for outputting a voltage of V to several hundred volts. That is, in FIG. 6, the commercial power supply 1 is rectified by the full-wave rectifier 2,
A DC voltage is supplied to the load 4 via. However, in this case, the loss of the transistor as a voltage adjustment element is large, and it is not used most of the time.Therefore, with the recent increase in the speed of switching elements, a high-speed chopper type power supply as shown in Fig. 7 has been developed. The device has become widely used. In FIG. 7, a commercial power supply 1 is rectified by a full-wave rectifier 2, connected to a load 4 via an inductance element 5 and a reverse current prevention diode 6, and a switching element 7 is connected to a control circuit 8.
controlled by. However, since the commercial power supply 1 is once accumulated in the smoothing capacitor C1, the waveform of the input current Is becomes as shown in Figure 8, which has many harmonic components, a low input power factor, and Since the peak value is very high, the current withstand capacity of the full-wave rectifier 2 must also be made larger than necessary. Therefore, there is a device shown in FIG. 9 that achieves low distortion and high input power factor by eliminating the smoothing capacitor and making the input current waveform as close as possible to the input voltage waveform. In FIG. 9, a commercial power source 1 is full-wave rectified by a full-wave rectifier 2 to obtain a pulsating voltage Vi. A chopper device 9 is configured by an inductance element 5, a reverse current prevention diode 6, a smoothing capacitor C2, and a switching element 7, and a DC stabilized voltage V0
is converted into and supplied to load 4. DC stabilization voltage■. is detected and the well-known PWM control circuit 10 adjusts the on/off duty cycle of the switching element 7 to obtain a stabilized DC voltage V. becomes stable. C0 is a capacitor that integrates high frequency components. The principle of the chopper device 9 is as shown in FIG. That is, when the switching element 7 is on, the equivalent circuit becomes as shown in FIG. After the switching element 7 is turned on for a time ton, the peak value of IQ during the time when it is turned off is Ip, which is accumulated in the inductance element 5. Here, Vi is the rectified Vs, so Vi=Vplsinωltl
((ALL is the angular frequency of Vs) and changes over time. On the other hand, the switching frequency f of the switching element 7
, is sufficiently high compared to ωL/2π, and IL is integrated by the smoothing capacitor C1, so the waveform of the input current Is eventually corresponds to the envelope of Ip. These waveforms are shown in Figure 11 (a
) to (d). The PWM control circuit 10 is ■. The on-time ton of the switching element 7 is varied depending on the magnitude of Vi, but since Vo is stable, ton can be considered to be approximately constant over the entire range of Vi. Therefore, since Ip is proportional to Vi and proportional to l sinωLtl, Is approximately matches sinωLt. Energy in the inductance element 5 is accumulated when the switching element 7 is on, and when the switching element 7 is off, the energy in the inductance element 5 is accumulated in the load 4 and the capacitor C2
However, the off-time tof of the switching element 7
If f is insufficient, the residual energy of the inductance element 5 will be added when the next switching element 7 is turned on, and 1. , Is become as shown in FIG. 11 (elf) and do not match sinωlt, so it is necessary to consider tof f. The equivalent circuit when the switching element 7 is off is as shown in FIG. 10B, and the following IQ flows through the inductance element 5. In order for the energy of the inductance element 5 to be completely released during the off-period tof of the switching element 7, it is sufficient to satisfy I □(toff)≦0 in the above equation, so that the following equation is obtained. Therefore, at any moment when tof f is Vi (1
) The PWM control circuit 10 may be set to satisfy the equation (2), but if the step-up ratio is low in (2). When approaches Vp, tOf
f has to be increased. Therefore, the above-mentioned conventional example has the following drawbacks. That is, it is necessary to make toff sufficiently large with respect to ton, and when Vi is small, 1. As a result, the integrative ability of capacitor C1 decreases and IL
is less likely to become a sine wave, and in order to transmit sufficient energy, it is necessary to reduce L of the inductance element 5, so Ip increases, the withstand capacity of the switching element 7 increases, and the speed of the switching element 7 increases. Due to the relationship, the absolute value of ton cannot be made small, and in the end fH will be lowered, and in extreme cases, fH may fall into the audible range.
Furthermore, in this countermeasure, if a fast switching element 7 is used, there is a drawback that the cost increases. As a method of compensating for the above-mentioned drawbacks, there is a method shown in FIG. 12 (see British Patent No. 2022943). According to this method, the current of the inductance element 5 is detected, and the voltage of this and Vi is divided. Since the off timing of the switching element 7 is determined by comparing the obtained value, the input current Is can be a sine wave. Furthermore ■. In order to stabilize
■. is detected, and based on this value, the partial pressure ratio of the previous Vi is made variable to control the machining. However, Vi, ■. It is necessary to detect not only the machining, but also the machining, which has the drawback that its control is quite complicated.In addition, since the envelope line of 19 matches Vl, the machining s is a sine wave in any case, but switching Since the on and off frequencies of the element 7 are kept constant, there is a drawback that energy may remain in the inductance element 5.

【発明の目的】[Purpose of the invention]

本発明の目的とするところは、簡単な構成で、入力電流
波形を入力電圧波形に略一致させ、しがも出力電圧をも
安定にし、かつインダクタンス素子のエネルギー蓄積を
回避するためのインダクタンス素子電流体止を無用に長
くとる必要がない電源装置の制御手段を提供するにある
An object of the present invention is to provide an inductance element current that has a simple configuration, allows the input current waveform to substantially match the input voltage waveform, stabilizes the output voltage, and avoids energy accumulation in the inductance element. To provide a control means for a power supply device that does not require an unnecessarily long suspension.

【発明の開示】[Disclosure of the invention]

第1図は本発明の基本的ブロック回路図で、商用電源1
を全波整流器2で全波整流してスイッチング素子7を具
備したチョッパ回路9で直流電圧に変換し、負荷4に供
給する。スイッチング素子7の閉成期間を設定するオン
期間決定回路11は直流電圧V0又は負荷電流によって
、閉成期間を決定し、オフ期間決定回路12は全波整流
電圧■iによってスイッチング素子7の閉成期間を決定
し、更に直流電圧が上がれば閉成期間を短縮し、入力電
圧瞬時値が上がれば閉成期間を短縮又は上記の逆方向に
制御するものである。 以下実施例により具体的に説明する。 X11L 第2図に於いて、商用電源、1を全波整流器2で全波整
流し、脈流電圧Viを得る。インダクタンス素子5、逆
流防止ダイオード6、平滑コンデンサC2及びスイッチ
ング素子7でチョッパ装置9を構成し、直流電圧を負荷
4に供給する。スイッチング素子7はオン期間決定回路
11により閉成期間を決定し、オフ期間決定回路12に
より閉成期間を決定する。第2図の各部の波形は第3図
(a)〜(h)に示すようになる。 チョッパ装置9の動作原理は従来例と同じである。今、
RSフリップフロップFFの出力QがHigh、 Qが
Lowとすると、スイッチング素子7がオンして電流I
Qが流れる始める。同時に充放電制御スイッチS、がオ
ンし、コンデンサC2は抵抗R3を介して放電し、電圧
比較素子CPIの出力はLowになり、同時に充放電制
御スイッチS2がオフしてコンデンサC3は電源Vcc
より抵抗R2を介して充電を開始する。直流電圧v0を
抵抗R3、R3で分圧してあり、増幅器A2、抵抗R,
、電源■「2で反転増幅器を構成し、VA2出力は−■
。に比例した電圧を出す、コンデンサC4の電圧Vc4
がVA2に達するまで、スイッチング素子7はオンして
いる。Vc4≧VA2になると電圧比較素子CP 2の
出力がHighとなり、RSフリップフロップFFはリ
セットされて出力QはLow、ζはHighになり、ス
イッチング素子7はオフし、電流IDが流れ始める。同
時に充放電制御スイッチS2がオンし、コンデンサC4
は抵抗R1゜を介して放電し、電圧比較素子CP2の出
力はLowになり、同時に充放電制御スイッチSIがオ
フし、コンデンサC2は電源Vccより抵抗RIを介し
て充電を開始する。 脈動電圧Viを抵抗R5、R4で分圧しており、増幅器
A1、抵抗Rフ、R7′、R7″、電源VrIで非反転
増幅器を構成し、VAI出力はViに比例した電圧を出
す、コンデンサC3の電圧V c3がVAIに達するま
でスイッチング素子7はオフしている。 Vc3≧VA、になると電圧比較素子CP +の出力は
Highになり、RSフリップフロップFFはセットさ
れて、スイッチング素子7はオンとなり、上記動作を繰
り返す0以上のような動作でスイッチング素子7のオン
、オフは制御される。即ち、■。を検出してVA2に変
換し、これとコンデンサC1の充電カーブによってto
nを決め、Viを検出してvAIに変換し、これとコン
デンサCコの充電カーブによってtof fを決める。 また、■AI、VA□はいずれも増幅器A5、A2によ
り各々Vi、V、を非反転増幅、反転増幅され、Viが
上がればVAIが上がり、Voが上がればVA2は下が
る。更にコンデンサC1、C1の充電カーブは一定であ
るため、Viが上がればVAIが上がり、Vc3との交
点が遅くなるからtoffが大きくなり、■。が上がれ
ばVA2が下がり、Vc4との交点が早くなってton
が小さくなる。先の従来例中の(1)式 によれば、Viが高いとき、toffを大きくし、Vi
が低いときはtof fを小さくすれば良いことを示し
ており、実施例1はこれを満足できるため、従来例のよ
うに不要なIL休止区間を減らずことができ、しかも、
Isの波形にも影響せず、tonを■。 で制御するので、■。は安定な出力となり、且つ構成も
簡単になる。 夫11走 第4図には本発明の他の実施例で、各部の波形は第5図
(a)〜(e)に示すようになる。RSフリップフロッ
プFFの出力QがHighであるとすると、スイッチン
グ素子7がオンして電流工。が流れ始める。同時にカレ
ントミラートランジスタST、、Sr1、抵抗R1、コ
ンデンサC1で構成したカレントミラー回路で、コンデ
ンサC1の電圧V e 3が一定の傾きで上昇し始める
。直流電圧v0を抵抗R,,R2で分圧しており、増幅
器A、電源Vr、抵抗R3で構成する反転増幅器の出力
VAは−Voに比例した電圧を出す、VAとVc3とを
電圧比較素子CP2で比較し、Vc、、がVAに達する
までスイッチング素子7はオンしている。Vc、−VA
になると、電圧比較素子CP2の出力がHighとなり
、RSSフリップフロラ1Fはリセットされて出力Qは
Lowになり、スイッチング素子7はオフし、IDが流
れ始める。電圧比較素子CP +でV c 3とVAI
vTとを比較し、vc3がVAIV丁に達するまでスイ
ッチング素子7はオフし、Vc3−VA+■Tになると
電圧比較素子CP、の出力がHighになり、RSフリ
ップフロップFFはセットされて出力QはHighとな
り、同時に充放電制御スイッチS、がオンしてコンデン
サC1を放電し、電圧比較素子CP1はすぐにLowに
なるため、充放電制御スイッチS3もオフし、上記動作
を繰り返す。 実施例2は昇降圧チョッパで、 I Q(t)=Vi/ L−t IO(t)= I p−V。/L−t I p=Vi/ L −ton toff≧Vi/Vo・ton となっておりtoffがViに比例しているとすれば完
全にILの休止をなくすことができる。この実施例では
、Vc3が完全な直線であるため、toffocViが
容易に実現する好適例である。
Figure 1 is a basic block circuit diagram of the present invention.
is full-wave rectified by a full-wave rectifier 2 , converted into a DC voltage by a chopper circuit 9 equipped with a switching element 7 , and supplied to a load 4 . The on-period determining circuit 11 that sets the closing period of the switching element 7 determines the closing period based on the DC voltage V0 or the load current, and the off-period determining circuit 12 determines the closing period of the switching element 7 using the full-wave rectified voltage ■i. The period is determined, and if the DC voltage further increases, the closing period is shortened, and if the instantaneous input voltage value increases, the closing period is shortened or controlled in the opposite direction. This will be explained in detail below using examples. X11L In FIG. 2, a commercial power supply 1 is full-wave rectified by a full-wave rectifier 2 to obtain a pulsating voltage Vi. A chopper device 9 is configured by the inductance element 5, the reverse current prevention diode 6, the smoothing capacitor C2, and the switching element 7, and supplies DC voltage to the load 4. The on-period determining circuit 11 determines the closing period of the switching element 7, and the off-period determining circuit 12 determines the closing period. The waveforms of each part in FIG. 2 are as shown in FIGS. 3(a) to 3(h). The operating principle of the chopper device 9 is the same as that of the conventional example. now,
When the output Q of the RS flip-flop FF is High and Q is Low, the switching element 7 is turned on and the current I
Q begins to play. At the same time, the charge/discharge control switch S is turned on, the capacitor C2 is discharged via the resistor R3, and the output of the voltage comparison element CPI becomes Low.At the same time, the charge/discharge control switch S2 is turned off, and the capacitor C3 is connected to the power supply Vcc.
Charging is then started via resistor R2. The DC voltage v0 is divided by resistors R3 and R3, and the amplifier A2, resistors R,
, the power supply ■"2 constitutes an inverting amplifier, and the VA2 output is -■
. Voltage Vc4 of capacitor C4, which outputs a voltage proportional to
The switching element 7 remains on until the voltage reaches VA2. When Vc4≧VA2, the output of the voltage comparison element CP2 becomes High, the RS flip-flop FF is reset, the output Q becomes Low and ζ becomes High, the switching element 7 is turned off, and the current ID begins to flow. At the same time, charge/discharge control switch S2 is turned on, and capacitor C4
is discharged via the resistor R1°, the output of the voltage comparison element CP2 becomes Low, and at the same time, the charge/discharge control switch SI is turned off, and the capacitor C2 starts charging from the power supply Vcc via the resistor RI. The pulsating voltage Vi is divided by resistors R5 and R4, and the amplifier A1, resistors Rf, R7', R7'', and power supply VrI constitute a non-inverting amplifier, and the VAI output outputs a voltage proportional to Vi, and the capacitor C3 The switching element 7 remains off until the voltage Vc3 reaches VAI. When Vc3≧VA, the output of the voltage comparison element CP+ becomes High, the RS flip-flop FF is set, and the switching element 7 is turned on. The on/off state of the switching element 7 is controlled by repeating the above operation over 0. That is, ① is detected and converted to VA2, and to is determined by this and the charging curve of the capacitor C1.
Determine n, detect Vi and convert it to vAI, and determine tof by this and the charging curve of capacitor C. Also, in both AI and VA□, Vi and V are non-invertingly amplified and invertively amplified by amplifiers A5 and A2, respectively, so that when Vi goes up, VAI goes up, and when Vo goes up, VA2 goes down. Furthermore, since the charging curves of capacitors C1 and C1 are constant, as Vi increases, VAI increases, and since the intersection with Vc3 becomes later, toff increases, and (2). As VA2 increases, the intersection with Vc4 becomes earlier and ton
becomes smaller. According to equation (1) in the prior art example, when Vi is high, toff is increased and Vi
This shows that when tof is low, it is sufficient to make tof f small, and the first embodiment satisfies this, so it is possible to avoid reducing unnecessary IL pause periods as in the conventional example, and moreover,
ton without affecting the Is waveform. Since it is controlled by ■. The output is stable and the configuration is simple. Figure 4 shows another embodiment of the present invention, and the waveforms at various parts are as shown in Figures 5(a) to 5(e). Assuming that the output Q of the RS flip-flop FF is High, the switching element 7 is turned on and the current flows. begins to flow. At the same time, in the current mirror circuit composed of current mirror transistors ST, Sr1, resistor R1, and capacitor C1, the voltage V e 3 of capacitor C1 begins to rise at a constant slope. DC voltage v0 is divided by resistors R,,R2, and the output VA of the inverting amplifier composed of amplifier A, power supply Vr, and resistor R3 outputs a voltage proportional to -Vo.VA and Vc3 are connected to voltage comparison element CP2. The switching element 7 is turned on until Vc, , reaches VA. Vc, -VA
Then, the output of the voltage comparison element CP2 becomes High, the RSS flip-flop 1F is reset, the output Q becomes Low, the switching element 7 is turned off, and ID begins to flow. V c 3 and VAI at voltage comparison element CP +
The switching element 7 is turned off until vc3 reaches VAIV, and when it reaches Vc3-VA+■T, the output of the voltage comparison element CP becomes High, the RS flip-flop FF is set, and the output Q is At the same time, the charge/discharge control switch S is turned on to discharge the capacitor C1, and the voltage comparison element CP1 immediately becomes Low, so the charge/discharge control switch S3 is also turned off and the above operation is repeated. Embodiment 2 is a buck-boost chopper, where I Q(t)=Vi/L-t IO(t)=I p-V. /L-tI p=Vi/L-ton toff≧Vi/Vo·ton If toff is proportional to Vi, it is possible to completely eliminate IL pauses. In this example, since Vc3 is a perfect straight line, it is a suitable example in which toffocVi can be easily realized.

【発明の効果】【Effect of the invention】

上述のように本発明は、入力電圧波形を商用電源波形に
略一致させ得るようにスイッチング素子の閉成期間を直
流電圧値又は負荷電流により決定し、閉成期間を全波整
流電圧値に応じて決定する如くしたから、簡単な構成で
入力電流波形を商用電源波形に略一致させることができ
しがち出力電圧を安定にでき、且つインダクタンス素子
のエネルギー蓄積を回避するためのインダクタンス素子
電流体止を無用に長くする必要がなく、またスイッチン
グ素子の閉成期間を直流電圧値の増加時は短くし、減少
時は長くする如くしたから、直流電圧値を一層安定にで
きるという効果を奏するものである。
As described above, the present invention determines the closing period of the switching element based on the DC voltage value or the load current so that the input voltage waveform substantially matches the commercial power supply waveform, and determines the closing period according to the full-wave rectified voltage value. Since the input current waveform can be made to substantially match the commercial power supply waveform with a simple configuration, the output voltage can be stabilized, and the inductance element current stopper can be used to avoid energy accumulation in the inductance element. There is no need to unnecessarily lengthen the DC voltage value, and since the closing period of the switching element is shortened when the DC voltage value increases and lengthened when the DC voltage value decreases, the DC voltage value can be made more stable. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の基本ブロック回路図、第2図は本発明
の1実施例の回路図、第3図は同上の動作タイムチャー
ト、第4図は本発明の他の実施例の回路図、第5図は同
上の動作タイムチャート、第6図は従来例の回路図、第
7図は同上の他の例の回路図、第8図は同上の電圧、電
流波形図、第9図は従来例の別の例の回路図、第10図
は同上の動作説明図、第11図は同上の要部電圧電流波
形図、第12図は従来例の更に他の例の回路図である。 図中、1は商用電源、2は全波整流器、4は負荷、5は
インダクタンス素子、6は逆流防止ダイオード、7はス
イッチング素子、9はチョッパ装置、11はオフ期間決
定回路、12はオフ期間決定回路である。 代理人 弁理士 石 1)長 七 第1 図 犯2図 第6図 第7図 第8図 第9図 IU 第10図 第11図 第12図
Fig. 1 is a basic block circuit diagram of the present invention, Fig. 2 is a circuit diagram of one embodiment of the invention, Fig. 3 is an operation time chart of the same as above, and Fig. 4 is a circuit diagram of another embodiment of the invention. , Fig. 5 is an operation time chart of the same as above, Fig. 6 is a circuit diagram of the conventional example, Fig. 7 is a circuit diagram of another example of the same as above, Fig. 8 is a voltage and current waveform diagram of the same as above, and Fig. 9 is a diagram of the same as above. FIG. 10 is a circuit diagram of another example of the conventional example, FIG. 10 is an operation explanatory diagram of the same as above, FIG. 11 is a voltage and current waveform diagram of the main part of the same as above, and FIG. 12 is a circuit diagram of still another example of the conventional example. In the figure, 1 is a commercial power supply, 2 is a full-wave rectifier, 4 is a load, 5 is an inductance element, 6 is a backflow prevention diode, 7 is a switching element, 9 is a chopper device, 11 is an off-period determining circuit, and 12 is an off-period It is a decision circuit. Agent Patent attorney Ishi 1) Chief 7th 1st figure 2nd figure 6th figure 7th figure 8th figure 9th figure IU figure 10th figure 11th figure 12th figure

Claims (2)

【特許請求の範囲】[Claims] (1)商用交流電源を全波整流し、これをスイッチング
素子、インダクタンス素子及び逆流防止ダイオードで構
成されるチョッパ装置で直流電圧に変換し、負荷に供給
する電源装置に於いて、入力電流波形を商用電源波形に
略一致させ得るように前記スイッチング素子の閉成期間
を前記直流電圧値又は負荷電流により決定し、閉成期間
を全波整流電圧値に応じて決定する如くして成ることを
特徴とする電源装置。
(1) A commercial AC power source is full-wave rectified, converted to DC voltage by a chopper device consisting of a switching element, an inductance element, and a backflow prevention diode, and the input current waveform is The closing period of the switching element is determined by the DC voltage value or the load current so as to substantially match the commercial power supply waveform, and the closing period is determined according to the full-wave rectified voltage value. power supply.
(2)スイッチング素子の閉成期間を直流電圧値の増加
時は短くし、減少時は長くする如くして成ることを特徴
とする特許請求の範囲第1項記載の電源装置。
(2) The power supply device according to claim 1, wherein the closing period of the switching element is shortened when the DC voltage value increases and lengthened when the DC voltage value decreases.
JP17725586A 1986-07-28 1986-07-28 Power source device Pending JPS6335170A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17725586A JPS6335170A (en) 1986-07-28 1986-07-28 Power source device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17725586A JPS6335170A (en) 1986-07-28 1986-07-28 Power source device

Publications (1)

Publication Number Publication Date
JPS6335170A true JPS6335170A (en) 1988-02-15

Family

ID=16027876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17725586A Pending JPS6335170A (en) 1986-07-28 1986-07-28 Power source device

Country Status (1)

Country Link
JP (1) JPS6335170A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0679099U (en) * 1993-04-13 1994-11-04 新日本照明株式会社 Power supply circuit for lighting bulb

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0679099U (en) * 1993-04-13 1994-11-04 新日本照明株式会社 Power supply circuit for lighting bulb

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