JPS633481B2 - - Google Patents
Info
- Publication number
- JPS633481B2 JPS633481B2 JP9438579A JP9438579A JPS633481B2 JP S633481 B2 JPS633481 B2 JP S633481B2 JP 9438579 A JP9438579 A JP 9438579A JP 9438579 A JP9438579 A JP 9438579A JP S633481 B2 JPS633481 B2 JP S633481B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- terminal
- hybrid
- amplifier
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000002131 composite material Substances 0.000 claims description 19
- 238000001514 detection method Methods 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000003786 synthesis reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/54—Circuits using the same frequency for two directions of communication
- H04B1/58—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B3/00—Line transmission systems
- H04B3/02—Details
- H04B3/03—Hybrid circuits
Description
【発明の詳細な説明】
本発明は、ハイブリツド回路障害検出回路、特
に3dBハイブリツド回路において、並列合成増幅
器の障害を検出すべく、出力側ハイブリツドのア
イソレーシヨン端子にモニタをもうけ、障害検出
を容易にしたハイブリツド回路障害検出回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a hybrid circuit failure detection circuit, particularly a 3dB hybrid circuit, in which a monitor is provided at the isolation terminal of the hybrid on the output side in order to detect failures in parallel composite amplifiers, thereby facilitating failure detection. This invention relates to a hybrid circuit failure detection circuit.
従来、第１図および第２図を参照して後述する
如く、3dBハイブリツド回路における並列合成増
幅器の障害を検知するために、合成出力に結合器
をもうけたり、あるいは各増幅器の直後に結合器
をもうけたりして、モニタをもうけることが行な
われている。しかし、この種の従来の検出回路の
場合、入力信号の信号レベルが変化した場合に障
害を十分検出できないことが生じたり、あるいは
合成出力がその分だけレベル低下する難点があ
る。 Conventionally, as described below with reference to FIGS. 1 and 2, in order to detect failures in parallel composite amplifiers in a 3 dB hybrid circuit, a coupler is provided at the composite output, or a coupler is placed immediately after each amplifier. People are trying to make money by making money and making monitors. However, this type of conventional detection circuit has the disadvantage that when the signal level of the input signal changes, it may not be possible to sufficiently detect a fault, or the level of the combined output may drop by that amount.
本発明は上記の点を解決することを目的として
おり、本発明のハイブリツド回路障害検出回路は
入力側に第１のハイブリツドをもうけると共に出
力側に第２のハイブリツドをもうけて並列合成増
幅器を有する3dBハイブリツド回路において、上
記出力側の第２のハイブリツドのアイソレーシヨ
ン端子に検波器をもうけ、該検波出力によつて上
記並列合成増幅器の障害を検出するようにしたこ
とを特徴としている。以下図面を参照しつつ説明
する。 The present invention aims to solve the above-mentioned problems, and the hybrid circuit fault detection circuit of the present invention has a first hybrid on the input side and a second hybrid on the output side, and has a parallel composite amplifier. The hybrid circuit is characterized in that a detector is provided at the isolation terminal of the second hybrid on the output side, and a fault in the parallel composite amplifier is detected by the detection output. This will be explained below with reference to the drawings.
第１図および第２図は夫々従来の検出回路を説
明する説明図、第３図は本発明の検出回路の一実
施例構成、第４図は本発明の適用例を示す。 FIGS. 1 and 2 are explanatory diagrams illustrating conventional detection circuits, FIG. 3 shows the configuration of an embodiment of the detection circuit of the present invention, and FIG. 4 shows an example of application of the present invention.
第１図において、INは入力信号端子、１は第
１のハイブリツド、２は第２のハイブリツド、３
―１，３―２は並列合成増幅器、４はアイソレー
シヨン端子、OUTは合成出力端子、５は結合器、
６は検波器、MONはモニタ端子、R1ないしR4は
夫々抵抗を表わしている。 In Figure 1, IN is an input signal terminal, 1 is the first hybrid, 2 is the second hybrid, 3 is the input signal terminal.
-1, 3-2 are parallel synthesis amplifiers, 4 is isolation terminal, OUT is synthesis output terminal, 5 is coupler,
6 is a detector, MON is a monitor terminal, and R1 to R4 each represent a resistor.
周知の如く、入力信号は第１のハイブリツド１
に供給され、増幅器３―１の入力と増幅器３―２
の入力とで90゜の位相差がつくられ、増幅器３―
１，３―２の出力側にもうけられた第２のハイブ
リツド２によつて、合成出力端子OUTから合成
出力が得られる。このときアイソレーシヨン端子
４には２つの波が打消されて一般には出力を生じ
ない。 As is well known, the input signal is the first hybrid 1
is supplied to the input of amplifier 3-1 and the input of amplifier 3-2.
A phase difference of 90° is created between the input of amplifier 3 and
A composite output is obtained from the composite output terminal OUT by the second hybrid 2 provided on the output side of the hybrids 1 and 3-2. At this time, the two waves are canceled at the isolation terminal 4 and generally no output is produced.
このようなハイブリツド回路装置において、増
幅器３―１，３―２のいずれか一方に障害が生じ
てゲイン零の状態となると、合成出力のレベルが
−6dB減少する。この点を利用すべく、第１図図
示構成の如く、合成出力端子側に結合器５をもう
け、結合器５の出力を検波器６によつて検波し、
合成出力を端子MONによつて監視することが行
なわれる。 In such a hybrid circuit device, if a failure occurs in either the amplifiers 3-1 or 3-2 and the gain becomes zero, the level of the combined output decreases by -6 dB. In order to take advantage of this point, as in the configuration shown in FIG. 1, a coupler 5 is provided on the composite output terminal side, and the output of the coupler 5 is detected by a detector 6.
The composite output is monitored via the terminal MON.
しかし、図示の場合、合成出力端子側にモニタ
をもうけていることから、この分だけ出力端
OUTに現われる合成出力レベルが低下する。ま
た該検出方式を用いた場合には、合成出力のレベ
ル監視を行なつているものであることから、仮に
入力信号端子INに入力される入力信号のレベル
が低下した場合にも、並列合成増幅器３―１，３
―２の障害として検出される。 However, in the case shown, since the monitor is provided on the composite output terminal side, the output terminal is
The combined output level appearing at OUT decreases. Furthermore, when using this detection method, since the level of the composite output is monitored, even if the level of the input signal input to the input signal terminal IN decreases, the parallel composite amplifier 3-1,3
-2 detected as a failure.
第２図は従来の他の構成を示し、図中の符号は
第１図に対応している。第２図図示の場合、各増
幅器３―１，３―２の出力端に夫々結合器５―
１，５―２を介してモニタ手段がもうけられてい
る。即ち、結合器５―１の出力を検波器６―１に
よつて検波して増幅器３―１の障害を検出し、結
合器５―２の出力を検波器６―２によつて検波し
て増幅器３―２の障害を検出するようにされる。 FIG. 2 shows another conventional configuration, and the symbols in the figure correspond to those in FIG. 1. In the case shown in FIG. 2, a coupler 5- is connected to the output terminal of each amplifier 3-1, 3-2
Monitoring means are provided via 1, 5-2. That is, the output of the coupler 5-1 is detected by the detector 6-1 to detect a failure in the amplifier 3-1, and the output of the coupler 5-2 is detected by the detector 6-2. A failure of amplifier 3-2 is detected.
この場合にも、上記結合器５―１，５―２の存
在によつて合成出力端子OUTの出力レベルが低
下し、また２つのモニタ手段をもうけることから
構成が複雑となる。 In this case as well, the presence of the couplers 5-1 and 5-2 lowers the output level of the composite output terminal OUT, and the provision of two monitor means complicates the configuration.
第３図は本発明の一実施例を示し、図中の符号
は第１図または第２図に対応している。本発明の
場合において、２つの増幅器３―１と３―２とが
健全であるとき、合成端子OUTに合成出力が得
られ、アイソレーシヨン端子４において打消され
て出力が現われないことは、第１図や第２図図示
の場合と変りはない。 FIG. 3 shows an embodiment of the present invention, and the reference numerals in the figure correspond to those in FIG. 1 or 2. In the case of the present invention, when the two amplifiers 3-1 and 3-2 are healthy, a composite output is obtained at the composite terminal OUT, and it is canceled at the isolation terminal 4 so that no output appears. There is no difference from the cases shown in Figures 1 and 2.
しかし、第１図や第２図図示の場合も同様であ
るが、いずれか一方の増幅器に障害が発生する
と、アイソレーシヨン端子４に出力が現われるよ
うになる。本発明の場合、この点に着目して、該
アイソレーシヨン端子４に、検波器６をもうけて
障害の発生を検出するようにする。即ち通常の場
合、アイソレーシヨン端子４には出力が現われな
いことから、モニタ端子MONの電圧は実質上零
であり、増幅器３―１または３―２に障害が発生
すると、モニタ端子MONに閾値レベル以上の電
圧が現われる。 However, as is the case with the cases shown in FIGS. 1 and 2, if a failure occurs in either one of the amplifiers, an output will appear at the isolation terminal 4. In the case of the present invention, paying attention to this point, a detector 6 is provided at the isolation terminal 4 to detect the occurrence of a failure. That is, in the normal case, since no output appears at the isolation terminal 4, the voltage at the monitor terminal MON is virtually zero, and when a failure occurs in the amplifier 3-1 or 3-2, the voltage at the monitor terminal MON reaches the threshold voltage. A voltage above the level appears.
本発明の場合、各増幅器が正常に動作している
時合成出力端子OUTに現われる出力にレベル低
下を与えることがない。また仮に入力信号のレベ
ルが低下しても、モニタ端子MONに出力が現わ
れることがない。なお、本発明の場合、アイソレ
ーシヨン端子４に検波器６がもうけられている
が、該検波器６のインピーダンスをハイブリツド
の終端インピーダンスに合わせることにより、仮
に通常の状態のもとでアイソレーシヨン端子４に
僅かに出力が現われても非所望な反射を生じるこ
とがない。 In the case of the present invention, when each amplifier is operating normally, the level of the output appearing at the composite output terminal OUT is not reduced. Furthermore, even if the level of the input signal drops, no output will appear at the monitor terminal MON. In the case of the present invention, a detector 6 is provided at the isolation terminal 4, but by matching the impedance of the detector 6 to the terminal impedance of the hybrid, isolation can be achieved even under normal conditions. Even if a small amount of output appears at the terminal 4, no undesired reflection will occur.
以下第４図を参照して、本発明による検出回路
の適用例を説明する。 An application example of the detection circuit according to the present invention will be described below with reference to FIG.
第４図において、符号１，２，３―１，３―
２，４，６，R1，R3，MON，OUTは第３図に
対応している。また７はトランスミツタ、８，９
は夫々フイルタ、１０ないし１３は夫々サーキユ
レータ、１４はアンテナ、R5ないしR7は夫々抵
抗、１５は本発明にいうハイブリツド回路を表わ
す。 In Fig. 4, the symbols 1, 2, 3-1, 3-
2, 4, 6, R 1 , R 3 , MON, and OUT correspond to FIG. 3. Also, 7 is a transmitter, 8, 9
10 to 13 are each a filter, 10 to 13 are each a circulator, 14 is an antenna, R5 to R7 are each a resistor, and 15 is a hybrid circuit according to the present invention.
トランスミツタ７からの送信信号は、フイルタ
８、サーキユレータ１０，１１を介して図示ルー
トＡの如くアンテナ１４から送信される。またア
ンテナ１４によつて受信された受信信号は、図示
ルートＢの如く、サーキユレータ１１，１２，１
３、フイルタ９をへてハイブリツド回路１５に供
給される。ハイブリツド回路１５からの出力はヘ
テロダイン回路に導びかれる。この場合、ハイブ
リツド回路１５は、増幅器を２重化しておき増幅
器のいずれか１つに障害が生じても受信し得るよ
うに配置してもうけられるものと考えてよい。 A transmission signal from the transmitter 7 is transmitted from the antenna 14 via the filter 8 and circulators 10 and 11 as shown in route A in the figure. Further, the received signal received by the antenna 14 is transmitted to the circulators 11, 12, 1 as shown in route B in the figure.
3. The signal is supplied to the hybrid circuit 15 through the filter 9. The output from hybrid circuit 15 is led to a heterodyne circuit. In this case, the hybrid circuit 15 may be constructed by duplicating amplifiers and arranging them so that reception is possible even if one of the amplifiers fails.
しかし、増幅器のいずれか一方の障害時には可
能な限ぎり早期にこれを検出して対策を立てるこ
とが望まれ、第１図ないし第３図を参照して説明
した如く、モニタ手段をもうけるようにされる。
この場合、上記受信信号はレベルは受信状態にお
いて大きく変動し、−30dBn程度から−70dBn程
度の変動幅が存在する。このために、仮に第４図
図示MON′の如く第１図図示の構成のモニタ手段
をもうけても、実質上上記増幅器３―１または３
―２の障害を検出できない。この意味からも本発
明の如くアイソレーシヨン端子４にモニタ手段を
もうけることが有効である。 However, in the event of a failure in either one of the amplifiers, it is desirable to detect this as early as possible and take countermeasures. be done.
In this case, the level of the received signal varies greatly in the receiving state, and there is a variation range of about -30 dB n to -70 dB n . For this reason, even if a monitor means of the configuration shown in FIG. 1 is provided, such as MON' shown in FIG.
-2 failure cannot be detected. From this point of view as well, it is effective to provide the isolation terminal 4 with a monitor means as in the present invention.
ただ本発明の場合においても、受信信号レベル
が極端に小さいと、増幅器のいずれか一方に障害
が生じていても、これを検出できないこともあ
る。送信信号が第４図図示ルートＣの如く非所望
に廻り込むことを防止するためにフイルタが設け
られているが一般的には、送信信号の−60dB程
度のレベルで廻り込みがある。送信機の出力が
1Wの時には−30dBn程度の信号が廻り込んでく
る事になる。これは、受信機の入力レベルの最大
値か又はそれ以上であり安定している。これを利
用して、増幅器の故障を検出することができる。 However, even in the case of the present invention, if the received signal level is extremely low, it may not be possible to detect a fault even if one of the amplifiers has a fault. A filter is provided to prevent the transmitted signal from undesirably looping around as shown in route C in FIG. 4, but generally, the looping occurs at a level of about -60 dB of the transmitted signal. The output of the transmitter is
At 1W, a signal of around -30dB n will come around. This is at or above the maximum input level of the receiver and is stable. This can be used to detect amplifier failure.
即ち本来非所望な廻り込み信号がハイブリツド
回路１５に供給される形となつて増幅器の障害時
には必ず閾値レベル以上の電圧がMON端子に現
われる事になり、増幅器の障害を適確に検出する
事が可能となる。 In other words, an originally undesired sneak signal is supplied to the hybrid circuit 15, and a voltage higher than the threshold level will always appear at the MON terminal in the event of an amplifier failure, making it difficult to accurately detect an amplifier failure. It becomes possible.
第１図および第２図は夫々従来の検出回路を説
明する説明図、第３図は本発明の検出回路の一実
施例構成、第４図は本発明の適用例を示す。
図中、INは入力端子、１は第１のハイブリツ
ド、２は第２のハイブリツド、３―１，３―２は
並列合成増幅器、４はアイソレーシヨン端子、
OUTは合成出力端子、６は検波器、MONはモ
ニタ端子を表わす。
FIGS. 1 and 2 are explanatory diagrams illustrating conventional detection circuits, FIG. 3 shows the configuration of an embodiment of the detection circuit of the present invention, and FIG. 4 shows an example of application of the present invention. In the figure, IN is an input terminal, 1 is a first hybrid, 2 is a second hybrid, 3-1, 3-2 are parallel synthesis amplifiers, 4 is an isolation terminal,
OUT represents a composite output terminal, 6 represents a detector, and MON represents a monitor terminal.
Claims (1)
に出力側に第２のハイブリツドをもうけて並列合
成増幅器を有する3dBハイブリツド回路におい
て、上記出力側の第２のハイブリツドのアイソレ
ーシヨン端子の検波器をもうけ、該検波出力によ
つて上記並列合成増幅器の障害を検出するように
したことを特徴とするハイブリツド回路障害検出
回路。1. In a 3 dB hybrid circuit having a first hybrid on the input side and a second hybrid on the output side and having a parallel composite amplifier, a detector is provided for the isolation terminal of the second hybrid on the output side, A hybrid circuit fault detection circuit characterized in that a fault in the parallel composite amplifier is detected by the detected output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9438579A JPS5619242A (en) | 1979-07-24 | 1979-07-24 | Detecting circuit for fault of hybrid circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9438579A JPS5619242A (en) | 1979-07-24 | 1979-07-24 | Detecting circuit for fault of hybrid circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5619242A JPS5619242A (en) | 1981-02-23 |
| JPS633481B2 true JPS633481B2 (en) | 1988-01-25 |
Family
ID=14108815
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9438579A Granted JPS5619242A (en) | 1979-07-24 | 1979-07-24 | Detecting circuit for fault of hybrid circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5619242A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0617973U (en) * | 1992-08-08 | 1994-03-08 | 株式会社東京プロダクツ | Document storage |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5866702U (en) * | 1981-10-30 | 1983-05-06 | 日本電気株式会社 | power synthesizer |
| JPS5896349U (en) * | 1981-12-23 | 1983-06-30 | ティーディーケイ株式会社 | microwave equipment |
| JPS59216308A (en) * | 1983-05-25 | 1984-12-06 | Hitachi Ltd | Output synthesizing circuit for amplifier |
| JPS6320906A (en) * | 1986-07-14 | 1988-01-28 | Nec Corp | Circuit for preventing output level of parallel operating amplifier |
| BE1002413A3 (en) * | 1988-05-11 | 1991-01-29 | Spoelders Ludy | Device for saw-cutting between two pairs of upper and lower blades and gluing the ends of veneer bands. |
-
1979
- 1979-07-24 JP JP9438579A patent/JPS5619242A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0617973U (en) * | 1992-08-08 | 1994-03-08 | 株式会社東京プロダクツ | Document storage |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5619242A (en) | 1981-02-23 |
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