JPS633393B2 - - Google Patents

Info

Publication number
JPS633393B2
JPS633393B2 JP55093942A JP9394280A JPS633393B2 JP S633393 B2 JPS633393 B2 JP S633393B2 JP 55093942 A JP55093942 A JP 55093942A JP 9394280 A JP9394280 A JP 9394280A JP S633393 B2 JPS633393 B2 JP S633393B2
Authority
JP
Japan
Prior art keywords
input
output transfer
transfer path
minor loop
minor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55093942A
Other languages
Japanese (ja)
Other versions
JPS5720987A (en
Inventor
Minoru Hiroshima
Susumu Kurokawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9394280A priority Critical patent/JPS5720987A/en
Publication of JPS5720987A publication Critical patent/JPS5720987A/en
Publication of JPS633393B2 publication Critical patent/JPS633393B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/02Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
    • G11C19/08Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
    • G11C19/0875Organisation of a plurality of magnetic shift registers

Description

【発明の詳細な説明】 本発明は磁気バブルメモリチツプの構成に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the construction of magnetic bubble memory chips.

第1図は従来のメイジヤマイナ方式の磁気バブ
ルメモリチツプの構成例を示す。図中、mは情報
を貯えるマイナループ群、MLは入出力情報を転
送する入出力転送路、Dは磁気バブルの有無を電
気信号に変換するバブル検出器、Gは情報を書き
込む磁気バブル発生器、S/Rはマイナループ群
mと入出力転送路MLを結合し、両者間で情報を
入れ替えるスワツプ動作や、マイナループ中の情
報を入出力転送路MLに複写するレプリケート動
作を行うゲート列、GRは前記各部分の外周を囲
み外部からの磁気バブル侵入を防止するガードレ
ール、BPは外部との接続に用いるボンデイング
パツドである。
FIG. 1 shows an example of the configuration of a conventional mager-Ya-miner type magnetic bubble memory chip. In the figure, m is a minor loop group that stores information, ML is an input/output transfer path that transfers input/output information, D is a bubble detector that converts the presence or absence of magnetic bubbles into an electrical signal, G is a magnetic bubble generator that writes information, S/R is a gate array that connects the minor loop group m and the input/output transfer path ML and performs a swap operation to exchange information between them and a replicate operation to copy information in the minor loop to the input/output transfer path ML, and GR is the gate array described above. The guardrail that surrounds the outer periphery of each part to prevent magnetic bubbles from entering from the outside, and the BP are bonding pads used for connection with the outside.

この様な構成の磁気バブルメモリチツプにおけ
る入出力転送路MLとマイナループmのパターン
周期の関係は、従来は第2図に例示したようにな
つていた。同図において、Eは入出力転送路ML
を形成する転送要素で、各マイナループmは単純
閉ループになつている。各マイナループ間の周期
をλn、入出力転送要素Eの周期をλMとするとき、
第2図ではλn=2λMとなつている。すなわち従来
の入出力転送要素Eは、1つのマイナループmに
対して2個の割合となつていた。
The relationship between the pattern periods of the input/output transfer path ML and the minor loop m in a magnetic bubble memory chip having such a configuration has conventionally been as illustrated in FIG. 2. In the same figure, E is the input/output transfer path ML
, and each minor loop m is a simple closed loop. When the period between each minor loop is λ n and the period of the input/output transfer element E is λ M ,
In Figure 2, λ n =2λ M. In other words, the conventional input/output transfer element E was two for one minor loop m.

これに対して入出力転送路MLの転送要素Eの
周期を2倍に拡大することにより、動作特性を向
上しようとする考えが従来からあつた。この方式
を2倍周期入出力転送路とよぶことにする。
On the other hand, there has been a conventional idea to improve the operating characteristics by doubling the period of the transfer element E of the input/output transfer path ML. This system will be referred to as a double period input/output transfer path.

第3,4図は、2倍周期入出力転送路の従来の
例を示す。第3図に示す例は、入出力転送要素E
の周期λ′Mを、マイナループ間周期λnと等しくす
ることにより2倍周期化している。第4図に示す
例は、各マイナループmを2重に折り重ねること
によりマイナループ間周期λ′nを2倍にし、入出
力転送要素Eの周期λ′Mも2倍にしている。第3
図の場合、各マイナループに対して1個の入出力
転送要素Eが対応するため、入出力動作時、入出
力転送路ML上の各ビツトに磁気バブル列が連続
することになる。この様にバブル列が連続して並
ぶと、バブル読み出し動作、あるいは書き込み動
作時、前後のバブルの影響を強く受けるという問
題がある。第4図の場合は第2図の場合同様、各
マイナループに対して2個の入出力転送要素Eが
対応しているから、入出力転送路ML上の磁気バ
ブル列は2ビツト間隔で並ぶので第3図の場合の
様な問題はないが、各マイナループが複雑化す
る、あるいは各マイナループの長さが2倍化する
という問題をもつている。
3 and 4 show conventional examples of double period input/output transfer paths. The example shown in FIG. 3 is the input/output transfer element E
The period λ′ M of is made equal to the inter-minor loop period λ n to double the period. In the example shown in FIG. 4, the inter-minor loop period λ' n is doubled by doubling each minor loop m, and the period λ' M of the input/output transfer element E is also doubled. Third
In the case of the figure, since one input/output transfer element E corresponds to each minor loop, magnetic bubble strings are continuous at each bit on the input/output transfer path ML during input/output operation. When the bubble rows are arranged consecutively in this way, there is a problem that the bubble read operation or write operation is strongly influenced by the bubbles before and after the bubbles. In the case of Fig. 4, as in the case of Fig. 2, two input/output transfer elements E correspond to each minor loop, so the magnetic bubble arrays on the input/output transfer path ML are arranged at 2-bit intervals. Although there is no problem as in the case of FIG. 3, there is a problem that each minor loop becomes complicated or the length of each minor loop doubles.

本発明の目的は上記従来の2倍周期入出力転送
路方式の問題点を解消した磁気バブルメモリチツ
プを提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a magnetic bubble memory chip that eliminates the problems of the conventional double-period input/output transfer path method.

上記目的を達成するために本発明においては、
多数個の単純閉ループよりなるマイナループ群
と、このマイナループ群の両端にそれぞれ2倍周
期の入出力転送路を設け、奇数番目のマイナルー
プはそれぞれ一端の入出力転送路に結合し、偶数
番目のマイナループはそれぞれ他端の入出力転送
路に結合するようにした。
In order to achieve the above object, in the present invention,
A minor loop group consisting of a large number of simple closed loops and an input/output transfer path with a double period are provided at both ends of this minor loop group, each of the odd-numbered minor loops is connected to one end of the input-output transfer path, and the even-numbered minor loops are connected to the input/output transfer path at one end. Each is connected to the input/output transfer path at the other end.

以下本発明を図面によつて更に詳細に説明す
る。第5図は、本発明を実施したメイジヤマイナ
方式2倍周期入出力転送路の磁気バブルメモリチ
ツプの構成を示す。図中、第1図中の符号と同じ
ものは第1図の場合と同じものを示す。構成上の
特徴は、各マイナループを奇数番目のマイナルー
プ群mと偶数番目のマイナループ群m′の2グル
ープに分け、入出力転送路、発生器、検出器、ゲ
ート列等を、両群ループが交互に横に並んだ両群
のマイナループの上下に、それぞれの群ごとに独
立に設けたことである。奇数番目のマイナループ
mは、上側のゲート列S/Rを介して入出力転送
路MLに結合され、発生器G、検出器Dにより情
報の入出力が行われる。偶数番目のマイナループ
m′は、下側のゲート列S′/R′を介して入出力転
送路ML′に結合され、発生器G′、検出器D′によ
り情報の入出力が行われる。第6図は、第5図に
示した構成の、マイナループm,m′と入出力転
送路ML,ML′のパターン周期の関係を示す。各
マイナループm,m′は単純閉ループになつてい
る。奇数番目マイナループm間の周期λ′n、偶数
番目マイナループm′間の周期λ′nは、各マイナル
ープ間隔λnの2倍になる。したがつて、入出力
転送路ML,ML′の要素E,E′の周期λ′Mは、λ′n
=2λ′M=2λnとなる。すなわち、奇数番目のマイ
ナループ群mと結合する入出力転送路MLの各要
素E、偶数番目のマイナループ群m′と結合する
入出力転送路ML′の各要素E′は、それぞれ2倍周
期化されており、両マイナループ群所属の各マイ
ナループそれぞれに対し、入出力転送路要素E,
E′はそれぞれ2個の割合になつている。
The present invention will be explained in more detail below with reference to the drawings. FIG. 5 shows the configuration of a magnetic bubble memory chip with a mager-minor type double period input/output transfer path in which the present invention is implemented. In the figure, the same reference numerals as in FIG. 1 indicate the same components as in FIG. 1. The structural feature is that each minor loop is divided into two groups, an odd-numbered minor loop group m and an even-numbered minor loop group m', and the input/output transfer paths, generators, detectors, gate arrays, etc. are arranged alternately between the two groups. They are provided independently for each group above and below the minor loops of both groups, which are lined up horizontally. The odd-numbered minor loops m are coupled to the input/output transfer path ML via the upper gate row S/R, and the generator G and detector D input and output information. Even numbered minor loop
m' is coupled to the input/output transfer path ML' via the lower gate array S'/R', and input/output of information is performed by the generator G' and detector D'. FIG. 6 shows the relationship between the pattern periods of the minor loops m, m' and the input/output transfer paths ML, ML' in the configuration shown in FIG. Each minor loop m, m' is a simple closed loop. The period λ' n between the odd-numbered minor loops m and the period λ' n between the even-numbered minor loops m' are twice the interval λ n of each minor loop. Therefore, the period λ′ M of the elements E and E′ of the input/output transfer paths ML and ML′ is λ′ n
=2λ′ M =2λ n . That is, each element E' of the input/output transfer path ML that connects to the odd-numbered minor loop group m, and each element E' of the input/output transfer path ML' that connects to the even-numbered minor loop group m' are each doubled in period. For each minor loop belonging to both minor loop groups, input and output transfer path elements E,
E' is in the proportion of two each.

以上説明したように本発明によれば、2倍周期
入出力転送路上に2ビツト間隔でバブル列が並ん
で良好な動作特性が得られ、しかも各マイナルー
プは簡単な形状の単純閉ループよりなる磁気バブ
ルメモリチツプが得られる。
As explained above, according to the present invention, bubble rows are lined up at 2-bit intervals on the double-period input/output transfer path, resulting in good operating characteristics, and each minor loop is a magnetic bubble consisting of a simple closed loop with a simple shape. Obtains a memory chip.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の磁気バブルメモリチツプ構成例
図、第2図は従来例のマイナループと入出力転送
路のパターン周期を示す図、第3,4図は2倍周
期入出力転送路方式の従来例図、第5図は本発明
一実施例図、第6図は本発明によるマイナループ
と入出力転送路の関係を示す図である。 m,m′……マイナループ、ML,ML′……入出
力転送路、E,E′……入出力転送要素、λM,λ′M
……入出力転送要素の周期、λn,λ′n……マイナ
ループ間隔。
Figure 1 is an example of the configuration of a conventional magnetic bubble memory chip, Figure 2 is a diagram showing the pattern period of the conventional minor loop and input/output transfer path, and Figures 3 and 4 are the conventional double-cycle input/output transfer path method. FIG. 5 is a diagram showing one embodiment of the present invention, and FIG. 6 is a diagram showing the relationship between the minor loop and the input/output transfer path according to the present invention. m, m'...minor loop, ML, ML'...input/output transfer path, E, E'...input/output transfer element, λ M , λ' M
... Period of input/output transfer element, λ n , λ′ n ... Minor loop interval.

Claims (1)

【特許請求の範囲】[Claims] 1 複数のマイナループm,m′と、該マイナル
ープの一方端に配置された第一の入出力転送路
MLと、上記マイナループの他端に配置された第
二の入出力転送路ML′と、奇数番目の上記マイナ
ループmと上記第一の入出力転送路MLとの間で
磁気バブルの転送を制御する第一のゲートS/R
と、偶数番目の上記マイナループm′と上記第二
の入出力転送路ML′との間で磁気バブルの転送を
制御する第二のゲートS/R′とを有し、上記第
一及び第二の入出力転送路における転送要素E,
E′の配列周期λM,λM′を隣合う上記複数のマイ
ナループm,m′の配列周期λmと等しくして成る
ことを特徴とする磁気バブルメモリチツプ。
1. A plurality of minor loops m, m' and a first input/output transfer path arranged at one end of the minor loops.
ML, a second input/output transfer path ML' arranged at the other end of the minor loop, and controlling the transfer of magnetic bubbles between the odd-numbered minor loop m and the first input/output transfer path ML. First gate S/R
and a second gate S/R' for controlling the transfer of magnetic bubbles between the even-numbered minor loop m' and the second input/output transfer path ML', The transfer element E in the input/output transfer path of
A magnetic bubble memory chip characterized in that the arrangement period λM, λM' of E' is equal to the arrangement period λm of the plurality of adjacent minor loops m, m'.
JP9394280A 1980-07-11 1980-07-11 Magnetic bubble memory chip Granted JPS5720987A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9394280A JPS5720987A (en) 1980-07-11 1980-07-11 Magnetic bubble memory chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9394280A JPS5720987A (en) 1980-07-11 1980-07-11 Magnetic bubble memory chip

Publications (2)

Publication Number Publication Date
JPS5720987A JPS5720987A (en) 1982-02-03
JPS633393B2 true JPS633393B2 (en) 1988-01-23

Family

ID=14096481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9394280A Granted JPS5720987A (en) 1980-07-11 1980-07-11 Magnetic bubble memory chip

Country Status (1)

Country Link
JP (1) JPS5720987A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5625285A (en) * 1979-08-09 1981-03-11 Fujitsu Ltd Magnetic bubble memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5625285A (en) * 1979-08-09 1981-03-11 Fujitsu Ltd Magnetic bubble memory unit

Also Published As

Publication number Publication date
JPS5720987A (en) 1982-02-03

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