JPS6333728B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high frequency amplifier circuit using a 4-pole MOS FET, and more particularly to a high frequency amplifier circuit that improves high frequency response changes when gain is attenuated by automatic gain control (hereinafter abbreviated as AGC).

Recently, high-frequency amplification circuits using MOS FETs have become popular, but when AGC is applied, the input/output impedance of the MOS FETs changes due to changes in operating voltage and current, and for this reason, the high-frequency response In extreme cases, this can even adversely affect image quality. This phenomenon is more pronounced in molded MOS FETs than in canned shielded MOS FETs. Qualitatively, this is considered to be due to an increase in feedback components due to the mold. Additionally, MOS FETs are inherently more prone to electrostatic damage than bipolar transistors, and although various circuit countermeasures have been taken, it is not possible to completely eliminate destruction accidents.

The present invention was made in view of the above circumstances, and
The impedance change due to AGC of MOS FET is
It is an object of the present invention to provide a high frequency amplifier circuit which can be corrected by adding another voltage variable impedance element that changes depending on the AGC voltage, and at the same time has increased strength against electrostatic damage.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic diagram of the invention. The input terminal 3 of the N-channel 4-pole MOS FET 1 is connected to the first gate 2, and the input terminal 3 is connected to the second gate 4 through a high resistance 5.
AGC power supply 6 is connected, and output terminal 8 is connected to drain 7.
is connected to the voltage variable impedance element 9, and further, a resistor 11 is connected to the source 10.

In other words, the second gate 4 of the 4-pole MOS FET 1
The impedance element 9 connected to the drain 7 of the FET 1 is changed in accordance with the change in the AGC voltage applied to the FET 1 through the high resistance 5.

In such a high frequency amplifier circuit, the high frequency response usually changes depending on AGC as shown in FIG. 2. In Figure 2, the solid line is at maximum gain (gain attenuation is zero), and the dotted line is at gain attenuation of 10 dB.
It's time. In FIG. 2, P is the video carrier frequency, S is the audio carrier frequency, and no particular channel is specified. The problem is that by applying AGC,
This is because the audio carrier frequency S of the high frequency response drops. Even if the gain is further reduced, the response does not change much. This phenomenon occurs because
This is because the input/output impedance of FET 1 changes by applying AGC.

The present invention aims to eliminate this phenomenon.
An example is shown in FIG. That is, the N-channel quadrupole MOS FET 12 has a first gate 13
An input terminal 15 is connected to via an input circuit 14,
A bypass capacitor 17 is connected to the second gate 16, and an AGC voltage application terminal 18 is also connected to the second gate 16.
An output end 21 is connected to the drain 19 via a high frequency tuning circuit 20, and a +B bias voltage application end 23 is connected to the source 22. A voltage variable capacitance diode 24 is connected between the drain 19 and the second gate 16 with its anode facing the second gate 16 side. The high frequency tuning circuit 20 includes a resistor 25
It is connected to the +B bias voltage application terminal 23 via. Further, the first gate 13 is connected to the +B bias voltage application terminal 23.

In other words, by applying AGC, FET1
The input/output impedance of the input/output circuit 2 changes, but since the bandwidth of the input circuit 14 is sufficiently wide compared to the bandwidth of the high frequency tuning circuit 20, which is an interstage circuit, we will ignore the change in input impedance here. Focusing only on the output impedance, at a relatively high frequency (200MHz), increasing the output capacitance of the FET 12 by AGC is effective, and at a relatively low frequency (100MHz), decreasing the output resistance is effective. In other words, in the case of television channels, the compensation method is to reduce the primary side tuning capacity of the high frequency tuning circuit 20 when AGC is applied in the high channel channel, and to increase the load Q in the low channel channel. It is. Next, to describe the circuit operation of FIG. _{0V at the time of attenuation (V AGC =} 8~0V) is applied to the drain 19 of the FET 12.
+B bias voltage (e.g.
16V) is supplied, and a drain current I _d is flowing. The potential V _D of the drain 19 has a value obtained by subtracting the product of the resistor 25 and the drain current I _d from the +B bias voltage. When the AGC voltage decreases, the drain current I _d also decreases, so the drain potential V _D
The value of increases. Thus, the voltage variable capacitance diode 24 connected between the second gate 16 and the drain 19 of the FET 12 is never conductive because the cathode side potential is always high. That is, the diode 24 is reverse biased with a voltage _VR that is the difference between the drain voltage V _D and the AGC voltage V _AGC . These voltages
Figure 4 shows the values of V _D , V _AGC , and _VR . Junction capacitance of diode 24 for this reverse bias voltage V _R
The relationship between C _j and load Q shows characteristics as shown in FIG. Assuming that the FET 12 is now operating in the maximum gain state, the drain current I _d will be the maximum (reverse AGC method is used), the voltage drop across the resistor 25 will be the maximum, and the drain potential V _D will be the minimum. On the other hand, since the AGC voltage V _AGC is the maximum at this time, the voltage V _R (V _R =V _D -V _AGC >0) is the minimum, so the junction capacitance C _j is the maximum and the load Q is the minimum. When AGC is applied and the AGC voltage V _AGC decreases, the drain current I _d also decreases, and the drain potential V _D
conversely increases, so the voltage V _R gradually increases,
At maximum attenuation, the voltage V _R is at its maximum, so the capacitance C _j is at its minimum and the load Q is at its maximum. To explain the above using the response in Figure 2, when AGC is applied, the dotted line waveform shows that the tuning capacity decreases and at the same time the load Q increases, so the audio carrier frequency S side is raised, and the solid line (maximum This means that the waveform approaches that of the gain mode.

Next, FIG. 6 shows another embodiment of the present invention. In this case, the voltage variable capacitance diode 26 is replaced by an FET.
The anode is connected between the drain 19 and source 22 of No. 12 with the anode facing the source 22 side. In other words, the potential on the cathode side of the diode 26 is the same as that shown in FIG. 3, so I will omit it and explain only the anode potential of the diode 26. When _AGC voltage _V resistor 2 connected to source 22 of
The voltage drop due to 7 is maximum. On the other hand, FET1
The source 22 of No. 2 is supplied with the +B bias voltage via the resistor 28, and the current flowing through this resistor 28 is minimized. However, as a result, FET12
The source potential of is maximum. Conversely, at maximum attenuation
The source potential of FET 12 is at its minimum. That is,
The source potential of the FET 12 moves in exactly the same direction as the potential of the second gate 16. Since the anode of the voltage variable capacitance diode 26 is grounded by the bypass capacitor 29 in terms of high frequency, it operates almost the same as the circuit shown in FIG. 3. Another advantage of this circuit is that, in particular, negative pulses can be prevented from entering the positive potential drain 19 of FET 12 by the bypass effect of diode 26.

As described above, according to the present invention, it is possible to provide a high frequency amplifier circuit using a 4-pole MOS FET that has excellent AGC characteristics and is resistant to electrostatic damage with a simple configuration. Therefore, it is particularly suitable for use in television channels.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration explanatory diagram for explaining the present invention, FIG. 2 is a diagram showing high frequency response characteristics of a general high frequency amplifier circuit, FIG. 3 is a circuit diagram showing one embodiment of the present invention, and FIG. Figure 4 is a diagram showing an example of the gain attenuation characteristics with respect to the voltage of each part of the circuit in Figure 3, Figure 5 is a diagram showing an example of the junction capacitance C _j and load Q characteristics of the circuit in Figure 3, and Figure 6 FIG. 2 is a circuit diagram showing another embodiment of the present invention. 1...4-pole MOS FET, 3...input end, 6...
...AGC power supply, 8... Output end, 9... Voltage variable impedance element, 14... Input circuit, 20...
High frequency tuning circuit, 24...voltage variable capacitance diode.

Claims (1)

[Claims] 1. A MOSFET having a source, a drain, and first and second gates; means for applying an input signal to the first gate and applying an AGC voltage to the second gate; and the source. and means for connecting the drain to a tuning circuit forming a signal output circuit; one end connected to the drain and the other end connected to the
Connect to a point that generates the AGC voltage or a voltage proportional to this AGC voltage and reverse bias it.
A high-frequency amplifier circuit comprising a voltage variable capacitance element whose capacitance value changes according to changes in AGC voltage. 2. The high frequency device according to claim 1, wherein the voltage variable capacitance element is a voltage variable capacitance diode, an anode of which is connected to the second gate, and a cathode of which is connected to the drain. Amplification circuit. 3. The voltage variable capacitance element is a voltage variable capacitance diode, and its anode is connected to the source and the first
2. The high frequency amplifier circuit according to claim 1, wherein the high frequency amplifier circuit is connected to a connection point with a resistor, and a cathode is connected to the drain.