JPS6332636A - Starting system for fixed cycle interruption program - Google Patents

Starting system for fixed cycle interruption program

Info

Publication number
JPS6332636A
JPS6332636A JP17556186A JP17556186A JPS6332636A JP S6332636 A JPS6332636 A JP S6332636A JP 17556186 A JP17556186 A JP 17556186A JP 17556186 A JP17556186 A JP 17556186A JP S6332636 A JPS6332636 A JP S6332636A
Authority
JP
Japan
Prior art keywords
cycle
programs
same
program
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17556186A
Other languages
Japanese (ja)
Other versions
JPH0461378B2 (en
Inventor
Masanori Hikichi
引地 正則
Hiroshi Sugiura
杉浦 寛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Fuji Facom Corp
Original Assignee
Fuji Electric Co Ltd
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Facom Corp filed Critical Fuji Electric Co Ltd
Priority to JP17556186A priority Critical patent/JPS6332636A/en
Publication of JPS6332636A publication Critical patent/JPS6332636A/en
Publication of JPH0461378B2 publication Critical patent/JPH0461378B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4812Task transfer initiation or dispatching by interrupt, e.g. masked

Abstract

PURPOSE:To execute the programs having the same interruption level and the same cycle in a fixed cycle by setting a start delay time to each fixed cycle interruption program and eliminating the cycle variance caused by the difference of the program processing times. CONSTITUTION:When two programs A and B having the same interruption level and to be executed in the same cycle T are available, the start delay times of both programs are set at T10 and T20 respectively. Then a fixed cycle table is produced after retrieval of programs and those start delay time are set to this table. When the times T10 and T20 are counted down by 1 to zero, the corresponding program is executed and at the same time the cycle T is set to the fixed cycle table. Thus both programs A and B are executed in the cycle T and therefore the cycle variance due to the difference of processing times between both programs. Then it is possible to execute plural programs having the same interruption level and the same cycle in a fixed cycle.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、プログラマブルコントローラのアプリケー
ションプログラムの如く、一定時間毎の割込み処理にて
実行される定周期割込みプログラムの起動方式に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for starting a periodic interrupt program, such as an application program of a programmable controller, which is executed by interrupt processing at regular intervals.

〔従来の技術〕[Conventional technology]

定周期プログラムの起動に当たっては、各プログラムの
周期Tをセットしておく定周期テーブルが用いられる。
When starting a fixed cycle program, a fixed cycle table is used in which the cycle T of each program is set.

第3図に定周期テーブルの例を示す。この定周期テーブ
ルには同図の如く、定周期割込プログラム番号(阻)と
、周期T(’r+、T2・・・・・・)とが格納される
FIG. 3 shows an example of a periodic table. As shown in the figure, this fixed period table stores the fixed period interrupt program number (interruption) and the period T ('r+, T2 . . . ).

第4図に定周期テーブル作成のための手・頂を示す。す
なわち、イニシャル時に各プログラムの検索を行い(■
参照)、次いで定周期テーブルを作成しく■参照)、こ
のテーブルに各プログラムの周期をセットして完了する
(■参照)。
Figure 4 shows the hands and tops for creating a periodic table. In other words, each program is searched at the time of initialization (■
), then create a fixed cycle table (see ■), set the cycle of each program in this table, and complete (see ■).

こうして作成された定周期テーブルにもとづき、第5図
の如き手順で各プログラムが実行される。
Based on the fixed-period table thus created, each program is executed according to the procedure shown in FIG.

まず、プログラム登録数が零か否かの判定が行われる(
■参照)。通常は零でないので、タイマによる割込処理
により、登録されている全定周期プログラムの周期(周
期に対応するカウント@)が1つずつ順次カウントダウ
ンされる(■参照)。
First, it is determined whether the number of registered programs is zero (
■Reference). Normally, it is not zero, so by interrupt processing by the timer, the cycles (counts corresponding to cycles) of all registered periodic programs are sequentially counted down one by one (see ■).

次いで、周期が零となったプログラムの起動フラグを全
てセットしく■参照)、以後はこのフラグとプログラム
の優先(割込)レベルに応じた処理が行われる(■、■
参照)。つまり、周期が零となったプログラムのうち、
最も割込レベルの高いプログラムの周期全プリセットし
く■参照)、プログラム起動処理をして(■参照)、プ
ログラムを実行する(■参照)。この処理が終ると再び
セットされている起動フラグがあるか否かを調べ、あれ
ばその割込レベルの高いものから処理をする手順を、セ
ットされている起動フラグが無くなるまで繰り返す。こ
のとき、同一の割込レベルをもつ同一周期のプログラム
が複数ある場合は、それらは同時に起動され、ンペル内
の登録優先順位に従って1狐次実行されることになる。
Next, set all startup flags for programs whose cycles have become zero (see ■), and from then on, processing is performed according to these flags and the priority (interrupt) level of the program (■, ■
reference). In other words, among programs whose period is zero,
Preset all cycles of the program with the highest interrupt level (see ■), perform program startup processing (see ■), and execute the program (see ■). When this process is completed, it is checked again whether or not there are activation flags that have been set. If so, the process is performed starting from the one with the highest interrupt level. This procedure is repeated until there are no activation flags that are set. At this time, if there are a plurality of programs with the same interrupt level and the same cycle, they will be started at the same time and executed in the order of priority registered in the program.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、このような方式では同じ割込レベルで第
1番目に実行されるプログラムの処理時間にバラツキが
生じると、第2番目以降に実行されるプログラム周期に
ずれが生じると云う問題がある。
However, with this method, there is a problem in that if there is variation in the processing time of the first program to be executed at the same interrupt level, there will be a shift in the cycle of the second and subsequent programs.

この点を具体的に示したのが第6図である。これは、同
一割込レベルをもつ同一周期のプログラムはこ\ではA
、Bの如く2つで、プログラムBよりもAの方が登録優
先順位が高く、プログラムAが第5図に示す割込処理プ
ログラムのスタート時点t8から一定周期(T)Ej!
過後の時刻t。で実行されたときの処理時間をtl、時
刻t。から一定周期(T)経過後の処理時間をt2とし
た場合の例を示しており、このときのプログラムBの周
期は、 T±(12−1,) となり、プログラムAの処理時間に影響を受けて一定周
期が確保されないことになる。
FIG. 6 specifically shows this point. This means that programs with the same interrupt level and the same period are A in this case.
, B, and program A has a higher registration priority than program B, and program A has a fixed cycle (T) Ej! from the start time t8 of the interrupt processing program shown in FIG.
Later time t. The processing time when executed at tl is time t. An example is shown in which t2 is the processing time after a certain period (T) has elapsed from As a result, a fixed cycle cannot be guaranteed.

したがって、この発明は上述の如き同一割込レベルをも
つ同一周期のプログラムにおいて、プログラムの処理時
間の違いによる周期Tのずれをなくシ、同一割込レベル
をもつ同周期のプログラムを一定の周期で実行可餌とす
ることを目的とする。
Therefore, the present invention eliminates the deviation in the period T due to the difference in program processing time in programs having the same interrupt level and the same cycle as described above, and allows programs having the same interrupt level and the same cycle to be processed at a constant cycle. The purpose is to make it viable bait.

〔問題点を解決するための手段〕[Means for solving problems]

同じ割込レベルをもち同じ同期で実行される定周期割込
プログラムの各々に、基準時点からの起動遅れ時間をそ
れぞれ設定し、この起動遅れ時間の経過後から一定の周
期をもって各プログラムを起動する。
A startup delay time from a reference time is set for each of the fixed-cycle interrupt programs that have the same interrupt level and are executed in the same synchronization, and each program is started at a fixed cycle after this startup delay time has elapsed. .

〔作用〕[Effect]

定周期割込プログラムの各々に起動遅れ時間を設定する
ことにより、同一割込レベルをもつ同一周期のプログラ
ムが同一レベルの他のプログラムの実行時間に影響を受
けないようにし、常に一定の周期で実行されるようべし
て安全性、信頼性を向上させる。
By setting a startup delay time for each fixed-cycle interrupt program, programs with the same interrupt level and the same cycle can be prevented from being affected by the execution time of other programs with the same level, and can always be executed at a constant cycle. It should be implemented to improve safety and reliability.

〔実施例〕〔Example〕

第1図はこの発明の詳細な説明するためのフローチャー
ト、第2図はこの発明による動作を説明するためのタイ
ムチャートである。
FIG. 1 is a flow chart for explaining the invention in detail, and FIG. 2 is a time chart for explaining the operation of the invention.

に まず、各プログラム番号を付与するとへもに、△ それぞれの動作周期T、プログラムスタート時からの起
動遅れ時間Tiを成る特別の命令(例えば、Prog命
令)により予め定義しておき、そのイニシャル時に第1
図の如き手頚により、起動遅れ時間′riを第6図と同
様の定周期テーブルにセットする。その後は、従来の場
合と同様にTiを1ずつカウントダウンシ、零になった
時点で対応するプログラムを実行すると同時に、周期T
を定周期テーブルにセットすることにより、該当プログ
ラムが周期Tで実行されるようにする。なお、上記のプ
ログラム番号は、割込レベルや優先順位等も考慮した形
で各プログラムに与えられるものとする。
First, in addition to assigning each program number, the operating cycle T and startup delay time Ti from the start of the program are defined in advance by a special instruction (for example, a Prog instruction), and the 1st
Using the hand and neck as shown in the figure, the activation delay time 'ri is set in a fixed periodic table similar to that shown in FIG. After that, as in the conventional case, Ti is counted down by 1, and when it reaches zero, the corresponding program is executed, and at the same time, the period T
By setting the period T in the fixed period table, the corresponding program is executed at the period T. Note that the above program number is given to each program in consideration of the interrupt level, priority order, etc.

以上の様子を示すのが第2図である。こ〜では同じ割込
レベルをもち同じ周期Tで実行されるプログラムがA、
Bと2つある場合で、プログラムA、Bの起動遅れ時間
がそれぞれTlG + T’2o  に設定された例・
が示されている。
FIG. 2 shows the above situation. Here, the programs that have the same interrupt level and are executed at the same period T are A,
An example where there are two programs A and B, and the startup delay time of programs A and B are each set to TlG + T'2o.
It is shown.

このように、プログラマブルコントローラの定周期割込
プログラムに起動遅れ時間を設定可能とすることにより
、同一割込レベルをもつ同一周期Tのプログラムが同一
レベルの他のプログラムの実行時間のバラツキに関係な
く、常に周期Tで正確に実行されることになる。
In this way, by making it possible to set the startup delay time for the fixed-cycle interrupt program of the programmable controller, programs with the same interrupt level and the same period T can be executed regardless of variations in the execution time of other programs at the same level. , will always be executed exactly with period T.

〔発明の効果〕〔Effect of the invention〕

この発明によれば、同一割込レベルをもつ同一周期のプ
ログラムにおいて起動遅れ時間を設定可能としたので、
同一割込レベルをもつ同一周期のプログラムの処理時間
による周期のずれをなくし、一定の周期で実行すること
ができる利点がもたらされる。その結果、安定性および
信頼性の高いプログラマブルコントローラを提供し得る
利点がもたらされる。
According to this invention, since it is possible to set the startup delay time for programs with the same interrupt level and the same cycle,
This provides the advantage that programs having the same interrupt level and having the same cycle can be executed at a constant cycle by eliminating cycle shifts due to processing time. This results in the advantage of providing a programmable controller with high stability and reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の詳細な説明するためのフローチャー
ト、第2図はこの発明による動作を説明するためのタイ
ムチャート、第3図は定周期テーブルを示す概要図、第
4図は定周期テーブル作成子j負を説明するためのフロ
ーチャート、第5図は割込処理手順を説明するためのフ
ローチャート、第6図は従来の定周期プログラム起動方
式による動作例を示すタイムチャートである。 符号説明 T + T1 + T2 ”””周期、T i * T
’to # T20 ”””起動遅れ時間、tl、t2
・・・・・・処理時間。 W+図 冥 2 図 ツー0ワフム+1ンート 第:11!1 填 4 図 第5 図
Fig. 1 is a flowchart for explaining the invention in detail, Fig. 2 is a time chart for explaining the operation of the invention, Fig. 3 is a schematic diagram showing a fixed periodic table, and Fig. 4 is a fixed periodic table. FIG. 5 is a flowchart for explaining the interrupt processing procedure, and FIG. 6 is a time chart showing an example of operation according to the conventional fixed-period program starting method. Symbol explanation T + T1 + T2 “”” period, T i * T
'to # T20 """Startup delay time, tl, t2
······processing time. W+Figure 2 Figure 2 0 Wahum + 1 Note No. 11! 1 Fill 4 Figure 5

Claims (1)

【特許請求の範囲】 同一の割込レベルをもち同一周期で実行される複数の定
周期割込プログラムにおいて、 該定周期割込プログラムの各々に基準時点からの起動遅
れ時間をそれぞれ設定し、 該起動遅れ時間の経過後から一定の周期をもつて各プロ
グラムを起動することを特徴とする定周期割込プログラ
ムの起動方式。
[Scope of Claims] In a plurality of fixed period interrupt programs having the same interrupt level and executed in the same cycle, a startup delay time from a reference time is set for each of the fixed period interrupt programs, and A fixed-cycle interrupt program startup method characterized by starting each program at regular intervals after a startup delay time has elapsed.
JP17556186A 1986-07-28 1986-07-28 Starting system for fixed cycle interruption program Granted JPS6332636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17556186A JPS6332636A (en) 1986-07-28 1986-07-28 Starting system for fixed cycle interruption program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17556186A JPS6332636A (en) 1986-07-28 1986-07-28 Starting system for fixed cycle interruption program

Publications (2)

Publication Number Publication Date
JPS6332636A true JPS6332636A (en) 1988-02-12
JPH0461378B2 JPH0461378B2 (en) 1992-09-30

Family

ID=15998232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17556186A Granted JPS6332636A (en) 1986-07-28 1986-07-28 Starting system for fixed cycle interruption program

Country Status (1)

Country Link
JP (1) JPS6332636A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08339317A (en) * 1995-04-06 1996-12-24 Bull Sa Periodic polling management apparatus for monitoring of information processing resource in network and method executed by said apparatus
US9727124B2 (en) 2011-04-19 2017-08-08 Apple Inc. Power saving application update in a portable electronic device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5238368A (en) * 1975-09-16 1977-03-24 Umekichi Mochizuki Process for reusing paper tndustry sludge
JPS5739452A (en) * 1980-08-20 1982-03-04 Toshiba Corp Timer interruption system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5238368A (en) * 1975-09-16 1977-03-24 Umekichi Mochizuki Process for reusing paper tndustry sludge
JPS5739452A (en) * 1980-08-20 1982-03-04 Toshiba Corp Timer interruption system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08339317A (en) * 1995-04-06 1996-12-24 Bull Sa Periodic polling management apparatus for monitoring of information processing resource in network and method executed by said apparatus
US9727124B2 (en) 2011-04-19 2017-08-08 Apple Inc. Power saving application update in a portable electronic device

Also Published As

Publication number Publication date
JPH0461378B2 (en) 1992-09-30

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