JPS6332288B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital filter without a zero point used, for example, in speech synthesis.

In order to synthesize speech from its characteristic parameters, the output of a pulse generator that simulates the vibration of the vocal cords and the output of a noise generator that simulates turbulence are switched or mixed depending on the voiced or unvoiced state, and the output is A driving sound source signal was created by amplitude modulating the signal according to the voice amplitude, and this was passed through a filter that simulated the resonance characteristics of the vocal tract to obtain synthesized speech. As described above, one of the main parts of speech synthesis is a filter that simulates the resonance characteristics of the vocal tract, and various filters have been used for this purpose in the past. It is known that a rational function filter having no zero point, that is, an all-pole filter, is effective as one of the filters suitable for this purpose (see, for example, Japanese Patent No. 670635, Speech Decomposition and Synthesis Apparatus).

The transfer function of the all-pole filter is expressed by the following equation.

H(z)=A/1+α ₁ Z+α ₂ Z ² +……+
α _p Z ^p , Z=e ^-j 〓(1) Then, ω is the normalized angular frequency 2πf△T, △T=
The sampling frequency, f=frequency, A represents the gain of the filter, and α ₁ , α ₂ , . . . , α _p are parameters for controlling the resonance characteristics of the filter.

Equation (1) is realized as a filter using a block diagram as shown in FIG. The input from the input terminal 11 is multiplied by A by the multiplier 12 and supplied to the adder 13. The adder 13 takes the difference from the output of the adder 14 and supplies it to the output terminal 15. The output of the output terminal 15 is supplied to a series circuit of delay circuits D ₁ to _{D p} each having a delay time of one sampling period, and each output of each of these delay circuits D ₁ to _{D p} is supplied to a multiplier M ₁ to D p, respectively. M _p is multiplied by coefficients α ₁ to α _p , respectively.
The multiplication outputs are sequentially added and all are added together by an adder 14.

In order for this filter to be a stable filter,
All zero points of the polynomial A _p (Z) = 1 + α ₁ Z + ... + α _p Z ^p in the denominator of equation (1) must be outside the unit circle on the Z plane.

In the configuration shown in Figure 1, the parameter {α _i }
By precisely controlling and A, it is possible to use it as a speech synthesis filter to synthesize extremely high quality speech. However, when {α _i } is coarsely quantized and encoded, the filter becomes unstable and the resonance characteristics are significantly distorted. This is the polynomial A _p with respect to Z in the denominator of the transfer function H(z) when the deviation due to quantization is added to the parameter α _i
This is because there is a possibility that any root of (z) will be included within the unit circle. It has been experimentally shown that the number of quantization bits for each α _i required to sufficiently prevent this possibility is 10 bits or more, which makes it difficult to reduce the It was becoming an obstacle.

This invention eliminates the disadvantage of requiring a large number of quantization bits for each filter coefficient α _i when directly realizing an all-pole filter with the resonance characteristic expressed by equation (1), and reduces the number of quantization bits. The present invention provides an all-pole filter that can more faithfully synthesize the resonance characteristics of audio using the number of quantization bits.

By the way, the polynomial A _p (Z) in the denominator of equation (1) has the relationship A _p (Z) = A _p-1 (Z) - k _p Z ^p A _p-1 (Z ^-1 ) (1)' . Here k _p is a parameter called PARCOR coefficient. (1)′ From A _p+1 (Z)=A _p (Z)−k _p+1 Z ^p+1 A _p (Z ^-1 )(1)″ Here k _p+1 is forced to +1 or If you set it to -1, you will get the following two polynomials.

P _p (Z)=A _p (Z)−Z ^p+1 A _p (Z ^-1 ) (2) Q _p (Z)=A _p (Z)+Z ^p+1 A _p (Z ^-1 ) (3 ) At this time, the roots of P _p (Z) = 0 and Q _p (Z) = 0 exist on the unit circle. Since (Z _i +Z _i ^-1 ) = 2COSω _i
P _p (Z) and Q _p (Z) are the following when p is an even number.
It is factorized as shown in equations (4) and (5).

P _p (Z)=(1-Z) _P/2 〓 ⁱ⁼¹ (1-2COSω _i Z+Z ² ) (4) Q _p (Z)=(1+Z) _P/2 〓 ⁱ⁼¹ (1-2COSθ _i Z+Z ² ) (5) Similarly, when p is an odd number, the following (6) and (7)
is obtained.

P _p (Z)=(1-Z ² ) _(P-1)/2 〓 ⁱ⁼¹ (1-2COSω _i Z+Z ² )
(6) Q _p (Z)= _(P+1)/2 〓 ⁱ⁼¹ (1−2COSθ _i Z+Z ² ) (7) Here, ω _i and θ _i are included in the domain [0, π] With constants, the arrangement is as shown in FIG. 6 (in the case of p=8). As is clear from this figure, P _p (Z) = 0,
The roots of Q _p (Z)=0 (strictly speaking, the argument angles of the roots) alternate with each other and have the following ordering relationship (when p is an even number).

0 = ω ₀ < θ ₁ < ω ₁ <...< θ ₄ < ω ₄ < θ ₅ = π On the other hand, the all-pole filter expressed by equation (1) has A in the negative feedback path as shown in Figure 7A. This is realized by a cyclic filter including a backward transfer characteristic of _p (Z)-1.
From equations (2) and (3), A _p (Z)-1 is given by equation (8) using P _p (Z) and Q _p (Z).

A _p (Z)-1=1/2 {P _p (Z)-1+Q _p (Z)-1}
(8) Therefore, the all-pole filter of equation (1) is realized by a recursive filter having two negative feedback paths as shown in FIG. 7B. Furthermore, P _p (Z)-1 and Q _p (Z)-1 are expanded as shown below depending on whether p is odd or even.
If p is an even number, the following identity is obtained from equations (4) and (5).

P _p (z)-1=(1-Z) _P/2-1 〓 ⁱ⁼¹ (1-2cosω _i Z+Z ² )-1 =Z{(a ₁ +Z)+ _P/2-1 〓 ⁱ⁼¹ (a _i+1 +Z) _i 〓 ^j=1 (1+a _j Z+Z ² )− _P/2 〓 ^j=1 (1+a _j Z+Z ² )} (9) Q _p (z)−1=Z{(b ₁ +Z )+ _P/2-1 〓 ⁱ⁼¹ (b _i+1 +Z) _i 〓 ^j=1 (1+b _j Z+Z ² )+ _P/2 〓 ^j=1 (1+b _j Z+Z ² )} (10) However, a _i = −2cosω _i b _i = −2cosθ _i (11) Using the relationships shown in equations (8), (9), and (10), the digital filter with the all-pole transfer function shown in equation (1) can be expressed as It can be constructed using the block diagram shown in FIG. FIG. 2 shows the case when p=8.

The input from the input terminal 11 is added to the output of the adder 17 in the adder 16, and the added output is supplied to the output terminal 15, and the coefficient multiplier 18 adds -
It is multiplied by 1/2. This 1/2 times corresponds to 1/2 times the right side of equation (8). The output of the coefficient unit 18 is supplied to a delay unit 19 for one sampling period, that is, a unit time, and the output thereof is supplied to delay units 21 and 22, coefficient units 23 and 24, and adders 25 and 26, respectively. Coefficient unit 2
3 and 24, the inputs are multiplied by a ₁ and b ₁ , respectively, and the multiplied outputs are sent to the delay devices 21 and 24, respectively.
22 and adders 27 and 28. The outputs of adders 27 and 28 are supplied to adder 29 and also to adders 25 and 26 through delay devices 31 and 32, respectively. The outputs of the adders 25 and 26 are supplied to delay units 33 and 34, coefficient units 35 and 36, and adders 37 and 38, respectively.
In 36, the inputs are multiplied by coefficients a ₂ and b _2, respectively, and the outputs are added to the outputs of delay devices 33 and 34 in adders 41 and 42, respectively, and the added output is supplied to adder 43. It is also supplied to adders 37 and 38 through delayers 44 and 45. The addition output is subtracted by an adder 17.

The delay device 19 corresponds to Z outside { } in equations (9) and (10), and includes delay devices 21, 31, adders 27, 25, coefficient unit 23, delay devices 33, 44, adder 37, 4
1, the coefficient unit 35 is 2 of 1 + Z (a _j + Z), respectively.
The next filters 46 and 47 are configured in the same way, and the delay units 22 and 32, the adders 26 and 28, the coefficient unit 24,
Further, the delay units 34, 45, the adders 38, 42, and the coefficient unit 36 constitute 1+Z (b _j +Z) secondary filters 48, 49, respectively. Therefore, by connecting the secondary filters 46 and 47 in series, the third term in { } of equation (9) is realized, and the delay unit 33, coefficient unit 35, and adder 41 in the filter 47 are (a _{i+ 1} + Z)
This circuit and the secondary filter 4
6, the second term in { } of equation (9) is realized,
Its output is supplied to adder 17 through adder 43. The delay unit 21, coefficient unit 23, and adder 27 in the secondary filter 46 realize (a ₁ +Z), and the output thereof is sent to the adder 17 through the adders 29 and 43 in sequence.
supplied to In this way, the secondary filter 4
6, 47 and adders 17, 29, 43 realize the part in { } of equation (9).

Similarly, secondary filters 48, 49, adder 1
7, 29, and 43 realize the part in { } of equation (10). Equations (9) and (10) differ only in the sign of the third term in { } in their formats, and due to this difference, the input sign to the adder 17 is different. Therefore adder 1
7, coefficient unit 18, delay unit 19, secondary filter 46
.about.49 realizes equation (8), and FIG. 2 as a whole realizes equation (1). This circuit has a main circuit 51 in which equations (9) and (10) are connected in series with p/2 secondary filters 46 and 47, respectively, in the feedback path.
A main circuit 52 is constructed in which p/2 secondary filters 48, 49 are connected in series, and taps 53, 54 are connected to the nodes of each section of this main circuit 51, that is, from the output sides of adders 27, 41, p ₁ , p ₂ and are summed by adders 29, 43, and 17. The configuration in which the output is taken from the tap of the main circuit in this manner will be referred to as a tap output type.

In FIG. 2, the secondary filter with the smaller value of j is placed on the output terminal 15 side, and the larger the value of j, the closer it is to the adder 17, but conversely, the side that is closer to the adder 17 side 2, so that the value of j is small
The following filters may be arranged. In that case, for example, as shown in FIG. 3, the output of the delay device 19 is supplied to secondary filters 47' and 49';
The outputs of 7' and 49' are added by an adder 17 through secondary filters 46' and 48'. Secondary filter 4
6' to 49', the front and back of each node of each secondary filter 46 to 49 are swapped, that is, the order of the circuit for adding the outputs of each delay device and coefficient device and the delay device is swapped. . The output of delay device 19 is tap 5.
3', 54' to the nodes of the secondary filters 46', 47', that is, it is of the tap input type as compared to FIG. input from tap 53', adder 1
7 constitutes the first term in { } of equation (9), and the circuit from tap 54' to adder 17 constitutes the second term. The main circuit 52' and secondary filters 48' and 49' are similarly constructed. Trunk circuit 5
1' is multiplied by -1 in the coefficient unit 55,
A negative sign for the third term in { } of equation (9) is realized.

If p is an odd number, the following identity is obtained from equations (6) and (7).

P _p (z)−1=Z{(a ₁ +Z)+ _(P-3)/2 〓 ⁱ⁼¹ (a _i+1 +Z) _i 〓 ^j=1 (1+a _j Z+Z ² )−Z _{(P- 1)/2} 〓 ^j=1 (1+a _j Z+Z ² )} (12) Q _p (z)−1=Z{(b ₁ +Z)+ _(P-1)/2 〓 ⁱ⁼¹ (b _i+1 +Z) _i 〓 ^j=1 (1+b _j Z+Z ² )} (13) Then, a _i = −2cosω _i b _i = −2cosθ _i (14) In the same way as when p is even, when p is odd too
From the relational expressions (8), (12), and (13), two types of digital filters called a tap output type and a tap input type can be realized by the configurations shown in FIGS. 4 and 5, respectively. In Figures 4 and 5, p=
It was assumed that 9. Note that, as is clear from the above filter configuration method, the permutation of the parameters (a ₁ , a ₂ , . . . ) or (b ₁ , b ₂ , . . . ) within each ( ) is arbitrary. Furthermore, Figure 2, Figure 3 or Figure 4
As is clear from FIG. 5, the digital filter of the present invention is composed of a secondary filter section with a tap output or a tap input.
Since each section within the filter has the same format, it is possible to easily share the same hardware by time division multiplexing. In other words, the series connection of the secondary filters means that the operations only need to be performed in series. Further, the -1/2 coefficient unit 18 and the delay unit 19 may be inserted at any position in the feedback circuit. In the tap output type, adders 29 and 43 may be provided separately in both trunk circuits 51 and 52.

In _short , the present invention converts an all-pole digital filter _{whose transfer function is expressed by equation (1) into P p (} z)-1,
When Q _p (z)-1 is factorized into a quadratic function of Z, each factor is configured with a quadratic filter section, and these are connected in series to configure two main circuits. are connected in parallel, and a 1/2 multiplier circuit 18 and a Z multiplier circuit 19 are inserted in common to form a feedback circuit. In that case, by configuring the main circuit as a tap output type or a tap input type, the circuit can be shared and configured easily.

As explained above, in the all-pole digital filter according to the present invention, the resonance characteristics of the filter are determined by the parameters a _i , b _i , that is, the frequency domain parameters ω _i ,
Since it is controlled by θ _i , it is possible to quantize and encode ω _i or θ _i to relatively low bits. According to the results of experimental studies, it has been confirmed that when the present invention is used for speech synthesis, extremely good synthesized speech can be obtained by quantizing ω _i and θ _i to 4 bits. In addition, the filter control parameters ω _i ,
θ _i or a _i , b _i is temporally coarse (for example, 20 m
sec), it is possible to synthesize good speech by linearly interpolating these parameters.

Therefore, by using this invention for speech synthesis, compared to conventional synthesis digital filters,
This has the advantage that high quality synthesized speech can be generated with a smaller amount of supplied information.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a conventional all-pole digital filter, and FIG. 2 is a diagram showing an example of an all-pole digital filter according to the present invention configured as a tap output type when the filter order p is an even number. Third
The figure shows an example of the configuration of a filter according to the present invention which is a tap input type when the filter order p is an even number, and Fig. 4 is an example of the configuration of a filter which uses the present invention as a tap output type when the filter order is an odd number. A diagram showing
FIG. 5 is a diagram showing a configuration example of a tap input type filter according to the present invention when the order of the filter is an odd number, FIG. 6 is a diagram showing the arrangement of roots of P(Z) and Q(Z), and FIG. FIG. 7 is a diagram showing a modification method of an all-pole filter. 11: Input terminal, 15: Output terminal, 18: 1/2
Coefficient unit, 19, 21, 22, 31, 32, 33,
34, 44, 45: unit time delay device, 23, 2
4, 35, 36: Coefficient unit, 46 to 49: Secondary filter, 51, 52: Main circuit, 53, 54: Tap.

Claims (1)

[Scope of Claims] 1. Adding means to which an input signal is supplied and whose output is a filter output; first and second adder means to which the outputs of the filters are respectively supplied via delay devices and which supply the outputs to the adding means, respectively. The first feedback means has a transfer function of (1+a _i Z+
The ^second feedback means is composed of a cascade of secondary filters expressed as (1+b _i Z+
_It consists of ^a cascade _of ^secondary _{filters expressed as i} is a parameter that has a value included in [0, π] and controls the resonance characteristics of the filter, and when the order p of the filter is an even number, the transfer function of the first feedback means is Z{(a ₁ +Z) + _P/2-1 〓 ⁱ⁼¹ (a _i+1 +Z) _i 〓 ^j=1 (1+a _j Z+Z ² )− _P/2 〓 ^j=1 (1+a _j Z+Z ² )}, and the above second feedback _The ^{transfer function} _{of the means} ^is _{: _} ^_ 1+b _j Z+Z ² )}, and when the order p of the filter is an odd number, the transfer function of the first feedback means is Z{(a ₁ +Z)+ _(P-3)/2 〓 ⁱ⁼¹ (a _{i +1} +Z) _i 〓 ^j=1 (1+a _j Z+Z ² )−Z _(P-1)/2 〓 ^j=1 (1+a _j Z+Z ² )}, and the transfer function of the second feedback means is Z{ (b ₁ +Z) + _(P-1)/2 〓 ⁱ⁼¹ (b _i+1 +Z) _i 〓 ^j=1 (1+b _j Z+Z ² )}.