JPS63318635A - Data processor - Google Patents

Abstract

PURPOSE:To execute a data processing at high speed by a simple hardware, by providing a waiting field on an instruction, and also, providing an execution waiting control circuit and a flag on an executing means and a storing means in a pipeline processor element. CONSTITUTION:Pipeline processor elements 101, 102, 103 and 104 consist of an instruction fetching unit 122, an executing unit 123 and a storing unit 124 of the same constitution component, and the unit 123 is provided with AND gates 203, 207, etc., for executing a waiting control. Also, the unit 124 is provided with a flag 209 by which the elements 101-104 become ON, when a processing of an instruction is ended, and a control circuit 208. In this state, when a waiting field (w) in an instruction decoded by an execution waiting control circuit consisting of the gates 203 and 207, etc., provided on the unit 123 is OFF, the execution of an instruction is started immediately. Also, when the field (w) is ON when the flag 209 become ON, the execution of the instruction is started. In such a way, a data processing can be executed at high speed by a simple hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel data processing device, and particularly to a data processing device comprising a plurality of pipeline processors.

[Conventional technology]

Pipeline processing is an effective means for speeding up a computer, and is an important technique in particular for speeding up a single process. However, there is a limit to how much a single pipeline process can contribute to improving performance.

For this reason, low-level parallel computers aiming at parallel processing at the microprogram level are being researched. This is 1For example, the 13th Computer Architecture Society (19th
86) Pages 280 to 289 (3th Sym
posiumon Computer Architecture
ture, pp 280-289.1986).

[Problem that the invention seeks to solve]

Since the above-mentioned conventional technology performs parallel processing at the microprogram level, the creation of the microprogram is complicated.Since the above conventional technology performs parallel processing at the microprogram level, the parallelization rate does not become very high. Problems included the complexity of the hardware, the large number of macro instructions needed to perform detailed control, and the difficulty of developing an efficient compiler. .

An object of the present invention is to introduce a multiprocessor concept to speed up a single process, and to provide a high-speed data processing device that uses simple hardware and is mainly based on repetition.

[Means for solving problems]

The above object is achieved by configuring a data processing device with a plurality of pipeline processors that execute a single instruction stream, and providing each pipeline processor with an inter-processor queuing control mechanism.

[Effect]

Separate pipeline processor elements take and execute instructions from a single instruction stream. The data processing device includes a plurality of pipeline processor elements that operate in parallel, so that parallel processing is performed on a single instruction stream. If queuing control is required between processor elements, prepare an instruction that performs queuing, and when this instruction is executed, it monitors the status of other processors, waits for their operations to finish, and then executes the instruction in its own processor. By starting, you can easily perform waiting control,
Processing can be sped up with a simple mechanism.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 2 shows the overall configuration of a data processing device implementing the present invention. The processing device is a processor unit (PU)
10. Memory control unit (MCU)20. Main memory (MM) 30, I10 pu 0-1=4+ (I
OP) Signal line group 15, 25, 3 connecting 40 and :
It consists of 5 parts. Of course, there are other components other than those described above, but they are omitted because they are not necessary for understanding the present invention. The processor unit 10 takes in instructions and operand data stored in the main memory 30 via the memory control unit 20, and executes the instructions. I
10 processor 40 is a processor for input/output control. Since the present invention relates to the processor unit 10, this will be mainly explained below. Of course, since the I10 processor 40 is also a processor, the present invention can be applied to it.

FIG. 3 is a block diagram showing the internal configuration of the processor unit 10. The processor unit 10 includes a plurality of pipeline processor elements (PP#2, PP#3.P
P#4) 101, 102, 103゜104 (hereinafter simply referred to as processor element) and common resource management unit (CR
M) Consists of 105.

In this embodiment, four sets of processor elements are waited for, but this number is not limited to four, and the present invention is applicable to any number.

Each processor element 101 to 104 has a signal line group 11
It is connected to the common resource management unit 105 by 1, 112, 113, and 114, and can process microinstructions as a single unit. And as long as there is no resource contention,
It can operate independently from other processor elements.

FIG. 4 is a block diagram showing the configuration of the processor element 101. The other components have the same configuration and the instruction fetch unit (
IU) 121. Instruction decode unit (DU) 122.
Execution unit (EU) 123° Store unit (SU)
It consists of 124 pieces. Each of the above units operates independently to realize four-stage pipeline processing.

The instruction fetch unit 121 sends the address of the instruction via the signal line 134, and transfers the fetched instruction to the signal line 13.
Receive via 5. The decode unit 122 transfers the instruction fetched by the instruction fetch unit 121 to the signal line 12.
1 and sends the decoded result to the execution unit 123 via signal 5132. Execution unit l-12
3 executes the instruction upon receiving the decoding result, and sends the execution result to the store unit 124 via the signal line 133.

The store unit 124 stores the received execution results on the signal line 14.
0 to the common resource management unit 105. bus 1
30 is a path for transferring data between each unit. A signal line 136 is a signal line that sends operand addresses and register addresses to the common resource management unit 105.
Signal lines 138 and 139 are for receiving and receiving register read data, and signal line 137 is for receiving and receiving memory read operands.

FIG. 5 is a block diagram showing the internal configuration of the common resource management section 105. Instruction fetch selector (IFS) 15
1 receives the fetch request and instruction fetch address of each processor element via the signal line 134, and if the access is to a common memory block, it is combined into one memory access, and if the access is to a different memory block, the instruction fetch address is received. In order.

The access request and memory address are sent to the memory access controller 153 via the signal line 161.

An operand access selector (OAS) 152 receives the fetch request and its address of each processor element via the signal line 136, and if the access is to a common memory block, it is combined into one memory access, and if the fetch request is to a common memory block, it is combined into one memory access, In this case, access requests and memory addresses are sent to memory access controller 1 in the order of arrival.
53 via the signal line 162. A memory access controller (AM) 153 includes an instruction fetch selector 15
1 or converts the address received from the operand access selector 152 into a physical address and accesses the main memory 30 via the signal [165. Read buffer (
RB) 157 buffers the read data received from main memory 30 via signal line 166 and sends it to instruction distributor 154 in the case of instruction fetch data and to operand distributor 156 in the case of operand data. Instruction distributor (ID) 15
4 sends the command received from the read buffer 157 via the signal line 163 to the requested processor element via the signal line 135. operand distributor (
OD) 156 is the signal line 16 from the read buffer 157.
The operand data received via line 137 is sent to the requested processor element via signal line 137. There are 8 sets of register files (RF) 158 as read ports.

It has 12 boats in total, 4 groups serving as light ports.

For each processor element, two sets of read data are sent via signal lines 138 and 139, and write data is sent via signal line 14.
Receive via 0. The store buffer (SB) 159 is
It receives the write data received via the signal line 140 and the memory address received via the signal line 165, and writes it into the main memory 30 via the signal line 167tt.

FIG. 6 shows the instruction format of microinstructions (machine language) executed by each processor element. By setting all instructions to a fixed length of 32 bits, it is possible to detect the position of the next instruction without decoding the instruction.
An instruction format called ction Set Computer) is adopted. Regarding RISC, for example, IEE, Computer, September 1982 issue, page 11 (IEE, Computer,
ppH.

September, 1982).

In this instruction format, all instructions other than load, store, and branch instructions take register operands or immediate-eight operands.

FIG. 6(a) shows the instruction format when all operands are registers. Opcode (OP) field that indicates the type of operation, (W) field that instructs to perform a wait test, and (Rs) field that indicates the register number.
1, Rsz, Ri) fields.

FIG. 6(b) shows the format of instructions such as load, store, and branch instructions that require calculation of memory addresses. The R5, R- field specifies the register number and the Disp field gives the offset value. Note that in FIG. 6, the W field is provided independently from the OP field.

Of course, it is also possible to code and include the W field within the OP field.

Next, the operation of each processor element will be explained.

7 and 8 show the pipeline stage flow of the entire processor unit 10.

Of these, FIG. 7 shows a case where there is no vacant space in the pipeline for all processor elements.

Each processor element has decode, execute, and store units 122, 123, and 124 that process instructions at one machine cycle pitch. Each processor element sequentially executes four separate instructions in the instruction stream. For example, in the processor element 101, after instruction n, instruction n+4 is executed, and then instruction n+8 is executed in this order. Similarly, in the processor element 102, the instruction n+1 is followed by the instruction n+1.
5. Next, execute instruction n+9 in order. Instructions being executed in the same pipeline stage differ by only 1 (or 3) between adjacent processor elements, unless a branch instruction is issued. The instruction is processor element 1
01, instruction n+8, processor element 102 instruction n'+9, processor element 103 instruction n+
In the 10° processor element 104, the instruction is n+11.

FIG. 8 shows a pipeline stage flow when executing an instruction after waiting for the completion of execution of another instruction. In FIG. 8, instructions n, n+1. n+2. n+3. n+4
．． n+5. n+6. n+7 is an instruction that is executed regardless of the execution state of the previous instruction. In order to indicate that it can be executed regardless of the execution state of the preceding instruction, the W field of the instruction word is set to "0" (in other words, indicating that there is no waiting).On the other hand, instruction n+8 is executed without depending on the execution state of the preceding instruction. This is an instruction that is executed after waiting for the completion of the process.

This kind of waiting is necessary, for example, when an operation is performed using the execution result of a preceding instruction. The processor element 101 that executes instruction n+8 waits for all processor elements to finish executing the preceding instruction (that is, for all processor elements to finish executing the store unit 24) after completing instruction decoding in cycle t4. , starts execution in the execution unit 123 after completion. In this way, when waiting for the completion of execution of the preceding instruction, the W field of the instruction word is set to gg 1 ##.

Since the other processor elements 102 to 104 are synchronized with the processor element 101, the instructions n+9, n+10*n+11 following the instruction n+8
For the three instructions, the W field is set to "1" similarly to instruction n+8, and the resulting wait state is shown by dotted lines in FIG. 8, and in the t5 cycle, the execution units of all processor elements are in the wait state.

FIG. 1 shows an embodiment of a circuit, which is a feature of the present invention, for realizing the above-mentioned instruction waiting function.

In the figure, four sets of processor elements 101 to 10
4 (PP#1 to #4) have the same components, so to distinguish them, $ is added after the code indicating each unit.
n (n=1+2e3*4) is added.

The instruction fetch unit 122 includes an instruction decoder (ID#1) 201 . It has a latch (DR#1) 202 that latches the decoded result. The execution unit 123 includes an AND gate 203 for performing wait control,
204, 207. Orgate 206. Inverter 205
has. The store unit 124 includes a control circuit (SC#
1) 208 and a flag (ST#1) 2 indicating that the store unit is idle or will become idle in the next cycle
It has Q9. This flag 209 is set/reset by a signal line 229 from the control circuit 208.

In such a configuration, the W field is 110 ##
When the instruction decoder 201 decodes the instruction and sets the result in the latch 202, the signal line 211 that instructs the execution unit 123 that the instruction does not require wait control becomes aO''.

This causes the OR gate output to be # 1 $1, and the clock signal 223 passes through the AND gate 207 to the clock signal 22 to all latch gates of the execution unit 123.
Output as 4.

On the other hand, when the W field of the instruction is "1" and wait control is required, the signal line 211 becomes 111)l, and in this case, the output of the OR gate 203 is J only when the output 222 of the AND gate 203 is "1". "become. However, the store unit (SU) of each processor element 101 to 104
If any of #1 to #4) is in operation, each flag 20
9 (SI #1 to #4) is 0'', the AND gate 203 output also becomes 410 III, and the execution unit 123 enters the wait state.Then, all operations of all processor elements 101 to 104 are completed. When all the flags become “1”, the output 22 of the gate 203
2 becomes N 1 yt, a flock signal 224 is output, and the execution unit 123 performs execution processing.

〔Effect of the invention〕

According to the present invention, a data processing device can be configured by a plurality of pipeline processor elements configured by repeatedly using simple logic, and compared to a conventional data processing device configured by a single processor having complex logic, This has the effect of realizing faster performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of wait control of the device of the present invention, FIG. 2 is a block diagram showing the overall configuration of a data processing device to which the present invention is applied, and FIG. 4 and 5 are block diagrams showing the details of FIG. 3. FIG. 6 is a diagram showing the instruction format adopted in an embodiment of the present invention. 7 and 8 are stage flow diagrams illustrating the operation sequence of an embodiment of the present invention. 101.102, 103, 104... Pipeline processor element, 122... Instruction decode unit, 123... Execution unit, 124... Store unit, 203, 204, 205, 206, 207...
Gate, 2o9...flag.

Claims (1)

[Claims] 1. Processors with the same pipeline structure, each having as a pipeline stage an instruction decoding means, an execution means for executing the instruction decoded by the means, and a storage means for storing the processing result by the means in memory. In a data processing device that includes a plurality of elements and is configured such that a single stream of instructions is sequentially and cyclically processed by each of the processor elements, a waiting field is provided for the instructions, and the storage means in the processor element is provided with a waiting field. A processor element is provided with a flag that is turned on when processing of an instruction is completed, and an execution wait control circuit is provided in the execution means in the processor element, and the execution wait control circuit is configured to turn off the wait field of the decoded instruction. , the execution of the instruction is started immediately, and when the wait field of the decoded instruction is on, the execution of the instruction is started when the flags of all the storage means are turned on. What is claimed is: 1. A data processing device having a function of controlling execution means.