JPS63316220A - System for supplying clock - Google Patents

Abstract

PURPOSE:To obtain a highly accurate clock with a small quantity of the skew by supplying only an original oscillation waveform signal with a starting function to respective units, responding to the reception of the signal in respective units and forming a clock periodic to the original oscillation waveform signal. CONSTITUTION:When the power source of an electronic equipment is inputted, a resetting signal is generated, a transmission control circuit 202, a clock forming circuit 206, etc., in respective units 204 are reset, an original oscillator 201 starts an oscillation action and continuously generates an original oscillation waveform signal (f). Thereafter, when a starting signal ST is generated, an RS301 in the circuit 202 is set, and therefore, a DFF302 is set by the trailing edge of a signal fd immediately after it, a next step DFF303 is set by the leading edge of the signal fd immediately after it, and the transmission of an original oscillation waveform signal fst with a starting function is started. At the clock forming circuit 206 in respective units 204, a shifting action synchronized with the signal fst is started, and the clock synchronized with the signal fst is formed.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention relates to a clock supply system for electronic devices [Prior Art] Conventionally, in electronic devices having a plurality of units requiring clocks, As described in Japanese Patent Laid-open No. 72724 and Japanese Patent Application Laid-Open No. 59-23631, the original oscillation waveform signal and the start signal (
In this system, a lock is supplied to each unit (or synchronization signal), and each unit creates a lock as necessary based on the original oscillation waveform signal and the start signal (synchronization signal).

FIG. 5 is a block diagram showing an example of such a conventional clock supply system. In this figure, 101 is an original oscillator, 102 is a start signal generator, and 103 and 104 are buffer circuits, which are centrally arranged at one location within the electronic device. This is to supply the original oscillation waveform signal generated by the original oscillator 101 and the start signal generated by the start signal generator 102 to each unit 105 with the phase difference as small as possible.

The original oscillation waveform signal is sent to each unit 105 via the buffer circuit 103, and is also supplied to the start signal generator 102. The start signal generator 102 generates a start signal synchronized with the original oscillation waveform signal, and this signal is sent to each unit 105 through the buffer circuit 104.

In each unit 105, the clock generation distributor 10
A clock generator 107 in 6 generates necessary multiphase clocks from the original oscillation waveform signal and the start signal. This clock is distributed to each circuit block 1o9 in the unit via the buffer circuit 108 for each phase. Each circuit block 109 uses the buffer circuit 110 to receive and use one distributed clock.

[Problem that the invention seeks to solve]

In such a conventional clock supply system, if the original oscillation waveform signal and the start signal received by each unit 105 do not maintain the phase relationship between the original oscillation waveform signal and the start signal in the buffer circuits 103 and 104, In each unit 105, normality or occurrence of lock cannot be expected. In order to suppress this phase error within an allowable range, it is necessary to provide wiring of equal length and equal load for both signals. Also,
In order to reduce clock skew, it is necessary to wire the two signals with equal length and equal load for each unit.

However, it is extremely difficult to realize equal length and equal load wiring for two signals for each unit. In particular, when the frequency of the original oscillation waveform signal is high, the phase error between the original oscillation waveform signal and the start signal allowed at the entrance of each unit 105 and the clock skew conditions become even more severe. It is extremely difficult to realize equal length and equal load wiring for supplying signals.

The purpose of the present invention is to eliminate the above-mentioned conventional problems,
An object of the present invention is to provide a clock supply method that facilitates high-precision clock supply.

[Means for solving problems]

The above object is to provide an electronic device with a transmission control means for controlling the start of transmission of an original oscillation waveform signal to each unit in the electronic device in response to a start signal, and to provide the transmission control means in each unit. This is achieved by providing a clock generating means that is activated in response to the original oscillation waveform signal received from the means and generates a clock synchronized with the original oscillation waveform signal.

[For production]

The original oscillation waveform signal with a start function is supplied to each unit under the control of the transmission control means, and within each unit, the clock generation means is activated in response to reception of the original oscillation waveform signal.

A clock synchronized with the original oscillation waveform signal is created.

In this way, it is only necessary to supply the original oscillation waveform signal with the start function to each unit, and there is no need to supply other signals. This eliminates the problem of signal quantity and phase errors that existed in the past, and also Since the number of lines is reduced, it becomes easy to realize equal length and equal load wiring for each unit, and it is possible to supply a high precision clock with less skew.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 201 is a free-running original oscillator for generating the original oscillation waveform signal f, and is composed of, for example, a crystal oscillator or a PLL circuit. 202 is a transmission control circuit that controls the start of transmission of the original oscillation waveform signal f to each unit 204 in response to a start signal ST (its generator is not shown), and is provided with a start function as described above. ) iA oscillation waveform signal fst is output.

203 is a buffer circuit for the start function-added original oscillation waveform signal fst.

In each unit 205, 207 is a clock generation/distribution circuit, which is composed of a clock generation circuit 206 and a clock distribution buffer circuit 207. 208 is a functional block that requires a clock, and 209 is a buffer circuit for taking in the clock. The start function added original oscillation waveform signal fst is received by the clock generation circuit 206. The 8-phase clock created by the clock creation circuit 206 is distributed to each functional block 208 via the buffer circuit 207 for each phase, and each functional block 208 receives the clock via the buffer circuit 209 and uses it internally. do.

FIG. 2 is a circuit diagram showing an example of the transmission control circuit 202. 301 is an RS flip-flop, 302 and 303
304 is an inverter, 305 is an AND gate, and 306 is a frequency divider.

The start signal ST is the S(
set) terminal, and the original oscillation waveform signal f is applied to one input terminal of the AND gate 305 and input to the 1 frequency divider 306.

A signal fd obtained by dividing the frequency of the original oscillation waveform signal f by two by this frequency divider 306 is input to the CK (clock terminal) of the D flip-flop 303, and after being inverted by the inverter 304, it is input to the GK terminal of the D flip-flop 302. is input. Each flip-flop 301, 302, 303
A reset signal generated when the device is powered on is applied to the R (reset) terminal of the device. RS flip flop 3
The output of 01 is D (data) of the D flip-flop 302.
The output of this D flip-flop 302 is input to the D terminal of the D flip-flop 303. D
The output of flip-flop 303 is input to the other input terminal of AND gate 305.

The start function-added original oscillation waveform signal fst is output from the AND gate 305.

FIG. 3 is a circuit diagram showing an example of the clock generation circuit 206. e401 is a delay element, 402 is an edge trigger type D flip-flop, and 403 is a serial input/parallel output shift register.

The start function-added original oscillation waveform signal fst received from the transmission control circuit 202 is directly input to the D terminal of the D flip-flop 402 and the CK terminal of the shift register 403, and is also input to the D flip-flop 402 via the delay element 401. It is input to the CK terminal. The output of the D flip-flop 402 is input to the SI (serial input) terminal of the shift register 403. Among the outputs T0 to T of the shift register 403, the second bit output T1 is input to the R terminal of the D flip-flop 402. In addition, the reset signal generated when the device power is turned on is transmitted to the shift register 40.
It is input to the CL/R (clear) terminal of No.3.

FIG. 4 is a signal timing diagram of each part.

The clock supply operation will be explained below. When the electronic device is powered on, the reset signal is generated to reset the transmission control circuit 202, the clock generation circuit 206 in each unit 204, etc., and also reset the original oscillator 201.
starts the oscillation operation and continuously generates the original oscillation waveform signal f.

After that, when the start signal ST is generated, the RS flip-flop 301 in the transmission control circuit 202 is set, so the D flip-flop 302 is set at the falling edge of the signal fd immediately after that, and the next one is set at the rising edge of the signal fd immediately after that. The D flip-flop 303 of the stage is set, and the transmission of the start function-added original oscillation waveform signal fst is thus started.

The timing of generation of the start signal ST and start of transmission of the start function-added original oscillation waveform signal fst is as shown in FIG.

This start function added source oscillation waveform signal fst is as follows.

It is transmitted to each unit 204 via the buffer circuit 203.

When the clock generation circuit 206 in each unit 204 receives the start function-added Jfi oscillation waveform signal fst, the D flip-flop 4 is clocked at the first rising edge of the Jfi oscillation waveform signal fst.
02 is set, the shift register 403 starts a shift operation in synchronization with the start function-added source oscillation waveform signal fst, and generates eight-phase clocks (T0 to T7) at the timing shown in FIG. . shift register 4
The output T1 of the second bit of 03 is connected to the D flip-flop 40.
2, the pulse width of each phase clock is equal to two periods of the signal fst, as shown in FIG.

The clocks of each phase are distributed to each functional block 208 via a buffer circuit 207, and taken into each functional block 208 via a buffer circuit 209 for use.

In this way, since the start function-added source oscillation waveform signal fst is only transmitted to each unit 204, the problem of phase error between signals that occurs when two types of signals are supplied to each unit as in the conventional case is eliminated. Essentially not occurring.

In addition, the wiring for propagation of the i signal between the buffer circuit 203 and each unit 204 is required to have equal length and equal load in order to minimize clock skew;
Since only one signal line to 04 is required, it is much easier to realize wiring that satisfies such conditions than in the conventional system using two types of signal lines.

Note that in the clock generation circuit 206, the outputs of other bits of the shift register 403 are transferred to the D flip-flop 40.
By feeding back to the R terminal of No. 2, the pulse width of the clock can be changed, and by increasing or decreasing the stages of the shift register 403, the number of clock phases can be increased or decreased.

It is also possible to configure the logical product signal of the outputs T0 to T7 of the shift register 403 and the start function-added original oscillation waveform signal fst to be used as a clock, and in this case, the pulse width of the original oscillation waveform signal f is changed. This makes the clock pulse width variable.

In the clock generation circuit 206, the shift register 40
Two shift registers corresponding to 3 are provided, one shift register is operated at the rising edge of the start function added original oscillation waveform signal fst, the other shift register is operated at the falling edge, and the corresponding pitches of both shift registers are operated at the falling edge. A configuration may be adopted in which the OR signal of the outputs of i~ is used as the clock. Even with such a configuration, the pulse width of the clock can be varied by changing the pulse width of the original oscillation waveform signal f.

In addition, in the transmission control circuit 202, the RS flip-flop 301 is omitted, and the start signal ST is changed to a level signal and inputted directly to the D terminal of the D flip-flop 302. It is also possible to start and stop transmission of the oscillation waveform signal fst. In this case, it is possible to operate or stop the shift register 403 in the clock generation circuit 206 by turning the start signal ST on or off.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, clocks can be supplied to each unit by simply supplying each unit with the original oscillation waveform signal to which the start function has been added. This eliminates the problem of signal quantity and phase errors that occur in conventional methods of supplying signals, and since the number of signals for each unit is halved, it is easy to realize equal-length, equal-load wiring to reduce clock skew. It becomes possible to easily supply high-precision clocks to multiple units such as

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of a transmission control circuit, FIG. 3 is a circuit diagram showing an example of a clock generation circuit, and FIG. 4 is a timing chart of signals related to clock supply. FIG. 5 is a block diagram showing a conventional clock supply system. 201... Original oscillator, 202... Transmission control circuit,
204...Unit, 206...Clock generation circuit. +-,te-. Fig. 2 ↑ Fig. 3 Fig. 4 "" ゛75,11

Claims (1)

[Claims] (1) In an electronic device having a plurality of units that require a clock, if a transmission control means is provided to control the start of transmission of the original oscillation waveform signal to each unit in the electronic device in response to a start signal. A clock supply system characterized in that each unit is provided with a clock generation means that is activated in response to the original oscillation waveform signal received from the transmission control means and creates a clock synchronized with the original oscillation waveform signal.