JPS63316121A - Track emulation system - Google Patents

Abstract

PURPOSE:To maintain compatibility by emulating an emulation targeted track format, by performing track emulation at every sub track separately in a DASD sub system with a variable length format. CONSTITUTION:(m) sub tracks ST are formed by dividing the physical tracks PT0 and PT1, etc., of a DASD equally into (m) parts by an index mark (indexj, j=1-m-1). Next, a simulation targeted track can be formed by detecting the index mark indicating each sub track boundary and collecting (n) sub tracks ST. In such a way, it is possible to maintain the compatibility by emulating the track format of another DASD when the physical track capacity of the DASD is the capacity of m/n times the emulation targeted track of another DASD with which the compatibility is desired to be taken.

Description

[Detailed Description of the Invention] [Summary] When the DASD track capacity is m,/n (an integer where m > n) times the emulation target track, the physical track of the DASD is divided into m equal parts by index marks, and m A track to be simulated is constructed by collecting n sub-tracks created by equally dividing the track.

As a result, it is possible to maintain compatibility by emulating the emulation target track format by utilizing all of the DASD capacity without wasting it.

[Industrial application field]

The present invention provides a method for emulating a DASD track formatter with a smaller track capacity using a D'ASD with a larger track capacity in a variable-length DASD subsystem, in particular, a DASD
- Rack capacity with other DAS to maintain compatibility
m/n of D (m, n are positive integers, and m > n)
The present invention relates to a track emulation method for emulating m emulation target tracks with n physical tracks when the number of tracks is multiplied by n.

[Conventional technology]

DASD (direct a) of magnetic disks, etc.
The capacity of direct access storage devices (direct access storage devices) has been increasingly expanded in recent years.

The capacity of the DASD is expanded by increasing the number of cylinders, the number of heads, and/or the physical track capacity.

Among these methods, the method of increasing the physical track capacity is advantageous because, due to recent advances in high-density recording technology, the capacity of the DASD can be expanded more easily than in the past without increasing the size of the DASD.

However, when the physical track capacity of a DASD is increased, software compatibility with conventional models having different physical track capacities becomes a problem.

Conventionally, in order to maintain software compatibility between new DASDs with increased physical track capacity and conventional DASD models, track emulation has been performed in the following manner.

+a+ Divide one physical track of the new DASD into two (
(generally divided into N) and has two logical tracks as in the prior art.

This method is used when the capacity of one physical track of the new DASD is twice the capacity ff1 of the emulation target track (in the case of N division, the capacity is N times), and the expanded capacity of the new DASD is effectively used. You can use it to perform track emulation.

('b) A method in which only the capacity of the emulation target track is used on one physical track of the new DASD.

This method maintains compatibility whenever the new DASD's single physical track capacity is larger than the track capacity of the DASD being made compatible, but the remaining physical track capacity after emulation is not used. become.

[Problem that the invention seeks to solve]

Conventional track emulation methods include the above-mentioned (a
) and fblO methods.

However, (AlO method has the advantage of being able to perform track emulation by effectively utilizing the expanded capacity of a new DASD, the physical track capacity is twice that of the DASD being emulated (generally There was a constraint that it could only be realized if the capacity was an integer multiple).

On the other hand, method (b) has the advantage of not being subject to such restrictions, but on the other hand, it has the disadvantage that the surplus portion of the physical track is discarded and the expanded capacity of the new DASD is not used effectively. Ta.

Furthermore, in either method, if the physical track capacity of the DASD is m/n (m, n are positive integers, and man) times the track capacity of the emulated DASD, There is a problem in that emulation cannot be effectively utilized and an increase in the physical track capacity of the DASD does not lead to an increase in the DASD capacity.

The present invention makes full use of the expanded capacity of a DASD, and when the physical track capacity of a DASD is m/n times that of the emulated tracks of another DASD with which compatibility is to be maintained, An object of the present invention is to provide a track emulation method that emulates m emulation target tracks of other DASDs using physical tracks of the present invention.

[Means for solving problems]

The solution taken by the present invention will be explained with reference to the principle diagram of the present invention shown in FIG.

In FIG. 1, P +6 − P T + ,...
・,PT,,lkan),...are variable length format DASD
each physical track.

Each physical track is divided into m equal parts, and each physical track is divided into m sub-tracks (ST). In the figure, LTH-7 (j=o to n-1) indicates each sub-track of the logical track LTH (i=o to m-1).

Each physical track PTo to P T , -, etc. is m/n times the emulation target track capacity of the compatible DASD. Therefore, now the capacity of each physical track P T 6 ”” P T (n-11, etc.) is
A. Assuming that the emulation target track capacity is C5 and the capacity of each sub-track ST is C8, the following equation holds true.

C,=C,Xm CP = CHX - Than this, GE = Cp x - = C, s xn becomes.

That is, since n sub-tracks ST provide a compatible target and a DASD emulation target track capacity C8, the track format can be emulated. In general, it is possible to emulate m emulation target tracks of a compatible DASD using n physical track capacity.

In FIG. 1, LTt-0 to LT=-+-++:
(i=0 to m-1) each indicate m logical tracks that are emulated.

In the following description, when referring to sub-tracks of each logical track LT, sub-tracks t, 'r, -
o or LTi-+, and when referring to sub-tracks in general regardless of each logical track LT, they are indicated as sub-tracks ST.

[Operation] Each physical track, PT, , PT, etc. of the DASD is marked with an index mark (index j , j = 1, 2
9...9m~1) Divide m into m sub-tracks ST
form.

Index mark 1n indicating each sub-track boundary
By detecting dex-j (j-1s 2 , =) and collecting n sub-tracks ST, an emulation target track is constructed.

In this way, by performing track emulation on sub-tracks, the overhead required for track emulation can be kept low.

In Fig. 1, LT, -0~LT, -, □-I, :(
i=0''m-1) indicates m tracks that are each emulated.

As shown in FIG. 1, each logical track LTi includes one on the same physical track and one spanning two physical tracks. For example, logical track L T
O-0~L To-(+1-11 exists on one physical track PT, but on the logical track LT, -0~L
T, -0-3) are two separation tracks PT and PT
, exists above.

When performing track emulation, a control device (not shown) sequentially accesses n sub-tracks forming each logical track LT to perform emulation processing.

If n sub-tracks of logical track LT□ are
When the sub-tracks span two separate tracks such as T, -0 to L Ti-tn-n , each sub-track is accessed by switching the physical track.

When the access is performed beyond the sub-track, the control device temporarily suspends the access operation and restarts it after switching the sub-track. At this time, n sub-tracks may span two or more physical tracks, but
In that case, switching is also performed (detailed emulation operation will be explained in the embodiment section).

As described above, when the physical track capacity of a DASD is m/n times the emulation target track of another DASD with which you want to make compatibility, you can emulate m tracks of another DASD using n physical tracks. Target tracks can be emulated to maintain compatibility.

As a result, during track emulation, the overhead required for emulation can be kept low, the entire capacity of the DASD can be used without waste, and an increase in track capacity can be directly linked to an increase in DASD capacity.

〔Example〕

Embodiments of the present invention will be described with reference to FIGS. 2 to 6. Figure 2 shows the tiger to be emulated.

3 is an explanatory diagram of the logical track configuration method in one embodiment of the present invention, FIG. 4 is an explanatory diagram of the sub-track format of the embodiment, and FIG. 5 is an illustration of the implementation system of the embodiment. The explanatory diagram, FIG. 6, is an explanatory diagram of an operation flowchart of the implementation system.

An embodiment of the present invention will be described below, taking as an example a case where the physical track capacity of the DASD is 3/2 times that of the emulation target track, that is, m-3, n=2.

(A) Track format to be emulated FIG. 2 shows an example of a standard track format of a DASD to be emulated.

In FIG. 2(A), 1ndex-0 is an index mark indicating the physical boundary of the track, and all tracks start and end at 1ndex-0.
Its track length TC is 49.728 bytes.

Each track has the same format, including a home address (HA), a record RO, and each record RN (N
=1,2,...), all of which have gaps Gl, G20, G2 . G3 and G
Separated by 4.

The record RO is composed of a count area and a data area, and the record RN (N=1, 2, . . . ) is composed of a count area, a key area, and a data area.

Gap G1 is between 1ndex-0 and home address HA
The gap between the two is 504 bytes.

Gap G20 is home address HA and record RO
The gap between the two is 248 bytes. G2 is a 224-byte gap that separates the count area, key area, and data area in each record.

Gap G3 is for each record RN except record RO.
A gap provided before (N-1, 2,...),
It is 216 bytes (see the table in FIG. 2(C) for the number of bytes in each of these areas).

The home address HA and each count area are shown in Figure 2 (B
), the total length is 40 bytes, and the contents of the HA are written during manufacturing.

SC (skip control) indicates the distance to the defective portion on the track in units of segments (one segment is 32 bytes). Defects are recorded in 2 bytes (2 bytes) each indicating the location of up to 7 defective parts per track.
(14 bytes in total) (SCO to 5C6).

S N (segment number) indicates a segment number that is one less than the home address HA and the segment number at the beginning of each count area. PA (phys
ical address) indicates the physical address of the track. F (flag) indicates various states of the track. CC/HH/R indicates the home address HA and the logical address to which each count area belongs, and is indicated by the cylinder number CC, head number HH, and record number R. K L (key l
length) indicates the key length of the record in bytes. However, in terms of -C, there is no key in record RO.

D L (data length) indicates the data length of the record in units of hides. However, the home address HA has no data, and the record RO is generally defined as 8 hides.

E CC (error correction code)
e) Detects and corrects errors for each area.

Record RO is the first record following the home address HA, and has the aforementioned count area and data area, and is used to designate a replacement track when this track is a defective track.

In record RN (N=1, 2,...),
The count field has the format and content described above and is used by the control device. The key area is used as a physical index when searching for records. The data area contains data information defined in the count area and key area, and is written and used by the programmer.

If there is a defective part in a track, the data is moved (m) in units of 3 segments (96 bytes) across the defective part.
over) or split.

Up to 7 defective parts are allowed in one track, so
The area corresponding to the maximum of 7 defective parts (96x7=
672 bytes) are provided as a remainder at the end of the track. Gap G4 has 96 bytes that correspond to this defect area, so the remaining size is 04X7
(-672 bytes).

As mentioned above, the standard track formant consists of the area (AC) of the home address HA, record RO, record RN (N=1.2...) sandwiched between gaps G1 and G20, and the remainder. configured.

Here, G1=504 bytes, HA=40 bytes, G2
0 = 248 bytes, record RO = 296 bytes, AC
(Record RN) = 47968 bytes, remainder (G4x
7) = 672 bytes, so track length TC = 49
．． This is 728 bytes (see the table in FIG. 2(C)). Note that in FIG. 2, AC and DC are values for a standard record with KL=O1DL=8 as the record RO. Further, DC is the maximum data length in the data area of record R1.

Compatibility with this track format requires that not only the track capacity be the same, but also the length of each gap and field within the record. Therefore, when emulating this track format, it is necessary to transfer these items to a new track without contradiction.

(B) Method of configuring logical tracks A method of configuring logical tracks when the capacity of the physical track to be simulated is 3/2 times the capacity of the track to be simulated will be explained with reference to FIG.

In FIG. 3, PTo, p'r, pTz indicate each physical track, and are defined by 1ndex-0 on the left and right.

In this example, since m=3.2-2, each physical track has 1ndex-0, 1nd
It is divided into three equal parts by ex-1 and 1ndex-2, forming three sub-tracks. In the figure, LT, -0 and LTH-+ (i = 0, 1, 2, . . . ) are each track of the logical track LT.

Since the capacity of these two sub-tracks is equal to the capacity of the emulation target track, emulation can be performed using two sub-tracks.

In this embodiment, the logical track LT is two consecutive sub-tracks LT; -o and LTi-.

Consists of. For example, the logical track L To is L
Consists of To-0 and LTo-+, logical track LT,
is composed of LT, -0 and LTi-.

In this case, logical track LT0. In LT4 etc.,
Consecutive sub-tracks span two physical tracks. However, even in such a case, since physical track switching can be performed within the gap Gl, continuity of processing is guaranteed and no problem occurs.

Next, specific contents of the logical track and each sub-track will be explained with reference to FIG. As aforementioned,
In emulation, it is necessary to make the track format look exactly the same as the track formant to be emulated in FIG. 2, so in this embodiment, the sub-track format is configured under the following prerequisites.

■ The net capacity of the two sub-tracks is
Equal to the capacity of the track to be emulated.

(2) In order to verify the validity of each sub-track f111, a home address HA is provided at the beginning of each sub-track.

(2) Since only one record RO is required, it is provided on the first sub-track (LT, -0) side.

(2) Since the number of defective parts allowed in one track is seven, it is assumed that the number of defective parts allowed in one subtrack is three. Therefore, G4x3 (=288 hides) is added to each sub-track as the remainder.

■Other formats are the same as before. However, since there are three defective locations on each sub-track, the number of SCs for the home address HA may be three, SCO, SCI, and SC2, as will be explained in FIG. 4(B) below.

FIG. 4(A) shows the logical track LT configured in this way and its sub-tracks LT, -0 and LT, -.
FIG. 2B shows the format of the home address HA and count area.

In FIGS. 4(A) and (B), gaps Gl, G
20.2, G3, G4, home address HA, record RO, record RN (N=1゜2,...), each count area, key area (not shown), data area, home address HA, and each count Area SC (SCO-S
C2), SN.

PA, F, CC, HH, R, KL, DL
, FCC, etc. and their number of bytes are the same as in FIG. 2, except for TC, AC, and DC.

However, record RN is LT, -0 part (record R
N(0)) and LTi-, part (record RN(1))
It is divided into two parts.

Note that since the allowable number of defective locations for each sub-track is three, the home address HA and SC of each count area are SCO, SCI, and SC, as shown in FIG. 4(B).
There are 2 and 3 pieces.

Therefore, the length of the home address HA is SC3~S
Although 32 bytes are reduced by 8 bytes of C6, that amount is incorporated into G1.

Also, record RN of both sub-tracks (N=1).

2,...), the length of AC remains unchanged at 47.968 bytes.

From this, the length of the logical track LT can be found as follows.

Logical track length = (G1+HA+record RO+G4X
3)+ (G1+ HA+G2+GX3)+AC The first term is the record RN in subtrack LT, -0 (
The second term is the sum of each area excluding record RN (11) in sub-track LT, -. Also, AC=record RN (N=1, 2
,...) = (Record RN (0)) + (Record RN
(11).

When calculating the logical track length from the above formula, the first term is 13
76 bytes, the second term is 1056 bytes, and the third term AC is 47,968 bytes, resulting in a total of 50,400 bytes.

In other words, the conventional 4 sub-tracks shown in FIG.
If we try to emulate a track of 9,728 bytes, the total length will be 50,400 bytes, with 25°200 bytes per subtrack. However, the track must be divided into segments of 32° hide, and in order to make it an integral multiple of 32, each subtrack length (S
TC) is chosen to be 25,216 bytes.

From this, each physical track PT,,PT,.

Strictly speaking, the length of PT, etc. is 25,216X3-75,
It is 648 bytes. This value is 3/2 times (=74 bytes) the emulation target track length (49,728 bytes).
．． 592 bytes), but this degree of difference is within the range of overhead that occurs in actual emulation processing, so there is no practical problem.

Also, sub track LT, -0 is sub track link LT.
, -1, but by averaging within the subtracks, each subtrack LTH-o and LT4-, (i=O,l,2...
) have the same subtrack length STC (=25,
216 bytes). In other words, each subtrack length includes the overhead required to configure a logical track, which is distributed to each subtrack. Therefore, although the net length of each subtrack (a value obtained by subtracting the overhead) is different, the physical lengths of the subtracks can be made equal.

(C) Configuration of implementation system The configuration of the implementation system of the track emulation method will be explained with reference to FIG.

In FIG. 5, lla, llb, llc, etc. are DAS
This is a magnetic disk device used as D.

12 is a magnetic disk control adapter (ADP), and 13 is a control device.

The control device I3 receives commands from the channel of the host device and performs read/write operations.The control device I3 sends each command necessary for processing to position a node (not shown) on a predetermined track or rack. It controls the transfer of data to be read/written.

In accordance with each command from the control device 13, the ADP 12 performs various controls such as selection control of a predetermined magnetic disk device, head positioning control, read/write control, etc. in the selected magnetic disk device.

In the control device 13, a channel interface section 131 performs interface control between the channel of the host device and the control device 13.

Reference numeral 132 denotes a data transfer unit 1, which controls read/write data transfer and includes a buffer (not shown).

133 is a device interface section, which is connected to ADP12. Controls the interface between II devices 13.

Reference numeral 134 denotes a control microprocessor (control MPU) that controls the operations of each section and the entire control device 13.

135 is a control microcode section, which is a control MPU 13
4 is stored in a memory (not shown).

The hardware configurations of these control device 13, ADP 12, each magnetic disk device 11a, llb, etc. are common to the conventional system.

(D) Operation of the Embodiment The emulation operation of the embodiment will be explained according to its processing steps with reference to the operation flowchart of FIG. 6.

(2) Step Sl, 52 The home address HA read from one sub-track ST on the physical track of the 6R disk device (referred to as Ila) is transferred to the control device 13 via ADPI2.

The control MPU 134 of the control device 13 checks the skip control (SC byte) of the home address HA (step S), its SCO, SCI, and SC2 (
The presence or absence of a defect in the sub-track ST is determined from the contents of (see FIG. 4(B)) (STE knob SZ).

Note that the processing of each step below is all performed under the control of the control MPU 134 and the control 1111 microcode section 135, unless otherwise specified.

■ Step S: +, Ss If there is no defect in the remaining area of the sub-track, only the index mark remains in the remaining area of the sub-track, so check whether the processing field crosses the sub-track boundary, that is, the inte nox mark. Judgment is made from the HA information (step si).

When the sub-track boundary is not reached, read/write processing is possible, so read/write processing is performed until the end of the processing field, and field read/write processing is completed (step S). In addition, the magnetic disk device 2
The read/write process to 1a is performed by channel, control device 1.
3. Performed by ADP 12 in the same manner as before.

■ Step Sz, Sa, Ss Step S2
If there is a defect in the remaining area of the sub-track,
It is determined from the SC information whether the processing field applies to the defect (step S4). If there is no defect, please apply
Since write processing is possible, read/write processing is performed until the end of the processing field in the same manner as in the above-mentioned ①, and the field read/write processing is completed (step S).
.

■ Step S6, S? -Ss If the processing field is applied to a defect in step S4, the processing field is either the count area or the short key area (short K
) or a short data area (short D) (step S6).

The length of the short key area and short data area is shorter than 20 bytes, that is, when it is contained in one segment (32 bytes), and the length of the counter high area is 40 bytes as shown above. .

If it is neither the processing field count tilt, short key area, nor short data area, read/write processing is performed (ECC is not added) with the processing field length up to the defective part, and then the process returns to the above-mentioned step S ( Step S?). In this case, data will be split.

If the processing field is one of the count area, short key area, or short data area, the processing field is shifted from the defective area by 3 segments, that is, 96 heights, and then the process returns to step S1 described above (step SS). In this case, data movement (move) will be performed.

■ Step S2 t S3 s Sq t S
l++ s11 If there is no defect in the remaining area of the sub-track in step S2, read/write processing is possible, but in step S3 it is determined whether the processing field overlaps the sub-track boundary.

If the processing field falls on a sub-track boundary, it is further determined whether the processing field is a count area, a short key area, or a short data area (step S9).

If it is in one of these areas, an inte-nox mark is detected in order to perform read/write on the next sub-track (step S, 1).

If the processing field is not in each of the above areas, the field length is up to the subtrack boundary, and the area between them is
After performing the write process (step S, .), index marks are detected (step S1). Note that in this case, since reading/writing of fields in one sub-track is completed for the time being, ECC addition processing is performed.

■ Step S, t, SI3. S14 Index mark detection is performed by the magnetic disk device 11a, and when an index mark is detected, A
The control device 13 is notified via the DP 12.

The control MPU 134 detects that the detected index is 1n.
It is determined whether it is dex-0, that is, an index mark indicating a physical track boundary (see FIG. 3) (step Sl□).

If it is not 1ndex-0, the next sub-track exists on the same physical track, so the next sub-track is entered without switching the physical track, and the physical track address and sub-track address are set to the predetermined one by the home address HA. It is confirmed that it is the same (step 514). When the validity of the sub-track is confirmed, the process returns to step Sl, repeats the above-mentioned processes, and resumes processing of the remaining or unprocessed fields on a new sub-track.

If 1ndex-0 is detected in step SI2, that physical track ends, so a physical track switching process is performed. In this case, the physical track processing can be switched by the control MPU 13 without going through the host device.
:b1] is performed as an internal operation of the control device 13 by a command issued internally by the controller 4.

When the physical track switching is completed, the validity of the physical track address and sub-track address is confirmed from the home address HA of the next physical track (step S
,,), returns to step S1, repeats the above-mentioned processes, and resumes processing of the remaining or unprocessed fields on a new sub-track.

As described above, the emulation target track format shown in FIG. 4 is read/written in units of sub-tracks. If the emulation target track spans two physical tracks, the physical track will be switched midway through, and the contents of the first half subtrack will be transferred to the first physical track, and the contents of the second subtrack will be transferred to the next physical track. Read/write processing is performed.

At this time, as described above, the processing that spans two or more sub-tracks and the physical track switching processing when the physical tracks of the sub-tracks of the emulation target track are different are both performed by the internal operation of the control device 13, so that the track emulation Processing can be performed efficiently.

Although one embodiment of the present invention has been described above, the embodiment of the present invention is not limited to this embodiment. It can be carried out.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(b) m of the emulation target track of another DASD with which the physical track capacity of the DASD is to be compatible
/n times, other DASD track formats can be emulated to maintain compatibility.

(") During track emulation, the overhead required for emulation is kept low, the full capacity of the DASD is used without waste, and the increase in track capacity can be directly transferred to the DA.
This can lead to an increase in SD capacity.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention. FIG. 2 is an explanatory diagram of the track format to be emulated. FIG. 3 is an explanatory diagram of the logical track configuration method in an embodiment of the present invention. FIG. 5 is an explanatory diagram of a track format, FIG. 5 is an explanatory diagram of an implementation system of the same embodiment, and FIG. 6 is an explanatory diagram of an operation flowchart of the same embodiment. In FIG. 5, 113-llc...magnetic disk device, 12...magnetic disk control adapter (ADP), 13...control device, 134...control microprocessor (control MPU). 7---LTo LT+→,! - Fragment of Kōro, Figure 1 of the figure of the sails % = hya 4 rows of Mikata Yasisdem Figure 5

Claims (4)

[Claims] (1) In a variable-length direct access storage subsystem, the track capacity is m/n of the track capacity of another direct access storage device (m, n are positive integers, and m>
n) a track emulation method that emulates the track format of another direct access storage device by a track of a direct access storage device that is twice the number of tracks of the direct access storage device, the method comprising: (a) each physical track (PT_
i:_i=0, 1, 2, . . . ) as index marks indicating subtrack boundaries (index-j: j=1,
2, ..., m-1) to form m sub-tracks (ST), (b) detecting index marks (index-j) indicating the boundaries of each sub-track; Truck (ST)
A track emulation method characterized in that a track to be emulated is constructed by collecting n pieces. (2) Home address (HA) at the beginning of each sub-track that indicates the physical location of the track, track status, etc.
A track emulation system according to claim 1, characterized in that the track emulation system is provided with:. (3) Processing spanning two or more sub-tracks is performed by internal operation of a control device (13) that performs track emulation processing without intervention from a host device. Track emulation method described in Section 2. (4) The track according to claim 3, characterized in that when the physical tracks of sub-tracks forming the emulation target track format are different, physical track switching is also performed by an internal operation of the control device (13). Emulation method.