JPS63314872A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the surface uniformity and reproducibility of a semiconductor element formed in a region for forming the element except a FET by covering the region with an insulating film and the like, and avoiding the influence of a plasma damage at the time of dry etching. CONSTITUTION:An S.I.GaAs substrate 1 is covered with an ion implanting mask 2, selectively ion implanted to form an n-type resistance implanted region 4, and an n-type channel layer 7 is similarly formed. The substrate 1 is covered with a heat treated protective film 8, implanted impurity is activated, and the film 8 is removed. The film 8 remains on the region 4 at this time. After a high melting point Schottky gate material 10 and an SiO2 layer 11 are formed on the substrate 1, the layer 11 is dry etched, and with the layer 11 as a mask the layer 10 is formed in a gate size by dry etching using a plasma. As a result, a Schottky gate 16 is formed, the region 4 is covered with a damage protective film 9. Thus, it is not plasma damaged. Thus, with the mask 15 and a gate 16 as masks regions 17-19 and electrodes 21 of a FET are formed.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a semiconductor integrated circuit in which an element other than a field effect transistor (hereinafter referred to as FET) is formed by implanting an impurity into a second region and/or a surrounding region thereof. By covering the semiconductor element with a protective film such as an insulating film and avoiding the influence of plasma damage during dry etching using plasma for FET gate processing, the in-plane uniformity of the semiconductor element formed in the second region can be improved. and improve reproducibility.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a semiconductor element other than a Schottky gate FET that is formed by selectively introducing impurities onto a semiconductor substrate.

[Conventional technology]

In recent years, in order to overcome the limits based on the physical properties of silicon, semiconductor devices using compound semiconductors such as gallium arsenide, which have higher electron mobility, have been developed, and their integration into integrated circuits is progressing. There is a demand for improvements in the uniformity and reproducibility of resistance values of semiconductor devices such as resistance elements. As shown in Figure 4,
In the case of compound semiconductors such as gallium arsenide, as in the case of silicon, it is usually done through a process of selectively introducing impurities into the active region of the device by ion implantation, and a heat treatment process to electrically activate the impurities. A FET element 6, a resistance element 13 and a diode element 1 are arranged on a single crystal substrate 1.
4 etc. are formed to constitute an integrated circuit.

A conventional technique for manufacturing a Schottky gate type FET is disclosed in Japanese Patent Laid-Open No. 57-113289, and FIG. 5 shows the manufacturing process. FIG. 5 will be explained below.

(1) As shown in FIG. 5(a), an ion implantation mask 2 is placed on the surface of a semi-insulating gallium substrate (hereinafter referred to as Sj, GaAs substrate) 1, and a window is opened in the area where the channel layer will be formed. Next, Si4 ions are implanted to form an n-type channel layer 7.

(2) As shown in FIG. 5(b), the ion implantation mask 2
, and the S, 1. The surface of the GaAs substrate 1 is newly coated with a heat treatment protective film 8 such as SiO□, and then heat treatment is performed to electrically activate the implanted Si.

(3) As shown in FIG. 5(c), after removing the heat treatment protective film 8, the S.1. For example, Wl, on the surface of the GaAs substrate 1. High melting point gate material layer 1 such as S i, .
0, then a 5-int layer 11 for gate electrode processing is formed.

After covering the gate forming portion with a photoresist 12, a 5iOz layer 1 is formed by dry etching using plasma.
1 into a Schottky gate shape.

(4) Subsequently, as shown in FIG. 5(d), using the 5iCh layer 11 as a mask, the high melting point gate material layer 10 is dry etched into a Schottky gate shape using plasma.

(5) By performing dry etching in this way, Si0
When the second layer 11 is removed, a Schottky gate 16 is formed, as shown in FIG. 5(e).

(6) Next, as shown in FIG. 5(f), using the Schottky gate 16, photoresist, 5in2, etc. as a mask, Si ions are selectively implanted to form the n-type source region 17 and drain region 18. form.

(7) As shown in FIG. 5(g), as in the step of FIG. 5(b), an n-type source region 17 and a drain region 18 are formed.
Activate the impurities injected into the

(8) As shown in FIG. 5(h), after removing the heat treatment protective film 20, AuGe/Au etc. are used for the n-type source region 17 and drain region 18, and the ohmic electrode 2
form 1.

Through the above process, Schottky gate type FET
can be formed.

[Problem that the invention seeks to solve]

The gate electrode of the Schottky gate type FE'r uses a high melting point metal material such as W Si as described in the explanation of FIG. 5 above. In order to electrically activate the implanted impurity ions as shown in FIG. 5(b), S, 1. Ga
After covering the surface of the As-based Fi1 with a heat-treated protective film 8,
This is because when heat treatment is performed for 850° CIO minutes, if a Schottky gate material with a low melting point is used, the shot gate material layer may not be able to withstand the heat treatment. In addition, when processing this high-melting point metal material into a Schottky gate shape, it is possible to process the shape vertically and neatly, and the thickness of the Schottky gate can be made sufficiently thick. It is generally processed by etching. Furthermore, in the explanation of FIG. 5 above, the manufacturing process for forming a Schottky gate type FET was explained, but when forming a diode element, a resistor element, etc. together with the FET, impurity ions may be introduced into the active region of the element. The heat treatment process after injection, etc.
Processes common to the ET manufacturing process are generally performed at the same time.

In this way, for example, when forming a Schottky gate type FET and a resistance element on the same semiconductor substrate, as shown in FIG. 1
Since the surface is exposed to plasma, ions in vacuum are S, 1. It collides with atoms on the surface of the GaAs substrate and forces them out.

1. There is a problem in that damage is caused to the surface of the S, I, GaAs substrate, such as by breaking atomic bonds on the surface of the GaAs substrate, and this adversely affects the characteristics of the resistor element. This damage causes problems in terms of production, such as making it difficult to manufacture the resistive element according to the designed value, and also increasing the dispersion in performance from product to product, resulting in poor yield. Therefore, it is an object of the present invention to provide a semiconductor device manufacturing method for preventing damage caused to element forming regions other than FETs by dry etching and for producing high-quality semiconductor elements such as resistive elements with good in-plane uniformity and reproducibility. This is the purpose of

[Means for solving problems]

The reason why the element formation region where semiconductor elements such as the above-mentioned resistor elements are formed is damaged during dry etching using plasma to process the gate electrode of the FET is that the semiconductor crystal surface of the element formation region is damaged. This is because the semiconductor crystal is exposed to plasma during dry etching and ions in vacuum collide with the semiconductor crystal. Therefore, in the present invention,
The element formation region and/or its surrounding area is covered with a damage protection film made of an insulating film, photoresist, etc., and then a layer of high melting point shortcut gate material such as WSi is formed on the surface of the semiconductor substrate by sputtering method etc.) Next, CV
A SiO□ layer is formed by the D method, and then Schottky
Cover the area where the gate will be made with photoresist. Through these steps, the element formation region is not exposed to plasma during dry etching using plasma, and the surface of the element formation region is prevented from being damaged.

[Effect]

As explained above, if the element formation region and its surrounding area are covered with a damage protection film, the surface of the element formation region will not be exposed to plasma during dry etching using plasma to form a Schottky gate. It can be avoided. Therefore, unlike the conventional example, the surface of the element formation region is not damaged by ions in vacuum, and the performance of the semiconductor element can be kept constant, improving in-plane uniformity and reproducibility.

〔Example〕

FIGS. 1A to 1J are cross-sectional views of the manufacturing process of the first embodiment of the present invention, showing the manufacturing process of an FET and a resistance element.

(1) As shown in FIG. 1(a), S, 1. An ion implantation mask 2 using Sing, photoresist, etc. is deposited on the GaAs substrate 1, and the exposed resistance implantation region is injected with an energy amount of 120 XeV and a dose of N IXIO13c.
An n-type resistance implantation region 4 is formed by selectively implanting ions at m-''.

(2) As shown in FIG. 1(b), the ion implantation mask 2
After removing the ion implantation mask, an ion implantation mask was applied in the same manner as in FIG. By doing so, an n-type channel layer 7 is formed.The order in which the resistance implantation region 4 and the channel layer 7 are formed does not matter. The amount and dose may differ somewhat depending on the design performance of the FET and resistance element to be manufactured.

(3) Next, as shown in FIG. 1(c), S, 1. GaA
The surface of the s-substrate 1 is coated with a heat-treated protective film 8 such as SiO□ to prevent arsenic in the substrate from evaporating under high-temperature conditions.
Heat treatment is performed at 0° C. for 10 minutes to activate the implanted impurities.

(4) As shown in FIG. 1(d), the heat-treated protective film 8 is removed, however, the area on the resistor injection region 4 is left for later use as a damage protective film 9.

(5) As shown in FIG. 1(e), 1. . A high melting point Schottky gate material 10 such as Si6.4 is formed using a method such as a sputtering method, and then an SiO□ layer 11 is formed using a CVD method or the like.

Next, the photoresist is patterned into a gate shape, and SiO□N11 is first dry etched to the gate size. The etching gas used is fluorine-based CF4.
CHF3 etc. are used.

(6) As shown in FIG. 1(f), the SiO□ layer 1
-1 as a single layer type 1. . The Si6,6 layer 10 is dry etched to the gate size by dry etching using plasma. In the dry etching performed here, the semiconductor substrate to be etched is placed below two vertically parallel electrodes in a vacuum container, and while an etching gas such as CF4 is injected, a A method is used in which a high frequency of about .56 M)lz is applied to create a plasma state in the container, and ions in a vacuum are perpendicularly collided with the semiconductor substrate. As a result, as shown in FIG.
Since the surface is covered with a damage protection film 9, it is not exposed to plasma during dry etching and is not damaged. The damage protection film 9 needs to have a thickness of 2000 Å or more in order to prevent the resistance injection layer 4 from being etched during the process of forming a Schottky gate by dry etching using plasma.

(7) As shown in FIG. 1(c), the damage protection film 9 is removed, and then the ion implantation mask 15 made of an oxide film or the like and the Schottky gate 16 are removed as shown in the figure.
is used as a mask, the energy amount is 175KeV,
Si" ions are implanted at a dose of 2.times.10"cn+-" to form the source and drain regions 17 and 18 of the FET and the n' contact region 19 of the resistor implantation region.

(8) As shown in FIG. 1(i), the ion implantation mask 1
After removing 5, in order to electrically activate the implanted impurity Si, the surface of the semiconductor substrate is covered with a heat treatment protective film 20 as shown in FIG.

(9) Finally, as shown in FIG. 1 U), after removing the heat treatment protective film 20, using AuGe/Au,
An ohmic electrode 21 is formed in the contact region 19.

The integrated circuit is then constructed by appropriately wiring FET resistance elements and the like.

As explained above, in the present invention, the resistance element region is covered with a damage protection film to prevent exposure to plasma during dry etching. Therefore, the resistance element region is prevented from being affected by damage, and the resistance value does not fluctuate, so that the in-plane uniformity and reproducibility of the resistance value can be improved.

Next, a second example will be described which shows a method for manufacturing an FET and a resistance element in the case where a dummy pattern is provided.

In the first embodiment, the surface of the resistance implantation region 4 is coated with a damage protection film 9, thereby preventing the surface of the resistance implantation region from being exposed to plasma during dry etching using plasma, thereby preventing damage. However, it is also possible to reduce the dry etching damage caused to the resistor element region by forming a dummy pattern around the resistor element forming region. Therefore, in the second embodiment, a dummy pattern is provided in the vicinity of the resistor element formation region to prevent the vicinity of the resistor element formation region from being damaged by dry etching using plasma.

Damage to the surface of a semiconductor crystal during dry etching using plasma can be reduced by heat treatment.
It can be reduced to a considerable extent. Furthermore, it has been revealed that the rate of damage reduction is faster when a dummy pattern is formed than when there is no damage retaining ta film. This difference is thought to be caused by whether or not there remains an undamaged portion on the surface of the semiconductor substrate in the vicinity of the resistive element region. If the surface of the resistor implanted region is not covered with a damage protection film during dry etching, the entire surface of the resistor implanted region will be damaged, and bonds between atoms may be broken or atoms may be missing. It becomes a state. On the other hand, if a dummy pattern is formed in the peripheral region of the surface of the resistance injection layer, the region directly under the dummy pattern will not be damaged even if dry etching is performed. For this reason, when heat treatment is performed to recover from damage, the recovery progresses with the undamaged portion as the core, so the amount of damage that remains is ultimately smaller when a dummy pattern is provided than when no protection is provided. It is.

Note that since the heat treatment for recovering damage is performed simultaneously with the heat treatment for activating the impurity after the impurity implantation, there is no need to separately perform heat treatment for recovering damage.

FIGS. 2(a) to 2(j) are drawings illustrating a second embodiment showing the manufacturing process of an FET and a resistance element when a dummy pattern is provided. Note that the same parts as in FIG. 1 are given the same numbers and their explanations are omitted.

(1) As shown in FIG. 2(a), S, 1. An ion implantation mask 2 made of SiO□, photoresist, etc. is deposited on a GaAs substrate 1, and the exposed channel layer formation region is injected with an energy amount of 5QKeV and a dose amount of 2X10"cm.
An n-type channel layer 7 is formed by implanting Si''- ions.

(2) As shown in FIG. 2(b), S, 1. GaAs group vi
The surface of 1 was coated with a heat-treated protective film 20, and heated at 850°C10
Heat treatment is performed for a minute to electrically activate the implanted impurities.

(3) As shown in FIG. 2(C), the heat-treated protective film 20 is removed. Further, at this time, the peripheral portion of the resistor implantation region is left for use as a dummy pattern when performing dry etching using plasma to process the Schottky gate.

(4) As shown in FIG. 2(d), S, 1. -1, on the surface of the GaAs substrate 1. A high melting point Schottky gate material such as Sio,i is formed using a sputtering method,
Next, a Si02 layer 11 is formed using a CVD method or the like.

Furthermore, a photoresist 24 is formed. Next, the photoresist 24 is patterned into a gate shape by photolithography. Continuing, as shown in Figure 2(e),
Using this photoresist 24 as a mask, the 5iOt layer 11 is dry etched to the gate size.

(5) Next, the high melting point Schottky gate material layer 10 is dry etched using the Si02 layer 11 as a mask to form a Schottky gate 16 as shown in FIG. 2(f). At this time, the surface of the resistive element formation region is exposed to plasma and damaged by ions in vacuum, but the region directly under the dummy pattern remains undamaged.

(6) As shown in FIG. 2 (8), the dummy pattern 22
Then, as shown in the figure, an ion implantation mask 15 made of an oxide film or the like and two parts of the Schottky gate 16 are removed.
Using one as a mask, St” ions are
It is implanted at 175 KeV and at a dose of 2×10 cm to form the source/drain regions 17.18 of the FET and the n-contact 9M region 19 of the resistance implantation region.

(7) As shown in FIG. 2 (b), the amount of energy 1
20KeV, dose it I X 10tScm-
"St" ion implantation is performed. Furthermore, (6) and (7)
It doesn't matter if you do it the other way around.

(8) As shown in FIG. 2(i), in order to electrically activate the impurities implanted into the source/drain regions 17 and 18 of the FET, the resistance injection region 4, and the n' contact region 19 of the resistance injection region. Perform heat treatment.

(9) Finally, as shown in FIG. 2(j), after removing the heat-treated protective film 20, an ohmic electrode 21 is formed.

In this way, by forming a dummy pattern in the peripheral region of the resistor implanted region in advance before dry etching, although the resistor implanted region 4 is turned into plasma during dry etching, the region around the resistor implanted region 40 is not damaged. Therefore, subsequent fluctuations in resistance value are reduced, and in-plane uniformity and reproducibility of resistance value are improved.

The manufacturing process and effects of FET and resistance elements in the case where a dummy pattern is provided in the peripheral area of the resistance element area have been described above, but the present invention is applicable to the process of dry etching using plasma used in Schottky gate fabrication. It is also effective to reduce damage to the FET0n type channel layer 7 due to exposure to plasma.

That is, in FIG. 2(C), by forming the dummy pattern 22 near the resistance element and simultaneously providing the dummy pattern 30 near the n-type channel layer, the channel layer 7 can be etched by dry etching using plasma. It can reduce the damage received.

Next, a third example will be shown. The third example is a combination of the first example and the second example. That is, in the first embodiment, the surface of the resistor element forming region is coated with a damage protection film to prevent damage to the resistor element forming region during dry etching.
In this embodiment, by forming a dummy pattern around the resistor element formation region, the resistor element region is exposed to plasma during dry etching using plasma to form a Schottky gate, as shown in FIG. 2(f). Although it is damaged, the area near the resistor element area is not damaged because of the dummy pattern, so the damage on the resistor element surface can be recovered quickly, and the degree of damage that remains even after recovery is lower than when no damage protection film is provided. It will be less than that. Therefore, as shown in FIG. 3, if the surface of the resistive element formation region 25 and its surrounding area are covered with the damage protection film 9, the effect of preventing damage during dry etching becomes more pronounced.

The embodiment has been described above, and FIG. 7 shows its effects.

FIG. 7 shows how the relationship between the ion implantation amount for forming the resistance implantation region 4 and the sheet resistance in the above embodiment changes depending on the presence or absence of the damage protection film and the dummy pattern.

As you can see from the figure, the absolute values of resistance are shown in the following order: without protective film, with dummy pattern, and with protective film.

The variation is also smaller. When comparing the case where no protective film is provided and the case where a dummy pattern is provided, the variation is reduced to about 115.

It can be seen that the degree of damage can be significantly reduced just by providing a dummy pattern.

In the above embodiments, the high melting point Schottky gate material is not limited to WSi, but any material that has a high melting point and can withstand heat treatment may be used, and the semiconductor substrate crystal may also be G.
In addition to aAs, the same effect can be obtained using other ■-V group compound semiconductors, silicon, etc. Furthermore, although the above embodiment deals with dry etching performed for Schottky gate processing, the present invention is not limited to this, and similar effects can be obtained when dry etching is performed for other purposes. Further, in the above embodiment, a resistive element is used as a forming element, but the present invention can also be applied to other semiconductor elements having an impurity conductive region, such as a diode or a condenser.

Incidentally, in the first embodiment, the resistance implantation region is formed before the dry etching for Schottky gate processing, that is, in FIG. The same effect can be obtained even if the Schottky gate is formed after the Schottky gate processing, as long as the surface of the area to be damaged is covered with a damage protection film. Also,
In the first embodiment, a heat-treated protective film was used as the damage protective film, but if it can be removed without etching the semiconductor substrate, an insulating film such as SiN and photoresist may be used as the protective film. The same effect can be obtained. However, it will add one step. Furthermore, in the second embodiment, the resistance implantation region is formed after the dry etching process for Schottky gate processing, but this is done in order to prevent the impurity ions Si implanted during dry etching from being damaged. This is to do so. Further, in the second embodiment, as in the first embodiment, it is also possible to use an insulating film, photoresist, etc. as the damage protection film. Also, as a dummy pattern, high melting point gate material W1. . It is also possible to use Sio and blO. In this case, as shown in FIG. 8(a), when patterning the photoresist 24 into the Schottky gate shape, a photoresist 25 is simultaneously formed on the area where the dummy pattern is to be formed. [Effects of the Invention] As described above, By covering the element formation region except for the FET with a damage protection film, damage to the surface of the element formation region during dry etching using plasma for forming a Schottky gate can be reduced.

Furthermore, if the vicinity of the element forming area is covered with a dummy pattern, the element forming area will be exposed to plasma during dry etching and will be damaged by ions in vacuum, but the area directly under the dummy pattern will hardly be damaged. Therefore, the speed of recovery from damage caused by heat treatment is faster, and the damage remaining after heat treatment is also reduced compared to when no damage protection film is provided. Therefore, according to the present invention, it is possible to improve the in-plane uniformity and reproducibility of a semiconductor element, and it is possible to bring about a great effect on the practical application of semiconductor integrated circuits.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the manufacturing process of the FET and resistance element, Figure 2 is a cross-sectional view of the manufacturing process of the FET and resistance element when a dummy pattern is used, and Figure 3 is damage protection for the element formation area and its surrounding area. A cross-sectional view of the manufacturing process of an FET and a semiconductor element when coated with a film, Figure 4 is a cross-sectional view of an integrated circuit with a conventional FET, a resistor, and a diode, and Figure 5 is a cross-sectional view of an FET and a semiconductor element covered with a film.
6 is a cross-sectional view showing the manufacturing process of the semiconductor substrate, and FIG. 6 is a cross-sectional view showing the damage caused to the semiconductor substrate by dry etching.
FIG. 7 is a drawing showing the relationship between ion implantation amount and sheet resistance, and FIG. 8 is a sectional view showing the manufacturing process when the gate material of an FET is used as a dummy pattern. 1 is a semiconductor substrate (gallium arsenide), 2.3.5.15
is an ion implantation mask, 4 is a resistance implantation region, 6 is an FET,
7 is an n-type channel layer, 8.20 is a heat treatment protective film, 9 is a damage protective film, and 1o is a high melting point Schottky. Gate material layer, 11 is a Sin, layer, 12.23 is a photoresist, 13 is a resistor, 14 is a diode, 16 is a Schottky gate, 17 is a source region, 18 is a drain region, 19 is a resistive injection region contact 9M 21 is an ohmic electrode, 22.30 is a 5iOz dummy pattern, 24 is a photoresist for gate processing, 25 is an element forming area, 26 is a photoresist for a dummy pattern, 27 is an F
The ET formation region and 28 indicate the resistance element formation region. 11 customers in total - 9 in total! Figure 2 Gummy/Zuturn proof cleaning/: Lillee reference-d'ET and #L
Geki J7 Cold 5 Kenko FETQK1. RM for 1st year of junior high school

Claims (1)

[Claims] A first region on a semiconductor substrate in which a field effect transistor (FET) having a high melting point Schottky gate is formed, and a second region in which an element other than a field effect transistor is formed by implanting impurities. an integrated circuit device having a second region and/or a peripheral region thereof with a damage protection film, and a layer of high melting point Schottky gate material on the surface of the semiconductor substrate and on the damage protection film. forming a Schottky gate; forming a Schottky gate by patterning photoresist into a gate shape on a Schottky gate forming region and etching using plasma; and using the Schottky gate as a mask to form a Schottky gate; A method for manufacturing a semiconductor device, comprising the steps of: injecting impurities into the semiconductor substrate to form source and drain regions; and forming a heat treatment protective film on the surface of the semiconductor substrate and the Schottky gate, and then performing heat treatment.