JPS63314047A - Signal reception circuit - Google Patents

Abstract

PURPOSE:To extend the noise margin by connecting outputs of two comparators, which are connected to signal input terminals in in-phase and anti-phase states, to a flip flop through integrating circuits and controlling a reception circuit by the output of the flip flop. CONSTITUTION:A reception circuit 3 with a control terminal C connected between signal input terminals through a bias circuit 2, two comparators 5 and 4 connected between signal input terminals in in-phase and anti-phase states, integration circuits 7 and 6 added to outputs of these comparators, and a flip flop 8 to which outputs of both integrating circuits are connected are provided, and the output of the flip flop 8 is connected to the control terminal C of the reception circuit 3. The constant of the integration circuit of the comparator connected in the anti-phase state is set to a small value and a set signal is outputted to the flip flop 8 by the first pulse, and that of the integration circuit of the comparator 5 connected in the in-phase state is set to a large value, and a reset signal is sent to the flip flop 8 when an input signal having a prescribed polarity continues for the signal period or longer. Thus, the input signal only in a prescribed period is amplified.

Description

[Detailed Description of the Invention] [Summary] The present invention is a signal receiving circuit in a signal transmission system between devices, in which a bias is applied to a signal input terminal of the receiving circuit with a control terminal, and the signal input terminal is set to have positive and negative phases. The two comparator outputs connected to the receiver are connected to a flip-flop via an integrating circuit, and the receiving circuit is controlled by the output of the flip-flop.

In addition, the noise margin of the receiving circuit in long-distance transmission between information processing devices can be increased.

[Industrial application field]

The present invention relates to a signal receiving circuit in a signal transmission system between devices.

In long-distance signal transmission between information processing devices, because the difference in ground potential is large, a DC separated balanced transmission system is often used in which a pulse transformer is used to connect a transmission line to a receiving circuit.

However, in this transmission method, a bias is applied between the input terminals of the receiving circuit in order to prevent the receiving circuit from oscillating when there is no signal, but on the other hand, this bias can cause noise to be mistaken for a signal. Become.

Therefore, there is a need for a signal receiving method that increases the discrimination difference (noise margin) between the signal and noise of this receiving circuit.

[Conventional technology]

FIG. 4 shows a conventional signal receiving circuit using a direct current separated balanced transmission system for long-distance transmission between information processing devices.

As shown in FIG. 4, the signal on the transmission line passes through the pulse transformer 1 and becomes the received signal voltage VIN.

The output terminal of the pulse transformer 1 is connected via a bias circuit 2 to input terminals X and Y (Y is an inverted signal input terminal of X, ie, a Y signal terminal) of a receiving circuit 3.

Bias circuit 2 has a power supply voltage (+5 V) connected to resistor R.
+, RZ, R:I, Rho, and R8, and both ends of R2 are connected as a bias voltage 6 to the input terminal of the receiving circuit 3 in parallel with the input signal voltage.

Receiving circuit 3 amplifies the signals input from input terminals X and Y to output voltage ■. Output ut.

FIG. 5 shows an operation timing diagram of the circuit shown in FIG. 4, in which the pulse signal voltage VIN is input and the output voltage is . I and A are output.

[Problem that the invention seeks to solve]

In this conventional system, if no bias is applied, when no signal is being transmitted, that is, in an idle state, the potential difference between the input terminals of the receiving circuit becomes O, and the output of the receiving circuit oscillates.

In order to prevent this oscillation, a bias circuit is added between the pulse transformer and the input terminal of the receiving circuit to provide a potential difference between the input terminals of the receiving circuit.

However, if noise mixes during signal transmission, there is a high possibility that this noise will be mistakenly received as a signal.

As shown in FIG. 5, in the circuit of FIG. 4, the input signal voltage V
The voltage between HH and ■8 is amplified and output signal voltage V. u
It becomes T.

FIG. 6 is a diagram illustrating malfunctions caused by noise. When noise N (N>V++) is input, it is amplified like a signal, so the noise is output at the same voltage level as the signal and is mistakenly recognized as a signal.

The present invention has been created in view of the above points, and an object of the present invention is to provide a signal receiving circuit using a direct current separated balanced transmission method, which has a larger noise margin and improved noise discrimination performance. It is an object.

[Means for solving problems]

In order to achieve the above purpose, a receiving circuit with a control terminal is connected between the signal input terminals via a bias circuit, two comparators are connected between the signal input terminals in positive and opposite phases, and each comparator output and a flip-flop connected to the outputs of both integrating circuits, and the output of the flip-flop is connected to the control terminal of the receiving circuit.

[Effect]

The integrator circuit constant of the comparator connected in opposite phase to the input terminal of the receiving circuit is set small so that the first pulse outputs a set signal to the flip-flop, and the receiving circuit is excited by the output of the flip-flop and is in the operating state. becomes.

The input signal is amplified by the receiving circuit and output from its output terminal.

On the other hand, the integrator circuit constant of the comparator in the same phase as the receiving circuit is set large so that when the input signal of a predetermined polarity continues for more than the signal period, a reset signal is sent to the flip-flop, and the receiving circuit is blocked by the output of the flip-flop. Put it into working condition. Therefore, the receiving circuit operates only on input signals of a predetermined period to amplify the signals.

Moreover, since a bias is applied, oscillation is suppressed.

〔Example〕

Fig. 1 is a block diagram of the configuration of an embodiment of the signal receiving circuit of the present invention, Fig. 2 is a diagram explaining the operation of the circuit shown in Fig. 1, and Fig. 3 shows the case where noise in the circuit shown in Fig. 1 is caused by human input. FIG.

Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 1, an input signal v1N input to a pulse transformer 1 is amplified by a receiving circuit 3 with a control terminal via a bias circuit 2, and an output signal 2 is obtained. , outputs a.

On the other hand, the input signal VIN is input to a comparator 4 connected in opposite phase to the receiving circuit 3, and is connected to a resistor R4 and a capacitor CI.
The signal is input to a set terminal S of a flip-flop 8 via an integrating circuit 6 configured as shown in FIG.

In addition, the input signal VIN is input to a comparator 5 connected in the same phase as the receiving circuit 1, and is connected to a resistor R6 and a capacitor C2.
The signal is inputted to the reset terminal R of the flip-flop 8 via the integrating circuit 7 configured as follows.

The output terminal 0 of the 7-flop 8 is connected to the control 11 terminal C of the receiving circuit 3, and the signal "0" at the control terminal C is connected to the control terminal C of the receiving circuit 3.
The receiving circuit 3 is excited by the signal “1” at the control terminal C.
” is occluded.

The comparator 4.5 is an oven collector output circuit, and the signal input to the S terminal of the flip-flop 8 is ``■'', and the signal input to the R terminal is ``■''.

When no input signal arrives, the bias voltage ■ is applied by the bias circuit 2, so the output of the comparator 4 is ON and the signal ■ is low level "L", the output of the comparator 5 is OFF and the signal ■ is high. The level becomes rHJ, the output signal of the flip-flop 8 is "1", and the receiving circuit 3 is blocked and is in a non-operating state.

Then, when the input signal arrives, the signal (2) rises with the time constant of the resistor R4 and the capacitor CI, and the dark value voltage (approximately 1.
3V), the flip-flop 8 is set.

Then, the signal at the output terminal O of the flip-flop 8 is "0".
'', the receiving circuit 3 is excited and becomes operational.

Therefore, the input signal of the receiving circuit 3 is outputted to the output terminal.

On the other hand, by selecting the time constant of the resistor R5 and capacitor C2 of the integrating circuit 7 to be larger than the maximum pulse width of the signal, the signal 2 can always be at the low level rLJ when the input signal arrives.

Next, FIG. 3 shows the operation when high frequency noise is induced in the input signal.

Since the noise component is removed by the time constant R4Cl of the integrating circuit 6, the flip-flop 8 is not set.

Therefore, the receiving circuit 3 is blocked and kept inactive,
Noise does not appear at the output of the receiving circuit 3.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to eliminate noise when no input signal arrives while maintaining a large noise margin during normal communication of the signal receiving circuit of the DC separated balanced transmission method in transmission between information processing devices. It can improve the ability and is extremely useful in practical terms.

[Brief explanation of drawings]

Fig. 1 is a circuit configuration diagram of an embodiment of the signal receiving circuit of the present invention, Fig. 2 is an operation timing diagram of the circuit shown in Fig. 1, Fig. 3 is a diagram explaining the operation in the case of noise generation, Fig. 4 5 is a diagram illustrating a conventional signal receiving circuit, FIG. 5 is an operation timing diagram of the circuit shown in FIG. 4, and FIG. 6 is a diagram illustrating malfunction due to noise. In the figure, 1 is a pulse transformer, 2 is a bias circuit, 3 is a receiving circuit, 4.5 is a comparator, 6.7 is an integrating circuit, 8 is a flip-flop, and C is a control terminal of the receiving circuit 3. Ichimaru persimmon example supination of the participating BPI Fig. 1 Fig. 3 Uhi
Figure Sub-example 17 Tumor recess ■ 4 limbs 73 Figure 4 Figure 4

Claims (1)

[Claims] A receiving circuit (3) with a control terminal (C) connected between signal input terminals via a bias circuit (2), and a comparator connected in opposite phase to the receiving circuit (3) between the signal input terminals. (4), an integrating circuit (6) added to the output of the comparator (4), a comparator (5) connected between the signal input terminals in the same phase as the receiving circuit (3), and the comparator (5) The integration circuit (6) added to the output
) with a larger time constant than the integrating circuit (7), and both integrating circuits (
6, 7) and a flip-flop (8) whose outputs are set to the set and reset terminals, and the output of the flip-flop (8) is connected to the control terminal (C) of the receiving circuit (3).
A signal receiving circuit characterized in that it is connected to.