JPS63313903A - Amplification circuit and light communication system using it - Google Patents

Abstract

PURPOSE:To prevent the increase of a power supply voltage, necessitated for the operation of an amplification circuit by providing a first FET, a second FET, a loading means and a current bypassing means, and connecting the drain of the FET of one side to a first operating potential point, and connecting the source of the first and the second FETs to a second operating potential point. CONSTITUTION:A first amplifying element 1 is constituted of the FETs Q1, Q2, the sources of which are connected differentially. Besides, the loading means 2 is constituted of a pair of resistors RL, and the current bypassing means 4 is constituted of a constant-current source to let a DC current I1 flow. Assuming that the DC current to the said constant-current source 4 is I1, the increase of an amplification factor Gv can be achieved by constituting the current of the constant-current source 3, added to the source part of a differential pair FET, so as to be I0 + 2I2. On the other hand, since the current to contribute to an output amplitude is only I0, it comes to V0 = RL.I0, and the increase of a DC voltage drop and the band deterioration of a loads 4, accompanied by the improvement of a gain Gv, are not generated theoretically. Namely, by adding the constant current I1, only the gm of the differential pair FET Q1, Q2 is improved, and the high gain can be realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an amplifier circuit, and more particularly to a method for increasing the gain of a differential amplifier or varying the gain, and particularly for integrating high-speed transmission circuits such as optical communications. The present invention relates to a wideband high gain amplifier suitable for

[Prior Art] A conventional differential amplifier is, for example, a low-power, source-coupled FET logic (SCFL) based GaAs
As shown in ``IC High Speed Frequency Divider'', a set of differential pair transistors, a load resistor connected to the drain of the differential pair,
It consists of a constant current source connected to the source, and uses the fact that the constant current source current is distributed according to the difference in gate input voltage of each differential pair to generate the output signal as a voltage drop across the load resistance. This is what is output. FIG. 2 shows a conventional circuit configuration. In Figure 2, the load resistance is RL.

Creates a constant current. and Q of each differential pair transistor.
l, Q2, and the mutual conductance constant is g□.

When the K value is K, the voltage gain gv is given by the following equation.

G v ” g engineering・RL (1) [Problem to be solved by the invention] In the case of a differential amplifier using a bipolar transistor, gm is given by the following equation.

Here, q is electron charge, k is Boltzmann's constant, T is absolute temperature, and re is emitter resistance. Therefore, gm: 40m
If the load resistance is Siemens and the load resistance RL is 500Ω, the gain will be about 20 times.

On the other hand, in the case of a differential amplifier using field-effect transistors (hereinafter referred to as FETs), gm is expressed by the following formula % where Rg is the source resistance. Therefore, gmz 5
m Siemens, and the gain is approximately 2.5 times for the same load resistance, which is approximately 1/8 gain reduction compared to the case of bipolar transistors. .

In this way, the reason why the mutual conductance gm of a bipolar transistor is large is that the collector current or emitter current increases exponentially in response to an increase in base-emitter voltage.
The reason why Tl is small is that the train current or source current increases in a square manner in response to an increase in gate-source voltage.

As mentioned above, in a bipolar transistor, gm
Because of the large g
Since m is small, the gain using the same load resistance is about 1/8. Therefore, in order to obtain a high gain in the FET amplifier circuit, it is necessary to increase the number of connected stages of the multistage amplifier. However, studies conducted by the inventors of the present application have revealed that as the number of connected stages of a multistage amplifier increases, the amplification band becomes narrower.

This is due to the following matters.

That is, one bipolar transistor or FET amplification element of each stage in a multistage amplifier necessarily has a phase shift with respect to its amplification effect (eg, amplification factor). In other words, the frequency at which the high frequency amplification factor is -3 dB lower than the low frequency amplification factor is called the cutoff frequency, and for input signals with frequencies higher than this cutoff frequency, the amplification value of the amplified output signal decreases, and its delay phase The transition will be large. Therefore.

An increase in the number of connected stages of a multistage amplifier causes an increase in the number of connected amplification elements on the signal transmission path from the input to the output of the entire multistage amplifier. This means that the cutoff frequency, which is related to the amplification factor of the entire multistage amplifier, is significantly lower than the cutoff frequency of the amplification factor of one amplification element.
As a result, the amplification band of the multistage amplifier becomes narrower.

Furthermore, an increase in the number of connected stages of a multi-stage amplifier also causes the following problems. That is, by connecting the output of the pre-stage amplifier and the input of the post-stage amplifier, a time constant is formed by the product of the output resistance of this output and the input capacitance of this input.

The increase in the number of connection stages described above causes an increase in the time constant,
After all, the amplification band of the entire multistage amplifier becomes narrower. This becomes noticeable when constructing a multi-stage amplifier using FETs having relatively large gate capacitance. Furthermore, since the gm of a FET is proportional to the gate width, it is possible to increase the gain by using a FET with a large gate width, but this also increases the gate capacitance icgs.

CGA and the like also increase, resulting in a problem that the band is significantly degraded. Furthermore, if the mutual conductance of the amplification element is gm and the load resistance is RL, then the voltage amplification factor Gv of the amplification circuit consisting of this amplification element and the load resistance is G
v ” g m ” RL.

Therefore, by increasing the resistance value RL of the load resistor, the voltage amplification factor Gv can be increased, but the Miller capacitance (
For example, a large time constant is formed by the Miller capacitance between the base and the collector or the Miller capacitance between the gate and the drain, which results in narrowing the band of the amplifier circuit itself.

The present invention has been made based on the above study results, and its main objective is to increase the amplification factor of the single-stage amplifier circuit itself.

Another object of the present invention is to provide a multistage amplifier with a high gain and a wide band by using the amplifier circuit with an increased amplification factor as described above in a multistage amplifier. Further objects and novel features of the present invention will be easily understood from the following description.

[Means for Solving the Problems] The above problems are basically solved by increasing the DC bias current of the amplification element.

That is, the mutual conductance gm of the amplifying element increases in proportion to the increase in the insulating current. For example, in a bipolar transistor, the emitter resistance re decreases as the bias current increases, so (2)
The mutual conductance gm increases according to the equation. on the other hand,
For FET, bias current engineer. By increasing , the mutual conductance gm increases according to the above equation (3).

Thus, as the bias current increases, the mutual conductance gm itself increases, and as a result, the voltage gain Gv increases.

By the way, since the amplifying element and the load resistor are connected in series in the amplifying circuit, increasing the DC bias current of the amplifying element also increases the DC voltage drop across the load resistor. Therefore, there arises an inconvenience in that the power supply voltage necessary for the operation of the amplifier circuit must be increased in accordance with the increase in the DC voltage drop.

In order to alleviate such inconveniences, the present invention basically has the following features.

That is, the output electrode (e.g. collector or drain) of the first amplification element (e.g. bipolar transistor or FET) is connected to one end of the load means (e.g. resistor), and the other end of this load means is connected to the first operating potential point (e.g. positive Connected to the power supply voltage ■.D).

A ground electrode (eg, emitter or source) of the first amplification element is connected to a second operating potential point (eg, ground voltage GND). The DC bias current of the first amplifying element is set to a large value so that the mutual conductance of the first amplifying element is a large value. Further, a current bypass means is connected to a connection node between the load means and the output electrode of the first amplification element so as to bypass a part of this DC bias current.

Note that the input electrode and the ground electrode of the first amplification element respond to an input signal.

According to an improved embodiment of the present invention, the input electrode (eg, base or gate) of the first
Additional amplification elements (e.g. bipolar transistors or FE
T) is placed. The ground electrode of this first additional amplification element (
For example, the emitter or source) is connected to the output electrode of the first amplification element.

An output electrode (eg collector or drain) of the first additional amplification element is connected to one end of the load means. Accordingly, direct connection between the output electrode of the first amplification element and the load means is avoided, thereby preventing formation of a large time constant due to the load means and the Miller capacitance of the amplification element.

According to a further improved embodiment of the invention, the current bypass means are connected to the ground electrode of the first additional amplification element.

If the current bypass means is connected to the output electrode of the first additional amplification element, the load means and the current bypass means are connected in parallel.

Since the impedance of this parallel connection is lower than the impedance of the load means, the voltage amplification factor Gv decreases. The impedance seen from the ground electrode of the first additional amplification element to which the input electrode is connected in an alternating current manner is a value that is sufficiently smaller than the impedance of the current bypass means. Therefore, the first
Most of the alternating current flowing to the output electrode of the amplifying element flows to the ground electrode of the first additional amplifying element, and almost no alternating current flows through the current bypass means, and substantially only direct current flows. Therefore, the voltage amplification factor Gv is prevented from decreasing as described above. Furthermore, the low alternating current impedance at the ground electrode of the first additional amplification element avoids the formation of large time constants due to the relatively large impedance of the current bypass means and the Miller capacitance of the first amplification element.

[Function] According to the basic feature of the present invention, the DC bias current flowing through the first amplification element is set to a relatively large value, so that the mutual conductance gm of the first amplification element is set to a large value. The amplification S$ of the one-stage amplifier circuit itself including the element increases.

Furthermore, the current bypass means bypasses the load means and allows at least a portion of the DC bias current to flow, thereby reducing an increase in the DC voltage drop in the load means and also reducing an increase in the power supply voltage of the amplifier circuit.

[Embodiment] FIG. 1 shows a circuit diagram of an amplifier circuit according to an embodiment of the present invention, and this amplifier circuit can be used as an amplifier in at least any stage of a multi-stage amplifier.

In the figure, a first amplification element 1 is constituted by FETs QI and Q2 whose sources are differentially connected, and a load means 2 is constituted by a pair of resistors RL. It is necessary that the impedance of the current bypass means 4 is greater than the impedance of the load means 2. Therefore, in this embodiment, the current bypass means 4 is constituted by a constant current source that passes a direct current 11, but it may be replaced by other means such as a resistor with a large resistance value. Further, a constant current source that flows a direct current is connected to the sources of the differential pair FETs QI and Q2 as a source common impedance means 3, but this common impedance means 3 may be replaced by a resistor. That is, in FIG. 1, the differential pair FETQ ], .

Add a load resistance of 1 to each drain of Q2. and another constant current source 4
Add.

If the DC current of this constant current source 4 is 1, then the differential pair FE
The current of constant current source 3 added to the source part of T is ■. +2I
, an increase in the amplification factor Gv is achieved. Further, the degree of improvement in this gain can be adjusted by adjusting the current value (1).

As mentioned above, in FIG. 1, the FET differential pair Ql, Q
A constant current source 4 is added to the drain of FETQI, Q2.
By supplying a direct current of , it is possible to achieve a high gain. Now, the current of the constant current source 3 connected to the sources of the FET differential pairs Ql and Q2 is calculated. , Ql, and Q2, and the load resistance is RL, the current of constant current source 4 is I
, = 0, the profit tj) is expressed by equations (1) and (3).

In equation (3), if the second term 1/R8 is compared to the first term and ignored.

becomes. However, ■1≠O constant current ■1 is constant current source 4
If given by , then . On the other hand, the current that contributes to the output amplitude is I.

■ Because it is only. =RL・ENG. Therefore, theoretically, an increase in the DC voltage drop of the load 4 and band deterioration due to an increase in the gain Gv do not occur. That is, by adding the constant 'a flow,'
By improving only the gm of the differential pair FETs QI and Q2, a high gain can be achieved.

FIG. 3 shows a modification of the embodiment shown in FIG. 1, in which the first additional amplifying element 5 is a FET Q3. It is composed of Q4. FETQ
3. The AC grounding of the gate of Q4 applies a predetermined DC voltage to this gate. The difference between a3 and the application circuit diagram is that F
Between the drains of the ET differential pairs Ql and Q2 and the load resistance RL, there is a FET differential pair Q3. Q4 is connected. In FIG. 1, the AC signal current component is I. If the additional constant current source circuit 4 has a sufficiently high AC impedance compared to the load resistor RL, all of the current flows through the load resistor RL, and outputs the AC amplified RL·To as in theory. However, if the constant current source 4 is not completely high impedance, the alternating current source 4 is not completely high impedance. A part of constant current′
The current flows to tX4, resulting in a decrease in the AC output amplitude.

On the other hand, as shown in Fig. 3, additional FETs Q3, Q4
By cascode-connecting the input source to the drains of the differential pair FETs QI and Q2, the drop in the AC output amplitude as described above can be prevented. That is, additional FETQ3. whose gate is AC grounded. Since the impedance seen from the source of Q4 is sufficiently smaller than the impedance means of constant current source 4, differential pair FET Q1. Most of the alternating current flowing to the drain of Q2 flows through the additional FET Q3. Q4 source
The current flows through the load resistor RL via the drain path, and the constant current source 4
Since the current does not substantially flow, the drop in the AC output amplitude is prevented.

Furthermore, additional FETQ3 in FIG. The connection between the source of Q4 and the differential pair FET QI and the drain of Q2 is made using the additional FET Q3. The low AC impedance seen from the source of Q4 can prevent the formation of a large time constant due to the load resistance RL or the constant current source 4 and the mirror capacitance of the differential pair FETs QI and Q2.

In addition, in FIG. 3, differential pair FETs QI, Q2 and additional FETs Q3. Those skilled in the art will readily understand that Q4 can be replaced with a differential pair bipolar transistor or an additional bipolar transistor, and in this case also a broadband, high gain differential amplifier circuit can be obtained. In this case, it goes without saying that the drain, gate, and source connections of the FET correspond to the collector, base, and emitter connections of the bipolar transistor, respectively.

FIG. 4 shows a comparison of gain-frequency characteristics between the circuit of FIG. 3 according to the present invention and the case where ■□=O in the circuit of FIG. By the way, what are the circuit constants?

FETQI~Q4 gate width is 120μm, IO=1
mA, Ω*I l = O~4 mA in R1-~1
It is. As is clear from the figure, when I, = 0 mA, the gain is 11 dB and the band is 8 GHz, whereas when I, = 4
At mA, the gain is 21 dB and the band is 8 GHz, and it can be seen that a high gain of 1 odB or more can be realized without deteriorating the band.

Next, FIG. 5 shows another embodiment of the present invention in which a constant current source 6 that can control □ by an external control voltage VC in FIG. 3 is added. In this circuit, the control voltage V. By changing the FETQI
, a current of ■1 is sent to the drain of Q2, and Ql
, ■ is the source of Q2. By providing the constant current source circuit 6 having the function of inserting a current of +2I, it is possible to change Xl, that is, to configure a variable gain amplifier in which the gain in equation (5) is made variable.

In the case of the example shown in FIG. 5, a gain variable width of 10 dB can be obtained.

Next, FIG. 6 shows an example of the configuration of the constant current source circuits 3 and 4 in the embodiment of the present invention shown in FIG. In FIG. 6, Q51. Q61. Q71゜Q81. Q91. Q
Constant current source 3 is connected to N-channel FET of IOI, and Q5
0. Q60. Q70゜Q80. Q90. A constant current source 4 is composed of a P-channel FET Q100. Here Q7
0. Q71 is the threshold value "thly", otherwise the threshold value is Vth2t
Or Q50. Q51 has a gate width of 4Wg 1 t Q
91 is gate width 2Wg□, Q101 is gate width Wg
2. Other than that, the gate width is Wg1.

Let the threshold difference between Vthl and Vth2 (7) be Δvth,
By creating an appropriate value and Δv t h, 11
It is possible to create a power supply value of =K(Δvth)2 (6) with the constant current source circuit 4 and a power supply value of I O+ 2 I 1 with the constant current source circuit 3.

Therefore, it is important to manufacture an FET with a larger threshold difference ΔVth in order to achieve high gain.

FIG. 7 shows a configuration example of the constant current source circuit 6 in another embodiment of the present invention shown in FIG. Here Q52. Q52
' , Q62. Q62', Q72 are P channel FEs
T, Q53. Q53', Q63゜Q64. Q73 is N
This is a channel FET. Also, the gate width is 2W for Q63.
g1. Q64 is W8° and all others are Wgl. In this configuration, the control voltage V can be adjusted by designing appropriate RIO to R20 and gate width. 1+VC2 can be adjusted to allow for a gain. In this case, by increasing the ratio of wgl to Wg2,
A variable gain amplifier with a wide variable gain range can be constructed.

Next, the simplest modified configuration example of the embodiment in FIG.
As shown in the figure. When the resistor 7 is inserted as a substitute for the constant current source 4, if the resistance value of the resistor 7 is several hundred ohms or more, almost all of the alternating current flows through the load resistor RL, so it can be regarded as a constant current source. Therefore, it is possible to obtain the effects described in the explanation of FIG. 4 with the simplest configuration.

FIG. 9 shows an embodiment in which the broadband high gain amplifier of the present invention is used to amplify a transmitted optical signal in an optical communication system. In the figure, by taking in an optical input signal 11 from a transmitting station from one end of the optical transmission line 10, an optical output signal 12 transmitted from the other end of the optical transmission line 10 can be taken out. This optical output signal 12 is converted into an electrical signal by a photoelectric conversion means 13.

In this converting means 13, the optical output signal 12 is converted into a current signal by a photodiode Dp.

The anode of the photodiode Dp is a current limiting resistor R100
is connected to the positive power supply voltage vco via.

The cathode of the photodiode Dp is connected to one end of the resistor R101 and the inverting input terminal (-) of the operational amplifier ○PAMP. Non-inverting input terminal (+) of operational amplifier OPAMP
is connected to ground voltage GND.

The output terminal of the operational amplifier OPAMP is connected to the other end of the resistor R101. Thus, resistor R1ot and operational amplifier O
PAMP constitutes a current/voltage conversion means, and converts the current signal of the photodiode Dp into a voltage signal. This voltage signal has a band of about 2.4 GHz and an amplitude of about 5 mV to 500 mV, and is transmitted to the input line Ω1 of the wide band high gain amplifier 14 via the coupling capacitor CLOo. This amplifier 14 includes a front stage amplifier 14a and a rear stage amplifier 1 which are connected in cascade.
4b and the input line Q.
In response to the signal Q2.1, a signal of opposite phase and a signal of the same phase are output to the output line Q2. It will occur in Q3. This output line Q2. The signal of Q3 becomes a differential input signal of the subsequent stage amplifier 14b. This rear-stage amplifier 14b responds to the signal on the output line Q2+Q3 and outputs a voltage signal V OUT having the opposite phase to the signal line a2 and an in-phase signal voU.
T is generated on output line Q4rQ5. The signal Vout and the signal voUT have the same phase and antiphase relationship as the signals of the input line Q1.

In addition, the output line Q4. Q5 has a load resistance of approximately 50 ohms R°C.
is connected. AGC control signal generation circuit 15 for performing automatic gain control is connected to line Q4. In response to the differential voltage across Q5, the gain control signal V A G C10+vAcC11+vx
cC20* Generates VAGC21 - These gain control signals VAGcto-vAcc2t cause the load resistance R to
The voltage gain Gv of amplifier 14 is set so that the voltage amplitude across λ is maintained at approximately 1 volt.

FIG. 10 is a circuit diagram showing the amplifier 14 (front stage amplifier 14a, rear stage amplifier 14b) of FIG. 9 in more detail. This amplifier 14 is composed of a GaAs IC, and the internal FETs QI to Q23 are N-channel GaAsM E
S F E T (MetalS emicondu
ctor F 1eld effect engineer
or ). The front stage amplifier 14a includes a differential pair of FETs QI, Q2 . Additional FETQ3. Q4. Constant current source FETQ5. Source follower FETQ7゜Q8. Constant current source FETQ9. QIO, Source 7 Oro'! FETQI
1. Ql 2. PN)) Transistor Q100. Q
IOI, register shift diodes D1 to D5, resistor R
1 to R11. The base is the gain control signal V A
GC□. PNP transistor Q controlled by
100. QIOI constitutes current bypass means. The gate of constant current source FETQ5 is controlled by gain control signal VACC11.

Source 7 Orota FETQ7. Q8. Qll.

Ql2 is the output line Q2. It operates as an impedance conversion means with high input impedance and low output impedance to improve sleep ability in Q3.

The rear stage amplifier 14b includes a differential pair FETQ13°Ql4, additional FETQ15. Q16. Constant current source FETQ17. Source 7 Oroku FETQ18. Q19, constant current source FETQ20
．． Q21, source filter FETQ22. Q23. P.N.
P transistor Q102. Q103, level shift diodes D6 to D10, and resistors R12 to R14.

P whose base is controlled by gain control signal VAGC20
NP transistor Q102. Similarly, Q103 constitutes current bypass means. The gate of constant current source FETQ17 is controlled by gain control signal vAcant. Source follower + FETQ18. Q19, Q
22. Q23 similarly operates as an impedance conversion means and improves the driving ability of the output lines Q4*Q5.

When the voltage amplitude across the load resistor RJ2 decreases, the AGC
Gain control signal V generated from control signal generation circuit 15
A a C10t V A G C20 decreases and the gain control signal V A G C11* V A G C21 increases. Therefore, PNP transistor Q100-Ql
03 increases, and the current flowing through constant current source FETQ5.03 increases. Q1
The current flowing through 7 also increases. As a result, as is clear from the above description, the voltage gain of the front-stage amplifier 14a and the voltage gain of the rear-stage amplifier 14b increase, and the voltage amplitude across the load resistor J is maintained at a constant value.

According to the embodiment of FIG. 10, the GHz band signal, e.g.
．． It has been confirmed that the optical communication electrical signal in the 4 GHz band is wideband and high gain amplified by the multistage amplifier 14 with a maximum gain of Gvm 8x to 48 dB.

In addition, since the required maximum gains Gv and Tlax can be obtained with a relatively small number of cascaded multistage amplifiers, the cutoff frequency related to the gain from the overall input to the overall output of this multistage amplifier can be increased. This allows the multi-stage amplifier to have a wider band.

On the other hand, prior to the filing of this application, it was discovered that by adding a constant current circuit as a current bypass means to a transistor amplifier circuit using a bipolar transistor as an amplifying element, distortion characteristics could be improved and operation at a low power supply voltage would be possible. Kaisho 49-1
It is known from No. 04549. In this known technology, the transistor operates with base input and emitter common,
The emitter current (bias current) of this transistor is set to a large value, and the base-emitter voltage VBE - emitter current of this transistor is improved.The distortion rate characteristics due to nonlinear characteristics are improved. A constant current circuit is connected in parallel with at least one of the emitter resistor or the collector load resistor, and this constant current circuit bypasses a portion of the large bias current.Therefore, the DC voltage drop across the emitter resistor or the collector load resistor is reduced. Transistor amplifier circuits can operate with relatively low power supply voltages.

As described above, the known technology disclosed in JP-A No. 49-104549 is aimed at improving the distortion characteristics and low power supply voltage operation of a transistor amplifier circuit using a bipolar transistor as an amplifier element, and the present invention is intended to improve the distortion characteristics and operate at a low power supply voltage. This is to be distinguished from the objective of making the underlying amplifier high gain and broadband.

[Effects of the Invention] According to an embodiment of the present invention, a variable gain width can be obtained for the signal current I0. As shown in Figure 4, I□=1mA
In this case, it is possible to increase the gain by three times when 11=4 mA and by five times when 11=12 mA.

Further, by adding a constant current circuit having a current control terminal, a variable gain amplifier can be constructed. Furthermore, in this high gain method, the load resistance RL and the signal current I. Since the gate width of the transistor is not changed, theoretically there is no deterioration of the band due to a change in gain.

Further, since the gain is 3 to 5 times higher than that of the conventional circuit, there is no need to significantly increase the number of cascaded multistage amplifiers, and band deterioration due to multistage cascade can be prevented, so a sufficiently wide band can be expected.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an amplifier circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventionally known amplifier circuit, and FIG. 3 is a circuit diagram of a conventionally known amplifier circuit.
A circuit diagram of an amplifier circuit according to a modified embodiment of the embodiment shown in the figure, FIG. 4 shows the gain-frequency characteristics of the embodiment of FIG. 3,
FIG. 5 is a circuit diagram of a variable gain amplifier circuit according to another embodiment of the present invention, and FIG. 6 is a circuit diagram of a constant current source circuit 3 in the embodiment of FIG.
4 is a circuit diagram specifically showing the constant current source circuit 6 in the embodiment shown in FIG. 5, FIG. 8 is a circuit diagram specifically showing the constant current source circuit 6 in the embodiment shown in FIG. An example circuit diagram, FIG. 9 is a system block diagram of an embodiment using the broadband high gain variable gain multi-stage amplifier of the present invention for amplifying a transmitted optical signal in an optical communication system, and FIG. 10 is an example of the embodiment of FIG. 9. FIG. 2 is a circuit diagram specifically showing a variable gain multi-stage amplifier in the embodiment. 13 Kuni 4th Noji; 艮f-, (HLn 1st 2nd figure! q 田

Claims (1)

[Scope of Claims] 1. (1) A first device whose sources are differentially connected to each other.
FET (Q1) and a second FET; (2) load means connected to the drains of either one of the first FET and the second FET; and (3) the drain of one of the above and the load. 1. A wide-band, high-gain amplifier circuit characterized by comprising: current bypass means for bypassing the load means and flowing a current for increasing the conductance of one of the FETs connected to the load means. 2. The drain of the one FET is connected to the first operating potential point via the load means, and the drain of the one FET is connected to the first operating potential point through the load means, and
2. A wideband, high gain amplifier circuit according to claim 1, wherein said source of the ET is connected to a second operating potential point via common impedance means. 3. The wideband/high frequency converter according to claim 2, wherein the current bypass means is constituted by a first constant current source circuit, and the common impedance means is constituted by a second constant current source circuit. Gain amplification circuit. 4. The first constant current of the first constant current source circuit is variably set by the first gain control signal, and the second constant current of the second constant current source circuit is variably set by the first gain control signal.
4. The broadband high gain amplifier circuit according to claim 3, wherein the constant current is variably set by the second gain control signal. 5, (1) first and second amplification elements whose ground electrodes are connected to each other to operate differentially with respect to the input signal; (2) whose ground electrodes are connected to the first and second amplification elements; (3) first and second additional amplification elements each connected to the output electrode of the amplification element and whose input electrode is connected to a predetermined DC potential point; (3) one end of which is connected to the first and second additional amplification element; (4) first and second load means each connected to an output electrode and having the other end connected to a first operating potential point; (4) the ground electrode and the second load means of the first and second amplification elements;
(5) a common impedance means connected between the output electrode of the first amplification element and the ground electrode of the first additional amplification element; (6) a second current bypass means connected to a common connection node between the output electrode of the second amplification element and the ground electrode of the second additional amplification element; A differential amplifier circuit featuring: 6. Claims characterized in that the first and second current bypass means are constituted by first and second current source circuits, respectively, and the common impedance means is constituted by a third constant current source circuit. The differential amplifier circuit according to item 5. 7. The first constant current of the first constant current source circuit and the second constant current of the first constant current source circuit.
The second constant current of the constant current source circuit is variably set by the first gain control signal, and the third constant current of the third constant current source circuit is set variably by the first gain control signal.
7. The differential amplifier according to claim 6, wherein the differential amplifier is variably set by a gain control signal. 8. A signal at a common connection node between the one end of the first load means and the output electrode of the first additional amplification element is input to the first impedance conversion means of high input impedance and low output impedance, The signal at the common connection node between the one end of the second load means and the output electrode of the second additional amplification element is input to the second impedance conversion means of high input impedance and low output impedance. The differential amplifier circuit according to range 6. 9. The first and second amplification elements and the first and second additional amplification elements are MESFETs in GaAs IC, and the first impedance means is a first source follower MESF.
9. The differential amplifier circuit according to claim 8, wherein the second impedance means includes a second source follower MESFET. 10. (1) an optical transmission line into which an optical input signal is taken in at one end and an optical transmission output signal taken out from the other end, and (2) opto-electrical conversion means for converting the optical transmission output signal into an electrical signal. and (3) a multi-stage amplifier for amplifying the electrical signal, wherein at least one stage of the multi-stage amplifier is formed by a differential amplifier circuit as defined in claim 9. An optical communication system comprising: 11. The optical communication system according to claim 10, wherein the front stage amplifier and the rear stage amplifier of the multistage amplifier are integrated in the GaAs IC.