JPS6331199Y2 - - Google Patents

Description

[Detailed description of the invention] This invention is an FM
This invention relates to an automatic balancing device for telemeters.

In order to more accurately operate telemeters, which are generally used with separate transmitters and receivers, signals from detectors that require equilibration with ambient temperature and atmospheric pressure, such as blood pressure transducers, must be This can be used as a reference when transmitting a DC signal using an FM telemeter or when the transmitter's V/F converter or receiver's F/V converter cannot be sufficiently stable. It is necessary to detect the level and transmit the value in advance.

It is well known in this type of device to first put the transmitter in a reference input state, and then to balance the receiver output to the reference level by manipulation on the receiver side. However, this requires operations on both sides of transmission and reception. Regarding this point, a telemeter can be considered in which the operation is performed only on the transmitting side and automatic balancing is performed at the receiver based on the command signal from the transmitter, but the processing of the command signal for automatic balancing at the receiver is complicated, and the Even after equilibrium has been achieved, readjustment is required when the receiver is turned off and turned on again, and operation becomes difficult, especially when the receiver becomes complex relative to one transmitter, and even more so when there are multiple transmitters. An operation is required each time the transmitter is switched.

The object of the present invention is to provide an automatic balancing device for an FM telemeter in which the automatic balancing operation is independent between the transmitter and receiver so as to eliminate the above-mentioned drawbacks. The problem is solved in such a way that the output frequency of the modulator can be balanced to the reference frequency.

According to the present invention, it is possible to eliminate at least the frequency fluctuation of the transmitter output signal with respect to the reference input signal at the transmitter, and also when there are multiple transmitters or receivers, or when the power of the receiver is turned on again. The problems that occur can also be eliminated.

Next, the present invention will be explained based on the illustrated embodiments.

Figure 1 shows a system equipped with an automatic balancing device according to the present invention.
1 is a block diagram showing the circuit configuration of a transmitter of an FM (frequency modulation) type telemeter. In the figure, 1 is a preamplifier that amplifies the input signal, 2 is an adder that adds the output signal of the preamplifier 1 and the output voltage of the D/A converter 14, and 3 is a V/F converter that functions as a subcarrier FM modulator. 4 is the main carrier
It is an FM modulator.

2, 5 to 14 are added to configure the automatic balancing device according to the present invention, and add voltage to the adder 2 according to the level of the output frequency of the V/F converter 3 with respect to the reference frequency with respect to the reference input signal. increases or decreases, and automatically balances when the output frequency matches the reference frequency. Of these, 5 is an automatic balance operation switch that issues a trigger when operated when adjusting the reference level if necessary, and 6 is set by a trigger from the automatic balance operation switch 5, and Q _x+ of the binary counter 11. Flip-flop (FF) reset by _one stage output,
7 is a delay circuit that delays the output of FF 6 by time _T0 , and 8 is a switch circuit that closes when a gate pulse is supplied from delay circuit 7 and supplies the subcarrier that is the output of V/F converter 3 to binary counter 10. be. Reference numeral 11 denotes a binary counter which receives the output signal of the clock generator 9 using a crystal oscillator, that is, the reference clock, and is reset by the inverted output of the Q _y+1 stage of the binary counter 10. 12 is the gate pulse which is the output of the Qy stage of the binary counter 10 and the binary counter 11
The gate pulse, which is the inverted output of the Qx stage, and this
This is an AND gate that receives as input the correction clock that is the output of the Qz stage. 13 is and gate 12
A binary counter 14 inputs the control clock from the binary counter 13 and is reset by a trigger from the automatic balance operation switch 5. A binary counter 14 converts the digital signal from the binary counter 13 into an analog signal in order to generate an input voltage for feedback to the adder 2. This is a D/A converter that converts

As an example, the frequency of the clock generator 9 is assumed to be 32.768kHz, which is the standard. Then, the QZ stage of the binary counter 11 was set to ²¹ stages, and the frequency was divided into 1/2.
Use the 16.384kHz output as the correction clock. Also
The Q _x+1 stage for resetting the FF6 is ²¹⁴ stages, and its output frequency is divided by ^1/214 to 2Hz.
As will be described later, automatic balancing is achieved when the period of the output signal of _{the Q} Or to set it around 2kHz for low frequency)
Q _y+1 stage is 2 ¹⁰ stages. In other words, the subcarrier frequency for the reference input signal is 2Hz×2 ¹⁰ =
It is configured to be balanced at 2.048Hz.

Next, the operation of the automatic balancing device having the circuit configuration described above will be explained with reference to FIG.

First, a reference input signal is given to the preamplifier 1. When the automatic balance operation switch 5 is pressed to generate a trigger (Fig. 2a, a), the binary counter 13 is reset, the output voltage of the D/A converter 14 becomes the minimum value, and the output frequency of the V/F converter 3 ( subcarrier frequency) to the highest value in the adjustment range. At the same time, the trigger causes the FF6 to be set, and after the delay time _T0 of the delay circuit 7 has elapsed (FIGS. 2a and 2b), the switch circuit 8 is turned on and the subcarrier is applied to the binary counter 10. In the Qy stage of this counter 10 the subcarrier is 1/2 ⁹ (Fig. 2a, d) and in the Q _y+1 stage the subcarrier is 1/2 ¹⁰
(Figures 2a and 2c) and output. On the other hand, the binary counter 11 starts counting as soon as the reset signal from the Qy ₊₁ stage (Fig. 2a, c) becomes "L", and the output of the clock generator 9 from the Qz stage is divided into 1/2. 16.384kHz correction clock (Fig. 2a, f) and 1/2 ¹³ from the Qx stage.
and the reset signal (Fig. 2a, c)
A frequency-divided signal (FIGS. 2a and 2e) terminated at is output. Therefore, the AND gate 12 generates a number of control clocks corresponding to the difference in period between the gate pulse obtained by dividing the subcarrier and the gate pulse obtained by dividing the reference clock so that the period can be compared with this gate pulse. (Fig. 2a, g). This control clock is applied to the binary counter 13 and counted, and converted into a corresponding DC voltage in the D/A converter 14 and supplied to the adder 2. This causes the V/F converter 3 to operate in the direction of lowering the output frequency.

By repeating this operation, the subcarrier gradually approaches the reference frequency, and when the state shown in FIG. 2b is reached, the automatic balancing operation is completed. In other words, the output frequency of the Q _y+1 stage of the binary counter 10 gradually increases to 2Hz.
As it approaches and even exceeds (FIGS. 2b, c and e), the output of the Qx stage is inverted by the reference clock. Therefore, the output of Q _x+1 stage changes to “H”,
Thereafter, it is reset by the output of the Q _y+1 stage (Fig. 2b, h).

FF6 is reset by the output from this Q _x+1 stage, and delayed by time _T0 in delay circuit 7 (second
Figure b, b) The switch circuit 8 is opened and the automatic balancing operation is completed. The binary counter 13 holds the counted contents until the next time it is reset by the automatic balancing operation switch 5. Note that the delay circuit 7 is for completing automatic balancing only when the reference input signal is within the automatic balancing operation range, and resets the binary counter 11 after the binary counter 11 outputs an output from the Q _x+1 stage. The binary counter 10 is used to ensure that the control clock stops.
switch circuit 8 until the Q _y+1 stage generates an output.
It has a function to delay the timing of opening. The delay time T ₀ is determined by the D/A converter 14, adder 2 or V/F that constitutes the feedback loop.
This delay time is set to the minimum within a range that does not fall below the maximum value of the error (the time that the output period of the Qy stage is extended by one control clock), which is set by taking into account the sensitivity or response time of converter 3, etc. T ₀ determines the maximum error of this circuit. In this embodiment, this delay time T ₀ is equal to one correction clock (61 μs).
The auto-equilibration error is 0.05%.

More specifically, the embodiment of the present invention described above has the following functions and effects.

Generally, in order to accurately detect the frequency or period of an input signal for each period using a reference signal, it is necessary to select the frequency of the reference signal to be several thousand times or more higher than that of the input signal. Therefore, in order to detect a 2 kHz subcarrier frequency with an accuracy of, for example, about 5×10 ^-4 as in this embodiment, a reference signal of about 4 MHz is required. Such high-frequency signals are not only difficult to handle and complicate the circuit, but also increase power consumption, so it has not been possible to apply this technology to telemeter transmitters, which require battery operation. It was hot.

However, in the present invention, by frequency-dividing the output (subcarrier) of the V/F converter 3 to be detected using a binary counter, a relatively low frequency reference clock of 32.768 kHz, which is obtained from a crystal oscillator commonly used in watches, is used. Using this, it is possible to detect the frequency or period with the required accuracy, and the assembled telemeter transmitter itself consists of several MOS gates and counters that operate with minute power in addition to the crystal oscillator. For,
It has become possible to meet the requirements of a telemeter transmitter: small size, light weight, and low power consumption.

More importantly, because the subcarrier frequency is divided, even if there is a slight fluctuation in the reference input signal during balancing operation, the reference level averaged within the division time will remain unchanged. can be transmitted as a signal, making measurements using a telemeter more accurate.

In addition, the present invention stores a number of control clocks corresponding to the difference between the output frequency of the V/F converter and the reference frequency in the binary counter 13, and adds the analog voltage of the value to the input of the V/F converter 3. Therefore, the frequency correction during the balancing operation is performed exponentially, achieving a quick balancing operation with a fast rise even though the subcarrier frequency to be detected is divided. It is possible.

In the above embodiment, the reference clock obtained from the clock generator 9 is halved as the correction clock.
However, the correction clock is not necessarily limited to this, and the present invention can be implemented in the same manner even if it is a pulse signal generated from another oscillator.

Furthermore, if the signal from the transmitter shown in Figure 1 is demodulated with high precision and high stability in the receiver and then output, the output signal level of the receiver with respect to the reference input signal will be more accurately and stably balanced to the reference level. It becomes possible to do so. As a receiver for this purpose, it is conceivable to use, for example, a pulse average type frequency discrimination circuit (Utility Model Application No. 53-097361) using a crystal oscillator in the pulse generating section of the demodulator.

As is clear from the above description, by automatically balancing the carrier frequency for the reference input signal to the reference frequency according to the present invention, fluctuations in the reference level caused by fluctuations in the transmitter are avoided. Also, the transmitter and receiver are independent in terms of automatic balancing operation,
There is no need for readjustment even when the power to the receiver is turned on again, and even if there are multiple receivers, setting the transmitter to the standard input state for one of the receivers will not interfere with other receivers. It disappears. Furthermore, even when one receiver selects one of the signals from a plurality of transmitters, there is no need to perform an automatic balancing operation every time the signal is switched. Furthermore, since the circuit is simple and the power consumption is small, it can also be applied to portable transmitters.
Furthermore, by making the receiver highly accurate and highly stable, it is possible to further improve the accuracy and stability of the reference level while maintaining the above-mentioned advantages. Since this method divides the output signal of the V/F converter relative to the reference input signal to match the reference period, it is only necessary to perform automatic balancing operation at the corresponding low frequency, which simplifies the circuit configuration and is advantageous in terms of cost. In addition, even if the reference input signal at the analog stage fluctuates minutely, the averaged reference frequency is output, making highly accurate telemeter measurement possible.

[Brief explanation of the drawing]

Figure 1 shows a system equipped with an automatic balancing device according to the present invention.
The transmitter circuit of the FM telemeter and Figures 2a and 2b show the operating waveforms of each part thereof. 1...Preamplifier, 2...Adder, 3...V/
F converter, 4... Main carrier modulator, 5... Automatic balance operation switch, 6... FF, 7... Delay circuit, 8... Switch circuit, 9... Clock generator, 10, 11, 13... binary counter, 1
2...AND gate, 14...D/A converter.

Claims (1)

[Claims for Utility Model Registration] In an automatic balancing device for an FM telemeter that can match the output signal level of a receiver with respect to a reference input signal of a transmitter to a reference level, an FM modulator of a transmitter is connected to a V/F converter 3. counter means 2, 13, 14 for counting the control clock and adding the counted output to the reference input signal as an analog signal; and a first gate for dividing the output signal of the V/F converter 3. frequency dividing means 10 for generating pulses; frequency dividing means 9 and 11 for dividing the frequency of a reference clock to generate a second gate pulse having a reference time width; and periods of the first and second gate pulses. correction clock generation means 9, 11 which generate a clock having a frequency capable of counting the difference between the clocks; an AND gate means 12 which outputs as the control clock a number of correction clocks corresponding to the difference between the two; and counter means 2, 13, 14 which hold the count output in response to the operation of the automatic balance operation switch 5; and control means 6, 7, and 8 for causing each of the means to perform an automatic balancing operation by resetting the FM.
Automatic balancing device for telemeters.