JPS6331108B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to an improvement in a gated bipolar transistor having a composite structure of a bipolar transistor and a junction field effect transistor.

The gated bipolar transistor (hereinafter abbreviated as "gated BPT") is a semiconductor device that is difficult to cause base punch-through even with a thin base width and low impurity concentration in the base region, and has excellent high voltage and high frequency characteristics. ) has been proposed (IEICE technical research report 78 [109]
(1978-8-25) See P.41-50).

FIG. 1 is a sectional view showing the basic structure of a gated BPT. In FIG. 1, 1 is a collector region of a first conductivity type, 2 is a base region of a second conductivity type that is formed on the first surface of the collector region 1 and has a higher impurity concentration than the collector region 1, and 3 is a base region 2. A first conductivity type emitter region 4 is formed on the surface of the base region 2 and has a higher impurity concentration than the base region 2; A gate region 21 of the second conductivity type is formed in a stripe shape protruding from the base region 2 into the collector region 1 so as to sandwich the main current path between the gate region 2 and the base region 2. _J1 is the base-collector junction formed by base region 2 and collector region 1, _J2 is the emitter-base junction formed by emitter region 3 and base region 2, and _J3 is the gate. The gate-collector junction formed by region 4 and collector region 1, W _B is the width in the main current direction of the main current path of base region 2 (base width), and θ is the J ₁ junction surface and J ₃ junction The tangent to the joint surface of J ₃ at the point of connection with the surface is J ₁
The angle 2a formed with the normal line of the bonding surface is the distance between the gate regions 4.

In gated BPT, before the base region 2 punches through, the depletion layer extending from the gate-collector junction _J3 on both sides comes into contact with the part of the collector region 1 sandwiched between the gate regions 4, and this part becomes pinch-off. By doing so, punch-through is made difficult to occur even in the base region 2 which is thin and has a low impurity concentration.

If the impurity concentration of the base region 2 is N _B , the impurity concentration of the collector region 1 is N _C , the amount of electron charge is q, and the dielectric constant of the semiconductor constituting the semiconductor substrate is ε _S , then the base region 2 punches through. The electric field strength E ₁ at the base-collector junction J ₁ at this time is E ₁ =qN _B /ε _S W _B (1).

Figure 2 shows the extension d of the depletion layer from the base-collector junction J ₁ and the gate-collector junctions J 3 on both sides and the distance between the gate regions ₄ when the collector region 1 sandwiched between the gate regions 4 is pinched off. It is an explanatory diagram for explaining the relationship with a which is 1/2.
In FIG. 2, d is the extension of the depletion layer from the base-collector junction J ₁ and the gate-collector junctions J ₃ on both sides (which are of the same value). α is the angle between the base-collector junction J ₁ and a straight line connecting the intersection of the above three depletion layers and the intersection of the base-collector junction J 1 and one of _the gate-collector junctions J ₃ . As can be easily seen from Figure 2, d=a tan α=a tan1/2(π/2+θ) =a tan(π/4+θ/2)...(2).

Electric field strength at base-collector junction J ₁ at this time
E ₂ is E ₂ =qN _c /ε _s d=qN _c /ε _s {a tan(π/4+θ/2
)} ...(3) becomes.

Therefore, the condition for the collector region 1 sandwiched between the gate regions 4 to be pinched off before the base region 2 punches through is as follows from equations (1) and (3): N _c :{a tanπ/4+θ/ 2)}<N _B W _B ...(4) That is, a<N _B /N _C W _B cot(π/4+θ/2)...(5).

FIG. 3 is a perspective view showing a transistor chip of an example of a gated BPT according to the prior art to which the above basic principle is applied, cut in two orthogonal planes. In FIG. 3, the same reference numerals as in FIG. 1 represent the same components as shown in FIG. Reference numeral 5 indicates an emitter electrode bonded to the emitter region 3 with its peripheral edge remaining, 6 indicates a base electrode bonded to the base region 2, and L _E indicates the emitter width. Collector area 1
Although a collector electrode is bonded to the surface of the electrode, illustration thereof is omitted.

However, in the conventional gated BPT mentioned above, due to its structure, when trying to increase the emitter width L _E , contact between the base electrode and the base region cannot be secured, and thus the emitter width L _E is limited by a. There is. For example, W _B =2μm,
Assuming N _B =10 ¹⁶ cm ^-3 , N _C =10 ¹⁴ cm ^-3 , and θ=0,
a=20μm, and the emitter width L _E must be 40μm or less. Since the emitter electrode 5 is bonded to the emitter region 3 with its peripheral edge remaining, the width of the emitter electrode 5 is even smaller than the emitter width L _E , and in this way, the emitter electrode 5
The width of is also limited by the spacing between gate regions 4,
This makes it difficult to form the emitter electrode 5. Also, the third
In the structure shown in the figure, the width of the emitter electrode 5 cannot be made large enough to be suitable for high power.

By the way, if the emitter region is arranged parallel to the gate region as in the past, the emitter width is limited by the spacing between the gate regions, and the area of the emitter region is also limited. If an emitter electrode is bonded to the emitter region and arranged in a direction perpendicular to the gate region, the width of the emitter electrode is hardly restricted at all, and the area of the emitter electrode can be increased.

Therefore, the present invention provides an emitter electrode and a base electrode so as to be orthogonal to the emitter region in the longitudinal direction, thereby making it possible to increase the width of the emitter electrode without being limited by the spacing between the gate regions. At the same time, a striped emitter region is formed in the form of an island within the base region, and the four sides of this emitter region are connected to the gate region to which the gate electrode is connected, and a low resistance region formed by the intersection of the gate region and the base region. The purpose of this invention is to provide a BPT with a gate that can eliminate the deviation of the emitter electrode by surrounding it with a gate, thereby increasing power consumption.

The present invention will be explained below based on examples.

FIG. 4 is a perspective view showing a transistor chip of an embodiment of the gated BPT according to the present invention, cut along two orthogonal planes. In FIG. 4, the same reference numerals as in FIG. 3 represent the same components as shown in FIG. 3a is a plurality of island-shaped emitter regions arranged in parallel along the longitudinal direction of the gate region 4 and formed in a stripe shape such that the length in the arrangement direction is longer than the length in the direction perpendicular to the arrangement direction; 5;
6a is an emitter electrode disposed perpendicularly to the longitudinal direction of the emitter region 3a and is bonded and electrically insulated from the portion of the base region 2 facing the gate region 4; 6a is a base region between the emitter regions 3a; A base electrode 7 is formed parallel to the emitter electrode 5a so as to be adhered to the emitter electrode 2, and an insulating film 7 electrically insulates the emitter electrode 5a from the surface of the base region 2.

Also in the gated BPT of this embodiment, since the spacing 2a between the gate regions 4 is formed so as to satisfy equation (5), the emitter width of the emitter region 3a is a value limited by a. , since the emitter electrode 5a is orthogonal to the emitter region 3a,
Unlike the emitter electrode 5 of the prior art, in which the emitter electrode 5 is bonded in parallel to the emitter region 3 with its peripheral edge remaining, the width and eventually the area of the emitter electrode 5a can be increased, and the formation of the emitter electrode 5a is easier. It becomes easier. Furthermore, a striped emitter region is formed in the form of an island within the base region, and the four sides of this emitter region are formed by a gate region to which the gate electrode is connected, and a low resistance region formed by the intersection of the gate region and the base region. By enclosing it, it is possible to eliminate unevenness of the emitter current, so the width of the emitter electrode 5a can be formed wide, and a large amount of current can be passed through the emitter electrode 5a, making it possible to increase the power. becomes.

As detailed above, in the gated BPT according to the present invention, the emitter region is formed in an island shape,
Since the emitter electrode and the base electrode are formed perpendicularly to the arrangement direction of the emitter regions, the width of the emitter electrode and As a result, the area can be increased, making it easier to form the emitter electrode, and since the unevenness of the emitter current can be eliminated, a large amount of current can flow through the emitter electrode, making it possible to increase the power. be.

[Brief explanation of the drawing]

Fig. 1 is a sectional view showing the principle structure of a gated BPT, Fig. 2 is an explanatory diagram for deriving a conditional expression for the distance between gate regions, and Fig. 3 is an example of a gated BPT transistor according to the prior art. FIG. 4 is a perspective view showing a transistor chip cut along two orthogonal sides. FIG. In the figure, 1 is a collector region, 2 is a base region, 3 and 3a are emitter regions, 4 is a gate region,
5, 5a are emitter electrodes, 6, 6a are base electrodes, 7 is an insulating film, J ₁ is a base-collector junction (first junction surface), J ₂ is an emitter-base junction (second
_J3 is the gate-collector junction (the third junction surface). Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A collector region of a first conductivity type, a base region of a second conductivity type provided adjacent to this collector region, and a stripe-shaped first conductivity type provided adjacently in an island shape within this base region. an emitter region, provided on both sides of the emitter region along the longitudinal direction, penetrating the base region and deeply within the collector region, and having a lower height than the base region at a portion intersecting the base region; a striped gate region of a second conductivity type forming a resistor region, disposed on the gate region and the base region on both sides of the emitter region along a direction perpendicular to the longitudinal direction of the emitter region; , and a base electrode electrically connected to the gate region and the base region, and an emitter electrode disposed along the direction perpendicular to the longitudinal direction on the emitter region and connected to the emitter region, A semiconductor device characterized in that a collector region sandwiched between the gate regions is pinched off before the base region punches through.