JPS6331090A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent the multi-select of a semiconductor storage device caused by the dispersion of the characteristic of a circuit element and to stabilize actions by setting the NOT OR between the NOT of a decoder output and a selection signal before one cycle as the selection signal in the present cycle. CONSTITUTION:A signal to which the decoder output 3a is inverted in invertors I0-In and the selection signals W0-Wn before one cycle make the NOT OR in NOT OR circuits N0-Nn and by setting the NOT OR as selection signals W0-Wn of the cycle the level of the selection signals in the present cycle keeps a low level till the selection signal before one cycle becomes a low level. So the occurrence of the multi-select state where more than two memories are simultaneously accessed by means of the overlap of selection signals can be prevented. The system like this is efficient only for the storage device which always accesses the address sequentially.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a GaAs field effect transistor.

[Conventional technology]

Since GaAs semiconductors have a mobility several times higher than Si semiconductors, efforts are being made in various places to develop GaAs LSIs with the aim of ultra-high-speed operation that cannot be achieved with Si semiconductors. In particular, GaAs field effect transistors (hereinafter referred to as Ga^
The integration of static semiconductor memory devices using sFET has been remarkable.

FIG. 5 is a block diagram of an example of a conventional semiconductor memory device.

This example includes a memory cell array 8, an X decoder 2a that decodes the address input 1a and outputs a selection signal as a decoder output to the word line 7a, and a switch signal line 5 that decodes the address input 1b and outputs a selection signal to the Ya selection switch 6. The Y decoder 2b selects the bit line 7b by sending a selection signal of the decoder output through the Y decoder 2b.

The operation of this example is that the X decoder 2a that decodes the address input 1a sets one of the word lines 7a to a high level and turns on the transmission gate connected to the selected word line 7a. The information of each memory cell is transmitted to each bit line 7b, and the Y selection of the bit line 7b is performed by selecting only one switch signal line connected to the Ym selection switch 6 by the Y decoder 2b that decodes the address 1b. It is carried out by

FIG. 6 is a time-decoder output characteristic diagram of an example of a conventional semiconductor memory device.

This shows a transient state when the signal between the decoder output X,' of the i-th cycle of the X decoder 2a and the decoder output X1+1' of the next i+1-th cycle is switched, and is a selection signal. The timing is designed so that multi-select, in which two or more memory cells are simultaneously accessed, does not occur due to overlapping decoder outputs.

Although only the timing of the decoder output of the X decoder 2a is shown here, the same applies of course to the Y decoder 2b.

[Problem that the invention seeks to solve]

However, when GaAs FETs are used as circuit elements in the conventional semiconductor memory devices mentioned above, it is currently very difficult to uniformly control the performance of GaAs FETs, so The performance of the connected decoder circuit part is i+
GaAs in the decoder section connected to the first word line
If the performance is lower than that of the FET, there is a drawback that a multi-select state can easily occur in which two or more word line outputs are at a high level at the same time.

SUMMARY OF THE INVENTION An object of the present invention is to prevent a multi-select state in a static type semiconductor memory device, in particular in which addresses are always accessed sequentially, and to ensure stable operation.

[Means for solving problems]

The semiconductor memory device of the present invention includes a decoder that decodes an address signal, a plurality of memory cells that are sequentially accessed by a selection signal, and a selection signal that performs the NOR of the negation of the decoder output and the selection signal one cycle before. The multi-select prevention circuit outputs the signal as a signal.

[Effect]

In the semiconductor memory device according to the present invention, a signal obtained by inverting the decoder output by an inverter and a selection signal from one cycle before are NOR'd by a NOR (hereinafter referred to as NOR) circuit, and this is NOR'd by a NOR circuit for the current cycle. By using it as a selection signal, the level of the selection signal of the current cycle is maintained at a low level until the selection signal of one cycle before becomes a low level.

Therefore, it is possible to prevent the occurrence of a multi-select state in which two or more memory cells are accessed at the same time due to the overlap of selection signals.

Such a method is effective only in a storage device in which addresses are always accessed sequentially.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In this embodiment, multi-select prevention circuits 4a and 4b are inserted between the X decoder 2a and the memory cell array 8 and between the Y decoder 2b and the Ym selection switch 6, respectively.
An address selection signal is outputted via multi-select prevention circuits 4a and 4b.

FIG. 2 is a detailed block diagram of the multi-select prevention circuit of FIG. 1.

This detailed block diagram shows a multi-select prevention circuit 4a for the output of the X decoder. Here, the respective decoder outputs Xo to Xn of the X decoder 2a are input to a multi-select prevention circuit 4a, and the signals are inverted by inverters 0 to I0, respectively, and input to one of the inputs of the NOROR circuit section N. N.

R circuit section. The other input of ~N is the output of the NOROR circuit section No~N n -1 one cycle before each,
That is, the selection signals W, . . . , Wo to W, to 1 are input.

Therefore, the selection signals Wo to Wn can be expressed as logical expressions: becomes.

3 and 4 are a time-decoder output characteristic diagram and a time-selection signal characteristic diagram, respectively, of an embodiment of the present invention.

As shown in Figure 3, the X decoder output differs between the i-th cycle and i+1 due to factors such as variations in the characteristics of circuit elements.
When the second cycle overlaps, there is a period in which the level is high at the same time.

However, this decoder output is
If the selection signal is output as a selection signal through a, as shown in FIG. 4, the i+1th selection signal will not go high until the i-th selection signal goes low, according to the logical formula (1).

As a result, two or more selection signals do not become high level at the same time, making it possible to avoid a multi-select state.

In this embodiment, only the multi-select prevention circuit on the X-decoder side is explained, but the multi-select prevention circuit on the Y-decoder side may also operate differently, although the number of decoder outputs and selection signals may differ. The same is true for both.

〔Effect of the invention〕

As explained above, the present invention provides a static semiconductor memory device in which addresses are always accessed sequentially, by using the NOR of the decoder output and the selection signal of one cycle before as the selection signal of the current cycle. This has the effect of preventing multi-select of the semiconductor memory device due to variations in the characteristics of the circuit elements, thereby stabilizing the operation, and also preventing a decrease in manufacturing yield due to variations in the circuit elements.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
Detailed block diagram of the prevention circuit, Part 3
4 and 4 are respectively a time-decoder output characteristic diagram and a time-selection signal characteristic diagram of an embodiment of the present invention, FIG. 5 is a block diagram of an example of a conventional semiconductor memory device, and FIG. 6 is a diagram of a conventional semiconductor memory device. FIG. 3 is a time-decoder output characteristic diagram of an example of a storage device. Ia, lb...address input, 2a...X decoder, 2b...Y decoder, 3a, 3b...decoder output, 4a, 4b...multi-select prevention circuit, 5...
・Switch signal line, 6...Y selection switch, 7a...
・Word line, 7b...Bit line, 8...Memory cell array, ■o~I0...Inverter, N, ~N0...
・NOR circuit, Wo~Wn, -・Selection signal, X, ~X
,. x, ', X1+1'...Decoder output. Agent Patent Attorney Oto Uchihara J$ l Figure In ~7? −: AntN−q, Nshiy ~N
tt 2MIIR'm, ;i nin to -. Wo ~ 8: Sacrilege, Xθ~X Tsujigo side y Hokuryoku. Tei 2 Figure #73 Times $ 4 Father-in-law

Claims (1)

[Claims] a decoder that decodes an address signal, a plurality of memory cells that are sequentially accessed by a selection signal, and a multi-select prevention circuit that outputs the NOR of the negation of the decoder output and the selection signal from one cycle before as the selection signal. A semiconductor memory device comprising: