JPH0376095A - Memory for logic circuit - Google Patents

Abstract

PURPOSE:To easily form a wiring for forming a logic circuit by providing one piece of bit line through a switching element between adjacent memory cells, and transferring through a word line a signal for instructing which of the adjacent memory cells is to be connected to the bit line. CONSTITUTION:Bit lines 30A - 30C for transferring a signal from each cell 12A, 12B are provided through path transistors 18A, 18B between memory cells 12A, 12B being adjacent in the row direction, and the bit lines 30A - 30C are held in common by each adjacent memory cell 12A, 12B.... Also, the bit lines 30A, 30B,... are connected to each memory cell 12A, 12B by a connection command signal passing through word lines 32A, 32B, 33A and 33B to the path transistors 18A, 18B. In such a way, the density of the wiring is reduced, and the wiring to a logic circuit can be facilitated.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a logic circuit memory suitable for application to a semiconductor device having a static type memory (SRAM). [Conventional technology]

2. Description of the Related Art Conventionally, some semiconductor devices have a memory section on a chip comprised of memory cells 12 made up of a combination of inverters 10 as shown in FIG. When transmitting read and write signals to each memory cell 12 in FIG.
B is connected to the memory cell 12 via the pass transistor 18. Here, the pass transistor 18 is turned on by a row designation signal input via the word line 2OA, 20B, . . . for each row, and connects only the memory cells 12 in the row to the bit line. Further, the selector switch circuit 2 determines which memory cell 12 is read from in the column direction.
It is selected by the selector signal input to 2. Therefore, only the memory cell 12 at the address specified by the row designation signal and the selector signal is connected to the output circuit 23, and the information of the memory cell 12 is amplified by the amplifier 24 and output. The bit line is usually made of aluminum. On the other hand, the word line is usually formed not from aluminum but from polysilicon (or polysilicide).

[Problems to be Solved by the Invention] When a memory cell as described above is to be incorporated into a logic circuit on a semiconductor chip, it is necessary to provide logic circuit wiring made of aluminum in addition to the bit line. However, since two bit lines are formed for each memory cell, the wiring tends to become dense in the column direction, and since each bit line is made of aluminum, it becomes difficult for logic circuit wiring to pass through. However, there arises a problem in that the degree of freedom of wiring and the degree of integration are limited. The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a memory for logic circuits that can reduce the density of wiring to memory cells and facilitate wiring with logic circuits. Take it as a challenge. [Means for Accomplishing the Object] The present invention provides a logic circuit memory in which read and write signals are transmitted to memory cells via two bit lines, in which a switching element is provided between adjacent memory cells. a bit line for transmitting a signal of each cell, and a word line for transmitting a signal instructing which of the adjacent memory cells the bit line is connected to, to the switching element; The above-mentioned vR problem is achieved by providing the following.

[Function J] The present invention provides memory for logic circuits with one bit line between adjacent memory cells via a switching element, whereas conventionally two bit lines were provided for each cell. A signal indicating whether to connect one of the adjacent memory cells to a bit line is transmitted via a word line, and a switching element connects the bit line to the memory cell in accordance with the signal. Therefore, since adjacent memory cells have one common bit line, the number of bit lines can be reduced to one-half times the number of bit lines added to the number of bit lines provided for each memory cell. Therefore, since the density of wiring is reduced, wiring for forming a logic circuit can be easily formed, and the degree of freedom and integration of wiring can be improved. Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. This embodiment is a logic circuit memory provided on a semiconductor chip as shown in FIG. Although FIG. 1 shows some memory cells 12A and 12B of this memory, a large number of these cells 12A and 12B are lined up in this memory. As shown in FIG. 1, in this logic circuit memory, the data from each cell 12A, 12B is connected between memory cells 12A, 12B adjacent in the column direction via pass transistors (corresponding to switching elements) 18A, 18B. Bit lines 30A, 30B, and 30C are provided for transmitting signals. That is, the bit lines 30A, 308, 300 are shared by adjacent memory cells 12A, 12B, . . . . These bit lines 30A, 30B, 30C... are connected to word lines 32A132B to pass transistors 18A and 18B.
, 33A, 33B to each memory cell 12A, 12B by a connection command signal. The bit lines 30A and 30B can be formed, for example, in a second wiring layer of aluminum, and wiring of a logic circuit can be provided in this layer. Also, two word lines 32A, 32B, 33A, 33B, etc. are provided for each row, which increases the number of word lines compared to the conventional one. Therefore, the density of the aluminum wiring layer is not affected. Selector circuits 34A, 34B are provided on the output sides of the bit lines 30A, 130B, 30C, and read signals outputted via the selector circuits 34A, 34B are amplified by an amplifier 24. . A matching circuit 36 is provided on the output side of the amplifier 24 to match the polarity of the read signal. This matching circuit 36 is designed to match each output signal because the polarity of the signals output from the memory cells 12A and 12B is reversed between the adjacent memory cells 12A and 12B, causing an address inversion. That is. The rest of the configuration is the same as that of the logic circuit memory shown in FIG. 2, so similar parts are given the same numbers and their explanations will be omitted. In the logic circuit memory of the embodiment, memory cell 12A
When selecting the bit line 30A, a connection command signal is input to the pass transistor 18A via the word line 32A, and the bit line 30A is selected.
, 30B are connected to the memory cell 12A. Next, a selection signal is input to the selector circuit 34A to select the bit lines 308,
300 is connected to the output line 35 and amplified by the amplifier 24. Also, at the same time as selecting the selector circuit 34A, the matching circuit 3
A selection signal is also input to 6 to select the inverter 36A side and invert the polarity of the read signal. On the other hand, when reading data from the adjacent memory cell 12B, the pass transistor 18B is connected via the word line 32B.
A connection command signal is input to the pass transistor 18B, and the memory cell 12B is connected to the bit lines 30B and 3.
Connect to 0C. Next, the selector circuit is switched to the 34B side, and the bit lines 30A and 30B are connected to the output line 35. At the same time, the matching circuit 36 turns on the 36B side and outputs the amplified read signal as it is without inverting it. In this way, signals read from adjacent memory cells 12A and 12B are matched, and address inversion can be prevented.

【Effect of the invention】

As described above, according to the present invention, the number of bit lines of a logic circuit memory can be reduced, the density of aluminum wiring can be lowered, and wiring for forming a logic circuit can be easily formed. Therefore, the advantageous effect of improving the degree of freedom of wiring and the degree of integration can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a configuration example of a logic circuit memory according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a configuration example of a conventional logic circuit memory. 10... Inverter, 12A, 12B... Memory cell, 18A, 18B... Pass transistor, 30A, 30
8,300...Bit line, 32A1328133A,
33B...Word line. Figure 1

Claims (1)

[Claims] (1) In a logic circuit memory in which read and write signals are transmitted to memory cells via two bit lines, signals of each cell are transmitted between adjacent memory cells via switching elements. A logic device comprising: a bit line for transmitting a signal; and a word line for transmitting a signal instructing which of the adjacent memory cells the bit line is connected to the switching element. Circuit memory.