JPS6330780B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a non-contact testing or diagnosis method using a semiconductor device in which a plurality of marks for position detection are regularly arranged on a chip.

As integrated circuit technology advances, the scale of integrated circuits is shifting from LSI to VLSI, but the testability of these circuits is becoming increasingly difficult. For this reason, non-contact testing and diagnosis have recently begun to be performed. Currently, non-contact testing and diagnosis are performed by enlarging a portion of the chip, rather than covering the entire surface of the IC chip at once. Therefore, when moving from one part to the next, one must check each part against the IC pattern diagram.

In order to eliminate this inconvenience, the present invention provides a non-contact testing method using a semiconductor device in which position detection marks are regularly arranged on an IC chip.

Examples thereof will be described below with reference to the drawings.

FIG. 1 shows an example of grid-like intersections as one example of regularly arranging the symbols of the present invention on an IC chip. In the figure, "1" is the semiconductor substrate, "2" is the bonding pad, "3" is the shaded area is the internal circuit, and "4" is the small circle mark at the intersection of the grid, and this is the position detection mark. Place.

Figure 2 is an enlarged view of a portion of the IC chip in Figure 1. This figure shows that the alphanumeric symbol "8" is placed at the grid intersection position "4" in FIG. In the figure, ``5'' is a semiconductor substrate, ``6'' is a bonding pad, and ``7'' is an internal circuit portion.

Similar to FIG. 2, FIG. 3 is an enlarged view of a portion of the IC chip in FIG. The difference from FIG. 2 is that the position detection marks in FIG. 2 are alphanumeric characters, but in FIG. 3, geometric patterns "12" are arranged at grid intersections. The shapes of the marks placed at grid intersections may be such that their positions can be easily detected during non-contact testing or diagnosis. In the figure, ``9'' indicates a semiconductor substrate, ``10'' indicates a bonding pad, and ``11'' indicates an internal circuit section.

Figure 4 shows potential measurement using an electron beam probe, which is one of the non-contact testing methods.
A portion of the IC chip under test is shown enlarged and projected on a CRT. The image projected on the CRT is an enlarged portion of the IC chip shown in Figure 2. “13” in the diagram is the test equipment.
It shows a CRT, and "14" shows a part of the IC chip displayed on the screen.

FIG. 5 shows a further enlarged view of the CRT screen shown in FIG. This screen only shows the letter "B" as a grid intersection mark, but since this single mark has directionality, this is sufficient to determine which part of the chip it is on. In other words, if there is even one position detection mark anywhere on the CRT screen or in the test or diagnosis field, recognition is possible. "15" in the figure indicates the CRT of the test device, "16"
shows an enlarged view of a portion of the IC chip displayed on the screen.

FIG. 6 shows an example of the shape of the position detection mark. This number mark "17" is formed simultaneously with the same material when forming the metal wiring. Width is 5μ
The size (length) is about 30 μm square and 1 μm thick.If this is scanned with an electron beam, the data necessary for position detection can be obtained.

Similarly to FIG. 6, FIGS. 7a and 7b also show examples of the shape of the position detection mark. This geometric mark is formed by etching a semiconductor substrate to form a groove, and the minimum line width and minimum interval thereof are 2 μm, and the etching depth is approximately 1 μm.
By scanning this with an electron beam, the data necessary for position detection can be obtained. "18, 21" in the figure indicates the semiconductor substrate, "19, 20, 22, 23"
indicates a groove. In addition to the methods shown in FIGS. 6 and 7, there is a method of simultaneously forming polycrystalline silicon and the like.

In FIG. 8, the position detection marks are arranged in a diamond shape. The mark arrangement is grid, diamond, triangle,
Any arrangement shape is possible as long as it is regular, such as an X-shape. “24” in the diagram
indicates a semiconductor substrate, and "25" indicates the arrangement of position detection marks.

The following effects can be considered as the effects of the present invention as described above.

(1) Regularly arranging position detection marks makes it easier to confirm non-contact testing and diagnosis on a CRT.

(2) Position detection marks make it easier to organize test and diagnostic data using image processing.

(3) There are many types of placement shapes for position detection marks, from which one can be selected according to the IC pattern.

[Brief explanation of the drawing]

Figure 1 shows grid intersections at which position detection marks are placed on a semiconductor substrate, Figure 2 shows a portion of an IC chip where alphanumeric position detection marks are placed, and Figure 3 shows a portion of an IC chip where geometric position detection marks are placed. Part of the IC chip, Figure 4 shows a part of the IC chip with the position detection mark projected on the CRT, Figure 5 shows the part of the IC chip with the position detection mark projected on the CRT.
A part of the IC chip, which is a further enlargement of a part of the diagram.
Figure 6 is a plan view of an example of a number mark, Figure 7a,
b is a plan view and a cross-sectional view of an example of a geometric mark;
FIG. 8 is a schematic diagram showing how position detection marks on a semiconductor substrate are arranged on rhombic intersections. In the figure, 1... semiconductor substrate, 2... bonding pad, 3... internal circuit part, 4...
Grid intersection position, 5... Semiconductor substrate, 6... Bonding pad, 7... Internal circuit portion, 8... Alphanumeric position detection mark, 9... Semiconductor substrate, 10
... Bonding pad, 11 ... Internal circuit part, 12 ... Geometric position detection mark, 13 ...
CRT of electron beam tester, 14... Partial enlarged image of IC chip, 15... Electron beam tester
CRT, 16... Partially enlarged image of IC chip, 17
... Numerical position detection mark, 19, 20 ... Geometric position detection mark (groove), 22, 23 ... Cross section of geometric position detection mark (groove), 21 ... Semiconductor substrate, 24 ... Semiconductor substrate, 25 . . . rhombic intersection position for position detection mark placement.

Claims (1)

[Claims] 1 Over almost the entire area on a semiconductor chip,
After forming a semiconductor chip in which a large number of position detection marks with different shapes are regularly scattered and arranged, the position of a predetermined portion of the semiconductor chip to be subjected to a non-contact test is determined by determining the shape of the position detection marks near the predetermined portion. 1. A non-contact testing method for a semiconductor device, characterized by recognizing the semiconductor device.