JPS63305549A - Complementary type mis semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a complementary type MIS semiconductor integrated circuit having high resistance to the total dose of radiation and being proper to improvement in yield by forming a high-concentration impurity diffusion layer without using shield plate isolation in an unnecessary region in inter-element isolation. CONSTITUTION:A high-concentration impurity diffusion layer is used as a region requiring no shield plate isolation for increasing radiation resistance. An epitaxial P-type silicon layer 24 is shaped onto a P-type high concentration substrate 23, and an N well 32 is formed into the layer 24. A gate electrode 25 for an NMOS, a source or a drain 33 in the NMOS, a gate electrode 26 for a PMOS, source-drain 34 in the PMOS, and a shield plate electrode 27 in a P-type region are shaped. A thin oxide film 29 and an inter-layer insulating film 35 are also formed. Accordingly, resistance to the total dose of radiation is increased, and a complementary type MIS semiconductor integrated circuit proper to improvement in the degree of integration and in yield is acquired.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is directed to a highly radiation-resistant complementary MIS (M@tal
-In5ulator -Sem1condueto
, r) Concerning semiconductor integrated circuits.

[Prior Art] Conventionally, in radiation-resistant semiconductor integrated circuits, in order to increase the total dose tolerance of the field isolation region, shield plate isolation (patent application 1986-1), in which the field oxide film is thinned, has been used.
'87632, Japanese Patent Application No. 60-131920, Japanese Patent Application No. 60-175797) and a multilayer field oxide film have been proposed. The former is structurally MOS)? Because it is a transistor, it is easier to design the amount of threshold voltage fluctuation due to radiation irradiation than the latter, and it has the advantage of not requiring a special manufacturing process. 1 indicates high concentration S
The i-substrate 2 is an engineered taxial silicon layer. 3 is a thermal oxide film, 4.5 is a dirt electrode, 6 and 7 are shield plate electrodes, 8 and 9 are source or drain, 10 is a guard band (also called guard ring), 1 is an n-well, 1
2 and 13 are power supplies for the shielding grating 6 and the shielding plate 7. When 1 and 2 are p-type and 11 is n-type, transistor 14 is NHO2,) transistor 15 is P-type.
It is MO8. When 1゜2 is n-type and 11 is p-type, transistor 14 is PMO3,) transistor 15 is NHO2
becomes. Since the oxide films 16 and 17 under the shield grate electrodes 6 and 7 are thin, isolation between elements with high radiation resistance is achieved. Note that when the oxide film is thick, more charged electrons are generated and accumulated in the oxidation layer due to radiation irradiation, and the breakdown voltage deteriorates. Furthermore, since the same power source is connected to the guard punt 10 and the a-el 11, latch-up is prevented by the guard punt 10 and the high concentration 81 substrate IVC. High total dose resistance, high 2
However, this structure has the following drawbacks. In the configuration of FIG. 3, the area of the regions indicated by (1) and (2) becomes extremely large within the LSI chip. In addition to areas necessary for isolation between elements, some of these areas are also used as wiring areas. A fallen oxide film having a large area as described above is susceptible to dielectric breakdown in a process that generates charge-up, such as a plasma dry etching process in an LSI manufacturing process. For example, as shown in FIG. 4, as the dirt area S of the MOS capacitor increases, M
The yield ratio of OS capacitors often tends to decrease, especially for KMOS capacitors? -) When the area becomes larger than Xam, the yield of MOS capacitors tends to decrease due to dielectric breakdown. In the structure shown in FIG. 3, since the area of the shield plate electrode 6.1 is large, dielectric breakdown of the thin oxide film under the shield plate electrodes 6, 7 is likely to occur.
Even if the power source 12 is set to the same potential as the epitaxial silicon layer 2, the above dielectric breakdown will occur on the shield plate electrode 6.1.
If this occurs at the end of the circuit, there is a problem in that the yield of LSI decreases.

Fig. 5 shows another conventional example using a shield plate, where 18 is a p-substrate, 19 is a thick oxide film for element isolation, and 20
is an r-) electrode, 21 is a shield plate electrode, and 22 is a source or drain.

In this case, since the area of the shield plate electrode 21 is small, there is an advantage that dielectric breakdown of the thin oxide film under the shield plate electrode 21 is less likely to occur.

In addition, a shield grate electrode 21 is provided at the end of the element isolation region.
Since a thick oxide film is used in most of the isolation regions between elements, stray capacitance is small and it is suitable for increasing the speed of LSI. However, in this structure, N
Since the shield grate electrode 21 is provided around the source or drain of the channel transistor, and a thick field oxide film is provided around its outer periphery, there is sufficient margin for alignment between the shield grate electrode 2 and the edge of the thick oxide film. As a result, the area indicated by (■) is large, and the element integration density of LI9I is greatly reduced compared to the structure shown in FIG. 3, which is a drawback.

[Problems to be Solved by the Invention] The present invention has been made in view of the above circumstances, and provides a complementary MIS integrated circuit with a shield plate separation structure suitable for improving the total dose resistance against radiation and increasing the integration of elements. It is an object of the present invention to provide a complementary fiMr8 semiconductor integrated circuit in which the shield plate electrode is reduced as much as possible and the problem of charge-up during processing is reduced.

[Means and effects for solving the problem] In order to improve the yield rate of cooled grating isolation, the present invention provides shield plate isolation in unnecessary areas such as those used only for wiring areas among element isolations. By providing a high-concentration impurity diffusion layer region without using the
The present invention provides an S semiconductor integrated circuit.

[Example code] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram illustrating a first embodiment of the present invention for a complementary MIS semiconductor integrated circuit in which a p-type substrate Kn well is formed. Highly doped impurity diffusion layers are used in areas that do not require shielding grating separation to improve radiation tolerance. Epitaxial p on the p highest concentration substrate 23
It has a type Cricon layer 24, and has an n-well 32 in 24.

25 is the NMO8Or-) electrode, 33 is the source or drain of NMO8, 26 is the r-) electrode of PMO8, 3I is the source/drain of PMO8, j7 is the shield plate electrode of the pm region, which is reversed to the region below the electrode Prevent layers from forming. Reference numeral 28 denotes a shielding grate electrode in the N-well region, which prevents the formation of an inversion layer in the region (2) below the electrode. 36 is a guard band for preventing latch-ag. The feature of the structure shown in FIG. 1 is that in order to reduce the area of the shield plate electrodes in regions ① and ② in FIG. It is. The high concentration impurity diffusion layer region 30 has the same type of impurity as the epitaxial silicon layer 24, and the high concentration impurity diffusion layer region 31 overlapping the well 32 has the same type of impurity as the well 32. With this structure, the shield plate can be installed only in areas where element isolation is required, so the area of the shield plate in the LSI chip can be significantly reduced compared to the configuration shown in FIG. Therefore, FIG. 1 provides an 0MO8 structure suitable for improving the yield of L1 as well as FIG. 3.

In Figure 1, 29 is a thin oxide film, 35 is an interlayer insulating film, and Jl
, 3g is a power supply. Although the first embodiment shows the structure of a pm substrate and an h-well, it is clear that the present invention can also be applied to a case where a p-well is used as an n-type substrate.

Further, the first region included in the element isolation region has a shield plate isolation made of an MIS structure, and the semiconductor in the second region excluding the first region and the end region of the well from the element isolation region. In a complementary MIS semiconductor integrated circuit in which a high-concentration impurity diffusion layer region having the same conductivity type as the semiconductor substrate is provided on the substrate surface, when an n-type well is used, the difference between the n-well and the p-type region is A high concentration diffusion layer region of n-type impurity is provided at the boundary, and when a p-deaf well is used, a high concentration diffusion layer region of p-type impurity is provided at the boundary between the pm well and the ni region. It is possible to have a region where the region overlaps the well.

Figure 2 shows the ratteag prevention guard band 36 used in Figure pJ1. 6D is a structure in which trench isolation is used to prevent chiar lag, and trench isolation is provided at the boundary between the p-type region and the nfi region. Reference numeral 52 denotes a buried film such as a CVD 5i02 film, /1Jsl or PSG film buried in the groove of trench isolation, and 53 is a thin oxide film in direct contact with the epitaxial silicon layer 40 and the high concentration substrate 39. be. In Figure 2, 4 is an n-well, 42 is a thin oxide film, and 43 and 44 are f
f-) electrode, 45.46 is source or drain, 41
．． 48 is a shield grating electrode, 49, 50.51 is a high concentration impurity diffusion layer region, 54 is an insulating film between the eyebrows, 55° 56
is powered on.

[Effects of the Invention] As explained above, in the present invention, shielding grade separation for improving the total dose resistance of radiation is provided only in regions where element isolation by shield plates is required, and high concentration impurity diffusion is provided in other regions. Since the layer separation structure reduces the area of the shield grate electrode and improves the insulation yield of the shield grate (shield grate) MOS capacitor, it is a complementary type suitable for high integration and high yield. A MIS semiconductor integrated circuit is provided. In addition, in LSI chips, the wiring formation area and areas around the chip where no elements are placed often occupy a small area in terms of area, so when the structure of the present invention is applied to L8IK, the step of L81 is A great effect can be obtained in improving the inside of the tb.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram showing a first embodiment in which shield plate separation, high concentration impurity diffusion layer separation, and guard band of the present invention are used in combination. Fig. 2 is a block diagram showing the shield plate separation and high concentration impurity diffusion layer separation of the present invention. , a configuration diagram showing a second embodiment using groove separation, and Fig. 3 is a 0MO8 using conventional shield plate separation.
A block diagram showing the structure, Figure 4 shows the dirt surface 8tS of the MO8 capacitor and the yield sheet Y.
FIG. 5 is a configuration diagram showing a MOS transistor using both conventional shield plate isolation and a thick element isolation oxide film. 1-Efi concentration Sl substrate, 2... epitaxial silicon layer, 3... thermal oxide film, 4, 5... dirt electrode,
6゜7.--Shield grade electrode, 8,9.. Source or drain, 10..Gart band, 11..
・Well, 12.13...Power supply, 14...Transistor, 15...Transistor, 16.17...Thermal oxide film, 18.-P substrate, 19...Thick oxide film, 20.
-4"-) Electrode, 21... Shield plate electrode, 2
2...source or drain, 23--high concentration substrate,
j 4-...Top pitaxial silicon layer, 25.26
... Dirt electrode, 27.28 - Shield great electrode, 29... Thin oxide film, 30.31... High concentration impurity diffusion layer region, 32 - N well, 3:9, 34...
- Source or drain, 35... Insulating film between eyebrows, 36
...Gart band, J7, 38-...Power supply, 39
-High concentration substrate, 40...Epitaxial silicon layer, 41...-rs':) L, 42...Thin oxide film, 43.44...Dirt electrode, 45°46...Source or drain , 47.48... Shield plate electrode, 49, 60.51... High concentration impurity diffusion layer region, 52... Trench buried film, 53... Thin oxide film, 5
4... Interlayer insulating film, 55, 56... Power supply.

Claims (3)

[Claims] (1) A shield plate isolation consisting of an MIS structure is provided in a first region included in the element isolation region, and a semiconductor substrate is provided on the surface of the semiconductor substrate in a second region excluding the first region from the element isolation region. A complementary MIS semiconductor integrated circuit characterized by providing highly concentrated impurity diffusion layer regions having the same conductivity type. (2) Complementary MIS according to claim 1, characterized in that a groove isolation is provided at the boundary between the p-type region and the n-type region.
Semiconductor integrated circuit. (3) The first region included in the element isolation region has a shield plate isolation made of an MIS structure, and the second region excluding the first region and the end region of the well from the element isolation region. In a complementary MIS semiconductor integrated circuit in which a high-concentration impurity diffusion layer region having the same conductivity type as the semiconductor substrate is provided on the surface of the semiconductor substrate, if an n-type well is used, the boundary between the n-type well and the p-type region is If a p-type well is used, a high-concentration diffusion layer region of p-type impurity is provided at the boundary between the p-type well and the n-type region. A complementary MIS semiconductor integrated circuit characterized by having a region overlapping with a well.