JPS63305390A - Driving of active matrix type liquid crystal display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention solves a conventional problem in an active matrix liquid crystal display device that causes display brightness unevenness depending on the display brightness mode of other liquid crystal cells when not selected. Therefore, the data 1lli pressure is set in a ramp shape or a shape that has a phase according to the display brightness level within one gate line selection period and has an equal effective value in all gate line selection periods regardless of the display brightness level. By driving with a stepped voltage, the display brightness can be made uniform regardless of the display brightness mode of other liquid crystal cells when not selected, and brightness unevenness can be prevented.

[Industrial application field]

The present invention selects the data line voltage applied to the data lines arranged in the horizontal direction by the gate line voltage applied to the gate lines arranged in the vertical direction, and selects the thin film transistor (hereinafter referred to as TPT) at the selected intersection. ) The present invention relates to a method for driving an active matrix liquid crystal display device that displays a screen by turning on a cell ( ) and applying a voltage to a liquid crystal cell.

In such a display device, the data line voltage shown in FIG. 7 (Δ) is selected by the gate line voltage (only one gate line is shown in the figure) to turn on the TFTl shown in FIG.
Even when TI is off and not selected, the liquid crystal capacitor ff1CLC shown in the equivalent circuit diagram of FIG. (determined by the effective value of the cell voltage),
Due to the TFTI's drain-source tomb, the liquid crystal cell voltage VLC fluctuates depending on the display brightness mode (data lit voltage Vo) of other liquid crystal cells when not selected, and the display brightness changes. Therefore, there is a need for a driving method that can display with uniform brightness without being affected by the display brightness of other liquid crystal cells when not selected.

[Conventional technology]

For example, a certain liquid crystal cell connected to the gate line in the first row is displayed at a brightness between 11 between white display and black display, and a liquid crystal cell connected to the gate line in the second row and below is displayed, for example. When displaying white (ON display) and black display (OFF display), as shown in FIG.
N, -VON) and black display voltage (+VOFF, -V
The data line voltage for the gate line voltage below the 21st) is set to the white display voltage (10 VoN, -VON).
> and black display voltage (+VOFF, -VOFF). In this case, for a certain liquid crystal cell connected to the gate line of the first row, →-VON and 10VO during the selection period.
Intermediate data line voltage between FF and -VON and -VOFF
A data line voltage intermediate between
10 VON during the display period of the liquid crystal cell connected to the gate line below the row.

Data line voltages -VON, +VOFF, and -VOFF are applied.

Therefore, the voltage shown in FIG. 10(B) is applied to a certain liquid crystal cell connected to the gate line in the first row, and the display is displayed at intermediate brightness. In this case, the non-selection period is a period in which the voltage is held when the TPT is off.

By appropriately selecting the intermediate voltage between the sub-VON and the sub-VOFF and the intermediate voltage between -VON and -VOFF, the liquid crystal cell 2 can display gradations.

[Problem that the invention seeks to solve]

As described above, in the active matrix liquid crystal display device, the liquid crystal cell voltage changes following the data line voltage when not selected. Therefore, the 10th display corresponds to the display mode (on display or off display) of other liquid crystal cells when not selected
As shown in Figure (B), the effective value of the liquid crystal cell voltage differs, resulting in a problem of uneven display brightness. In addition,
The broken line shown in FIG. 10(B) is an ideal liquid crystal cell voltage that does not cause uneven brightness.

On the other hand, as shown in FIG. 11, when the data line voltage when the first row is selected is, for example, the ON display voltage, and when the first row is not selected, the data line voltage is an intermediate voltage (the second row In the gradation display (described below), the effective value of the liquid crystal cell voltage varies depending on the gradation display mode of other liquid crystal cells, resulting in uneven brightness. In FIG. 11, 1H is one gate line selection time for selecting the gate line of each row.

[Means for solving problems]

FIG. 1 shows a principle diagram of a method for driving an active matrix liquid crystal display device according to the present invention. As shown in the figure, the data line voltage (D) is set for one gate line selection period (1H).
) has a phase according to the display brightness level above,
In addition, it is driven with a ramp-like or step-like voltage such that the effective value is equal in all gate line selection periods regardless of the display brightness level.

[Operation] The data line voltage of a certain column is, for example, a ramp waveform having a phase depending on the gradation display brightness level, and this is selected depending on the gate line voltages G+, G2, . . . of each row. The liquid crystal cell has a data line voltage G+, a gate line voltage G+,
A voltage corresponding to G2, . . . is applied, and gradation is displayed. In this case, for example, in the gate line of the first row, the effective value of the liquid crystal cell voltage is always constant regardless of the gradation display brightness of the liquid crystal cell when not selected, and uneven brightness does not occur.

〔Example〕

FIG. 2 shows a block diagram of one embodiment of the present invention.

In FIG. 2, 5 is a control circuit which outputs a scanning control signal and 5 DATA every 1H indicating the start timing of the video signal, a video signal brightness signal, and a latch signal in synchronization with the video signal and the synchronization signal. 6 is a gate driver which controls gate line voltages G+, G2, . . . with gate line selection intervals of 81° 82, . . . k: 1H (7) of the display panel 7.
・Apply. Reference numeral 9 denotes a data driver, which has the configuration shown in FIG. 3, and, as will be described later, provides ramp-shaped data line voltages D+, D2, and the like having phases (different within 111 periods) corresponding to the video signal luminance signal level. ... on the data lines 10+, 102, ... of the display panel 7
to be applied.

Here, the operation for obtaining a ramp-shaped data line voltage as shown in FIG. 1(B) will be described. FIG. 4 shows a specific circuit diagram corresponding to one data line of the analog latch & ramp waveform wave generation circuit 12 of the data driver 9 shown in FIG. 3, and FIG. 5 shows the signal waveform for explaining its operation. Show the diagram.

5DATΔ(
When the signal (FIG. 5(B)) is taken out and supplied to the shift register 11 shown in FIG. 3, the signal Q+ is generated in synchronization with the reset signal CLK (FIG. 5(A)).

G2 ((C), (D) in the figure), . . . QN are output. Signals Q+, G2, . . . QN are output repeatedly in a 1H period. In the 1st H, for example, the signal Q
1, the switch S W + shown in FIG. 4 is turned on, and the luminance signal (FIG. 5 (E)) is transferred to the capacitor C1.
, the amplifier 13 performs thimble hold, and the output of the amplifier 13 becomes as shown in FIG. 5(G). shift register 11
When the signals Ql-QN are output from the latch signal (fifth
(F)) is output, and the switch SW2 is turned on during the H level period of the latch signal. The latch signal is output to all data lines simultaneously.

From the voltage sampled at the latch timing when the switch SW2 is turned on, the capacitor C2 becomes Iref --
It is charged with a time constant of Vref /R, and the output voltage of the amplifier 14 gradually rises as shown in FIG. 5(H) (amplifier 14. capacitor Cz.

(The integrator is formed by the resistor R.) When the output voltage (data line voltage Di) reaches the voltage set in the amplifier (comparator) 15 QNk: the reset signal ◎ (Fig. 5 (I)
) is taken out, the switch S W 3 is turned on, and the data line voltage D1 is held at the voltage VOFF. When the reset signal ends, switch S W 3 is turned off and capacitor C2 is charged again. In this way, the first H-th ramp data line voltage is obtained.

When the latch signal is taken out at the end of the 1st H, the switch SW2 is turned on, and the sample-and-hold output voltage of the amplifier 13 is taken out as the data line voltage, and thereafter, the same operation as in the 1st H takes place in the 2nd H. A ramp-shaped data line is obtained. After the 3rd H, a ramp-like data line voltage is obtained by the same operation, for example, as shown in Fig. 1 (
A waveform as shown in B) is obtained. The slope of the ramp waveform can be freely selected by appropriately setting the values of the resistor R and the reference voltage -V ref of the capacitor 021 in FIG. 4.

In FIG. 1, for example, the gate line voltage G1 in the first row is shown as a solid line, and the gate line voltage G2 in the second row and below is shown in order to make it easier to understand the phase relationship between the gate line voltages in the second and subsequent rows.
, G3. ... is shown by a dashed line. In addition, in the same figure (B), the broken line is, for example, the data line voltage of the second column,
Liquid crystal cells 2+, 22, connected to each gate line
It has a phase corresponding to the gradation display brightness of... In this case, the slopes of the ramp-shaped data line voltages are all set to be the same, and only the phases differ, so the effective value is a ramp-shaped data line voltage with all phases aligned, for example, as shown in Figure 1 (A) in the first column. It is the same as the data line voltage (that is, the effective values within 1H brightness are all the same).

Here, when all the liquid crystal cells in any row display at the same brightness, the liquid crystal cell voltage is as shown in FIG. 6(A), and on the other hand,
The liquid crystal cell voltage in the case of gradation display with different brightness depending on the row is as shown in FIG. 4(B). In this case, since the data line voltage effective values are all the same regardless of the display mode of the liquid crystal cells in other rows, the effective value of the liquid crystal cell voltage is also constant regardless of the display mode.

Therefore, since the effective value of the liquid crystal cell voltage is always constant regardless of the display mode of other liquid crystal cells when not selected, uneven brightness does not occur.

Note that TFT1+ is applied only when the ramp data line voltage becomes equal to the desired voltage applied to the liquid crystal cell.

12,... to apply the liquid crystal cell voltage by turning on,
The on-resistance of TFT12+, 122, . . . must be sufficiently low.

Further, the data line voltage is not limited to a ramp-like waveform, but may be a step-like waveform having a phase corresponding to gradation display.

〔Effect of the invention〕

According to the present invention, display brightness can be made uniform regardless of the display brightness mode of other liquid crystal cells when not selected, and brightness unevenness can be prevented.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of a data driver, and Fig. 4 is a specific circuit diagram of an analog latch & ramp waveform generation circuit. , Fig. 5 is a signal waveform diagram of the circuit shown in Fig. 4, Fig. 6 is a liquid crystal cell voltage waveform diagram of the present invention, Fig. 7 is a general drive waveform diagram, and Fig. 8 is a diagram of TPT and one pixel of LCD. , FIG. 9 is an equivalent circuit diagram when the TPT is off, and FIGS. 10 and 11 are conventional drive waveform diagrams. In the figure, 111121... are thin film transistors (TPT), 2
+, 22... are liquid crystal cells, 5 is a 1II11 control circuit, 6 is a gate driver, 7 is a display panel, 8+, 82,... are gate lines, 9 is a data driver, 10+, 102,... are Data line, 11 is shift register, 12 is analog latch & ramp waveform generation circuit, 13-1
5 is an amplifier, C+, C2 are capacitors, R is a resistor, SW+ to SW3 are switches, D, D+, C2,... are data line voltages, G+, G
2, . . . are gate line voltages. Figure 1 of Keihan Akira n Rinbuji Figure 1 for Kontoshi Ichikata Shark's Fuma 2 Figure 2 Main data code \N/%: 1's 7゛ Low v 2 eyes Wb 4 Figure

Claims (1)

[Claims] The data line voltage (D) applied to the data lines arranged in the horizontal direction is changed from the gate line voltage (G_1, G_2, G_3) with a constant period applied to the gate lines arranged in the vertical direction.
. is a ramp-shaped or A method for driving an active matrix liquid crystal display device, characterized in that it is driven using a stepped voltage.