JPS63302759A - Snubber circuit for switching power source - Google Patents
Snubber circuit for switching power sourceInfo
- Publication number
- JPS63302759A JPS63302759A JP13439787A JP13439787A JPS63302759A JP S63302759 A JPS63302759 A JP S63302759A JP 13439787 A JP13439787 A JP 13439787A JP 13439787 A JP13439787 A JP 13439787A JP S63302759 A JPS63302759 A JP S63302759A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- auxiliary
- circuit
- transformer
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004804 winding Methods 0.000 claims abstract description 36
- 239000003990 capacitor Substances 0.000 claims abstract description 27
- 238000001514 detection method Methods 0.000 claims description 5
- 230000008929 regeneration Effects 0.000 claims description 3
- 238000011069 regeneration method Methods 0.000 claims description 3
- 238000007599 discharging Methods 0.000 abstract description 2
- 230000001172 regenerating effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 230000005284 excitation Effects 0.000 description 2
- 101001126234 Homo sapiens Phospholipid phosphatase 3 Proteins 0.000 description 1
- 102100030450 Phospholipid phosphatase 3 Human genes 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
本発明は中または大電力のより高周波化したスイッチン
グ電源において、能率の向上を達成するためのスナバ−
回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention is directed to a snubber for achieving improved efficiency in medium or high power, higher frequency switching power supplies.
It is related to circuits.
「従来の技術」
一般に、この種のスイッチング電源は、第６図に示すよ
うに、主トランス（１）の１次巻線（２）と主開閉素子
であるＭＯＳＦＥＴ（３）とを直流電源（４）間に直列
に結合し、前記主トランス（１）の２次巻線（５）に、
整流ダイオード（６）、転流ダイオード（７）、チョー
クコイル（８ａ） 、コンデンサ（８ｂ）からなる整流
ろ波回路を結合し、この出力を検出増幅回路（９）とア
イソレータ（ｌＯ）を介して時比率制御用ＩＣ（１１）
に結合し、このＩＣ（１１）にてＭＯＳＦＥＴ（３）を
制御するように構成されている。``Prior Art'' In general, this type of switching power supply, as shown in FIG. 4) coupled in series between the secondary windings (5) of the main transformer (1);
A rectifier filter circuit consisting of a rectifier diode (6), a commutation diode (7), a choke coil (8a), and a capacitor (8b) is combined, and the output is passed through a detection amplifier circuit (9) and an isolator (lO). Duty ratio control IC (11)
This IC (11) is configured to control the MOSFET (3).
このようなスイッチング電源において、高能率化達成の
ための従来のスナバ−回路は、第６図に示すように、Ｍ
ＯＳ Ｆ Ｅ Ｔ（３）のドレン・ソース間に、ダイオ
ード（１２）と抵抗（１３）の並列回路に、コンデンサ
（１４）を直列に挿入した回路を結合し、同時に前記主
トランス（１）の３次巻線（１５）とダイオード（１６
）の直列回路からなるクランプ回路を併用していた。In such a switching power supply, the conventional snubber circuit for achieving high efficiency is as shown in FIG.
A circuit in which a capacitor (14) is inserted in series with a parallel circuit of a diode (12) and a resistor (13) is connected between the drain and source of the OS FET (3), and at the same time the main transformer (1) is Tertiary winding (15) and diode (16)
) was used together with a clamp circuit consisting of a series circuit.
「発明が解決しようとする問題点」
以上のような従来の回路における各部の波形図が第７図
に示される。この第７図のＴ１時に、ＭＯＳＦＥＴ（３
）がターンオフしたものとすると、このＭＯＳＦＥＴ（
３）を流れる電流Ｉｑは直ちに零点に向うが、主トラン
ス（１）の１次巻線（２）には＋ Ｉ” ｑｐ （Ｌｘ
＋ｌ、、 ）のエネルギーが残存し、１４時まで継続
する。"Problems to be Solved by the Invention" A waveform diagram of each part in the conventional circuit as described above is shown in FIG. At T1 in Fig. 7, MOSFET (3
) is turned off, this MOSFET (
3) immediately goes to zero, but the primary winding (2) of the main transformer (1) has +I”qp (Lx
+l,, ) energy remains and continues until 14:00.
なお、ＩＱＰはターンオフ時のピーク電流、Ｌｌは１次
巻線（２）のり一ケージインダクタンス、Ｌ３は１次巻
線（２）に換算した２次巻線（５）のり一ケージインダ
クタンスである。Note that IQP is the peak current at turn-off, Ll is the one-cage inductance of the primary winding (2), and L3 is the one-cage inductance of the secondary winding (5) converted to the primary winding (2).
前記エネルギーはダイオード（１２）を介してコンデン
サ（１４）に充電される。つまりＴ３−Ｔ、間はＩｔ−
Ｉｑ＝Ｉｃが成立する。このときＶｑｐ＝＝Ｖｃｐとす
れば下記（１）式が成立する。The energy is charged to a capacitor (14) via a diode (12). In other words, T3-T, the interval is It-
Iq=Ic holds true. At this time, if Vqp==Vcp, the following equation (1) holds true.
＋ Ｉ”ＱＰ（Ｌｉ”Ｌａ）＝＋ ＣＶ”ｑｐ
−（１）つぎに、Ｔ、−Ｔ４間にコンデンサ（１４）に
蓄えられたエネルギーはＴ４−Ｔ、間に抵抗（１３）と
主トランス（１）の１次巻線（２）を通じてそのエネル
ギーは一部が電源（４）に返送され、さらにＴ１時点の
ＭＯＳＦＥＴ（３）のターンオン時に、抵抗（１３）と
ＭＯＳＦＥＴ（３）を介して抵抗（１３）の損失として
消耗され、電圧■ｃは零となってターンオフ時点のＴ。+ I”QP(Li”La)=+CV”qp
-(1) Next, the energy stored in the capacitor (14) between T and -T4 is transmitted through the resistor (13) between T4 and T4 and the primary winding (2) of the main transformer (1). A part of is returned to the power supply (4), and furthermore, when the MOSFET (3) is turned on at time T1, it is consumed as a loss in the resistor (13) via the resistor (13) and MOSFET (3), and the voltage ■c becomes T at the time of turn-off when it becomes zero.
まで待期する。すなわち、Ｔ、−Ｔ４のターンオフ時に
コンデンサ（１４）に充電されたエネルギーの大半はＴ
、−Ｔ、間とＴ、−Ｔ、間に抵抗（１３）の損失となっ
て放電される。I'll wait until then. In other words, most of the energy charged in the capacitor (14) when T and -T4 are turned off is T.
, -T, and T, -T, causing a loss in the resistor (13) and discharging.
ツマリ、ＭＯＳＦＥＴ（３）の印加ピーク電圧ＶＣＩＰ
を抑制するためにはコンデンサ（１４）の容量も（１）
式のように相当量が必要であるが、この放電時の損失と
なるので、能率と実装上の考慮より充分な大きさのもの
は実用上用意できない、これを補うため、第６図の従来
回路においては３次巻線（１５）とダイオード（１６）
を設けて、
＋Ｉ”、ｑｐ（Ｌｔ＋Ｌお）
というエネルギーの大半を電ホ（４）側に返送すると同
時にピーク電圧ＶＱＰの抑制を図ったものである。Applied peak voltage VCIP of MOSFET (3)
In order to suppress the capacitor (14), the capacity (1)
As shown in the formula, a considerable amount is required, but due to the loss during this discharge, it is practically impossible to prepare a sufficiently large one due to efficiency and mounting considerations.To compensate for this, the conventional method shown in Fig. 6 In the circuit, the tertiary winding (15) and the diode (16)
+I'', qp(Lt+Lo) Most of the energy is returned to the power supply (4) side, and at the same time, the peak voltage VQP is suppressed.
これらの方式ではＭＯＳＦＥＴ（３）の時比率が５０％
以下に制限され１回路全体のバホーマンスが損われるの
みならず、中および大電力においてはピーク電圧ＶｑＰ
の抑制も不充分であるという問題点があった。In these methods, the duty ratio of MOSFET (3) is 50%.
Not only is the vacuum of the entire circuit impaired, but also the peak voltage VqP is limited to
There was also the problem that the suppression of
ｒ問題点を解決する起めの手段」
本発明は上述のような従来の欠点を除去するためになさ
れたもので、主トランスの１次巻線と主開閉素子との直
列回路を直流電源に結合し、前記主トランスの２次巻線
を整流ろ波回路を介して出力端子に結合し、この出力端
子に結合した検出増幅回路を、アイソレータと時比率制
御ＩＣを介して前記主開閉素子の開閉を制御するように
したスイッチング電源において、前記主開閉素子の両端
に、ダイオードとコンデンサの直列回路を結合し、この
ダイオードとコンデンサの結合点と前記直流電源の一端
との間に、補助トランスの１次巻線と補助開閉素子との
直列回路を結合し、前記補助トランスの２次巻線を、整
流ろ波回路を介して電力回生利用個所に結合してなるも
のである。The present invention was made in order to eliminate the above-mentioned drawbacks of the conventional technology. The secondary winding of the main transformer is coupled to an output terminal via a rectifying filter circuit, and the detection amplifier circuit coupled to this output terminal is connected to the main switching element via an isolator and a duty ratio control IC. In a switching power supply that controls opening and closing, a series circuit of a diode and a capacitor is coupled to both ends of the main switching element, and an auxiliary transformer is connected between the connection point of the diode and the capacitor and one end of the DC power supply. A series circuit of a primary winding and an auxiliary switching element is coupled, and a secondary winding of the auxiliary transformer is coupled to a power regeneration utilization point via a rectifying filter circuit.
「作用」
主開閉素子がターンオフすると主トランスのり一ケージ
インダクタンスに蓄えられたエネルギーと励磁エネルギ
ーの戻りが、主開閉素子と並列なコンデンサに充電され
る。この充電電荷は、従来は主開閉素子のターンオンに
より抵抗を介して主開閉素子を通して放電される。とこ
ろが、本発明では、補助トランスの１次巻線と補助開閉
素子を通して放電されるので、補助トランスの２次巻線
から全エネルギーが取出され、電力回生利用個所に供給
される。"Operation" When the main switching element is turned off, the energy stored in the main transformer cage inductance and the return of the excitation energy are charged to the capacitor in parallel with the main switching element. Conventionally, this charged charge is discharged through the main switching element via a resistor when the main switching element is turned on. However, in the present invention, since the discharge is carried out through the primary winding of the auxiliary transformer and the auxiliary switching element, all the energy is taken out from the secondary winding of the auxiliary transformer and supplied to the point where the power is regenerated.
ｒ実施例」 以下、本発明の゛一実施例を図面に基づき説明する。r Example” Hereinafter, one embodiment of the present invention will be described based on the drawings.
（１）は主トランスで、この主トランス（１）の１次巻
線（２）と主開閉素子であるＭＯＳＦＥＴ（３）との直
列回路を直流電源（４）に結合する。前記主トランス（
１）の２次巻線（５）には、整流ダイオード（６）。(1) is a main transformer, and a series circuit of the primary winding (2) of this main transformer (1) and a MOSFET (3) which is a main switching element is coupled to a DC power supply (4). The main transformer (
The secondary winding (5) of 1) is a rectifier diode (6).
転流ダイオード（７）、チョークコイル（８ａ）、コン
デンサ（８ｂ）からなる整流が波回路を介して出力端子
（１７）（１８）が結合されている。また、この出力端
子（１７） （１ｇ）に検出増幅回路（９）を結合し、
さらにアイソレータとしてのフォトカプラ（１０）、時
比率制御ＩＣ（１１）を介して前記ＭＯ８ＦＥＴ（３）
の開閉を制御するようにしてスイッチング電源を構成す
る。このスイッチング電源において、前記ＭＯ８ＦＥＴ
（３）の両端に、ダイオード（１２）とコンデンサ（１
４）の直列回路を結合し、このダイオード（１２）とコ
ンデンサ（１４）の結合点と前記直流電源（４）の一端
との間に、補助トランス（１９）の１次巻線（２０）と
補助開閉素子としてのＭＯＳ Ｆ Ｅ Ｔ（２１）との
直列回路を結合し、前記補助トランス（１９）の２次巻
線（２２）を、ダイオード（２３） （２４）、チョー
クコイル（２５）からなる整流ろ波回路を介して電力回
生利用個所１例えば、前記時比率制御ＩＣ（１１）の補
助電源部（２６）に結合する。この補助電源部（２６）
は具体的には、主トランス（１）の３次巻線（２７）で
取出された電力を、ダイオード（２８）とコンデンサ（
２９）で平滑化する回路で構成されている。A rectifier consisting of a commutation diode (7), a choke coil (8a), and a capacitor (8b) is coupled to output terminals (17) and (18) via a wave circuit. In addition, a detection amplifier circuit (9) is connected to this output terminal (17) (1g),
Furthermore, the MO8FET (3) is connected to the photocoupler (10) as an isolator and the duty ratio control IC (11).
A switching power supply is configured to control opening and closing of the switch. In this switching power supply, the MO8FET
A diode (12) and a capacitor (1
4), and the primary winding (20) of the auxiliary transformer (19) is connected between the connection point of the diode (12) and the capacitor (14) and one end of the DC power supply (4). A series circuit with the MOS FET (21) as an auxiliary switching element is coupled, and the secondary winding (22) of the auxiliary transformer (19) is connected to the diodes (23) (24) and the choke coil (25). It is coupled to the power regeneration utilization point 1, for example, the auxiliary power supply section (26) of the duty ratio control IC (11), through a rectifying and filtering circuit. This auxiliary power supply section (26)
Specifically, the power extracted by the tertiary winding (27) of the main transformer (1) is transferred to the diode (28) and the capacitor (
29) consists of a smoothing circuit.
以上のような回路構成における作用を第５図（ａ）（ｂ
）の波形図によって説明する。Ｔ３−Ｔ４時のＭＯＳＦ
ＥＴ（３）のターンオフ時の動作は第７図の従来例と同
様である。しかし、スナバ−コンデンサ（１４）が本発
明の場合、充分大きいものを用いることにより（１）式
によりピーク電圧ｖｑｐは充分に抑制されＴ３−Ｔ４期
間も長くなる。ちなみに、この電圧ｖｑの立上りの緩和
は人、出力端子の雑音電圧抑制にも非常に重大である＠
Ｔ４−Ｔ４’の期間は主トランス（１）の励磁エネル
ギーの戻りがコンデンサ（１４）に充電され、Ｔ４′に
至りて電圧ＶＱは最高値となる。Ｔ４’−Ｔ、間におイ
テは補助（７）ＭＯＳＦＥＴ（２１）は主ＭＯ８ＦＥＴ
（３）と同様遮断されているので、その間もコンデンサ
（１４）の電圧Ｖｃは最大電圧Ｖｑｍｘにキープされる
。Ｔ２に至りて主ＭＯ８ＦＥ Ｔ （３）がターンオン
すると、ダイオード（１２）に阻止されるので従来回路
によるようなＴ１−Ｔ、間の電流Ｉｃ、は主ＭＯＳ Ｆ
、Ｅ Ｔ（３）を通過せず、電流ＩＱＩには急峻な電流
は存在しない、ちなみに、従来例のＴ、−Ｔ、間では急
峻な電流は抵抗（１３）の損失のみならず主ＭＯ５ＦＥ
Ｔ（３）−Ｏターンオン損失および入出力端子雑音を増
大しこれも重大な障害の１つであった。The effects of the above circuit configuration are shown in Figures 5 (a) and (b).
) waveform diagram. MOSF at T3-T4
The operation of the ET (3) at turn-off is similar to the conventional example shown in FIG. However, in the case of the present invention, the snubber capacitor (14) is sufficiently large, so that the peak voltage vqp is sufficiently suppressed according to equation (1), and the T3-T4 period is also lengthened. By the way, easing the rise of this voltage vq is also very important for suppressing noise voltage at the output terminal.
During the period T4-T4', the return excitation energy of the main transformer (1) charges the capacitor (14), and the voltage VQ reaches its maximum value at T4'. T4'-T, the one in between is the auxiliary (7) MOSFET (21) is the main MO8FET
Since it is cut off like in (3), the voltage Vc of the capacitor (14) is kept at the maximum voltage Vqmx during that time as well. When the main MO8FE T (3) turns on at T2, it is blocked by the diode (12), so the current Ic between T1 and T, as in the conventional circuit, is reduced to the main MO8FE T (3).
, E T(3), and there is no steep current in the current IQI.Incidentally, the steep current between T and -T in the conventional example is caused not only by the loss of the resistor (13) but also by the main MO5FE.
This increased T(3)-O turn-on loss and input/output terminal noise, which was also one of the serious problems.
ところが、本発明ではＴＬ時点において、補助ＭＯＳ
Ｆ Ｅ Ｔ（２１）がターンオンするとコンデンサ（１
４）に蓄えられた電荷のエネルギーは補助トランス（１
９）を通じてＴ、−Ｔ、間に放電される。しかして第１
図の点線で示すように、このときの補助トランス（１９
）と直列に挿入されたチョークコイル（３０）は適当な
インピーダンスであって、コンデンサ（１４）の放電電
流の立上りを抑制するとともにコンデンサ（１４）と適
当な共振により電圧Ｖｃを１２時点において零にまで持
ちこすものである。前記チョークコイル（３０）は無損
失のインピーダンスであるのでコンデンサ（１４）に充
電されたエネルギーは理論上、すべて補助トランス（１
９）の２次巻線（２２）より取出すことが可能であり、
時比率制御ＩＣ（１１）への電力の回生利用が可能であ
る。However, in the present invention, at the time of TL, the auxiliary MOS
When FET (21) turns on, the capacitor (1
4) The energy of the charge stored in the auxiliary transformer (1
9) is discharged between T and -T. However, the first
As shown by the dotted line in the figure, the auxiliary transformer (19
) is inserted in series with the choke coil (30), which has an appropriate impedance and suppresses the rise of the discharge current of the capacitor (14), and also reduces the voltage Vc to zero at time 12 by appropriate resonance with the capacitor (14). It is something that can be brought up to. Since the choke coil (30) has a lossless impedance, theoretically all the energy charged in the capacitor (14) is transferred to the auxiliary transformer (1).
9) can be taken out from the secondary winding (22),
It is possible to regenerate power to the duty ratio control IC (11).
前記第１図の実施例では補助トランス（１９）で取出さ
れたエネルギーは時比率制御ＩＣ（１１）の電源の一部
として帰還するようにした。In the embodiment shown in FIG. 1, the energy taken out by the auxiliary transformer (19) is fed back as part of the power supply for the time ratio control IC (11).
しかし１本発明ではこれに限られるものではなく、第２
図に示すように、直流電源（４）に並列に電力帰還させ
ても、第３図に示すように、直流電源（４）に直列に電
力帰還させても、さらに第４図に示すように負荷側に電
力帰還させてもよい。However, the present invention is not limited to this, and the second invention is not limited to this.
Even if the power is returned in parallel to the DC power source (4) as shown in the figure, even if the power is returned in series to the DC power source (4) as shown in Figure 3, the power will be returned as shown in Figure 4. Power may be fed back to the load side.
なお、本発明は、フライバック方式、プッシュプル方式
、ブリッジ方式などすべてのコンバータに応用できる。Note that the present invention can be applied to all converters such as flyback type, push-pull type, and bridge type.
「発明の効果」
本発明は上述のように構成したので、主開閉素子のター
ンオフ時に充電されたエネルギーはすべて電力帰還され
て有効に利用され、損失がない。[Effects of the Invention] Since the present invention is configured as described above, all of the energy charged when the main switching element is turned off is fed back and used effectively, and there is no loss.
また、ノイズの抑制、能率の向上等にも優れた効果を有
する。It also has excellent effects in suppressing noise and improving efficiency.
第１図は本発明によるスイッチング電源のスナバ−回路
の一実施例を示す電気回路図、第２図、第３図および第
４図はそれぞれボ発明の異なる例の回路図、第５図は本
発明による回路の各部の波形図、第６図は従来の回路の
電気回路図、第７図は従来回路の各部の波形図である。
（１）・・・主トランス、（２）・・・１次巻線、（３
）・・・主開閉素子（ＭＯＳ Ｆ Ｅ Ｔ）、 （４）
・・・直流電源、（５）・・・２次巻線、（９）・・・
検出増幅回路、（１０）・・・アイソレータ（フォトカ
プラ）、（１１）・・・時比率制御ＩＣ１（１２）・・
・ダイオード、（１４）・・・コンデンサ、 （１９）
・・・補助トランス、 ’（２０）・・・１次巻線、
（２１）・・・補助開閉素子（ＭＯＳＦＥＴ）、（２２
）・・・２次巻線、（２６）・・・補助電源部、（３）
・・・チョークコイル。
出願人 ネミック・ラムダ株式会社
同 株式会社 電 設FIG. 1 is an electric circuit diagram showing one embodiment of the snubber circuit of a switching power supply according to the present invention, FIGS. 2, 3, and 4 are circuit diagrams of different examples of the invention, and FIG. FIG. 6 is a waveform diagram of various parts of the circuit according to the invention, FIG. 6 is an electric circuit diagram of a conventional circuit, and FIG. 7 is a waveform diagram of various parts of the conventional circuit. (1) Main transformer, (2) Primary winding, (3
)...Main switching element (MOS FET), (4)
...DC power supply, (5)...Secondary winding, (9)...
Detection amplifier circuit, (10)...Isolator (photocoupler), (11)... Duty ratio control IC1 (12)...
・Diode, (14)...Capacitor, (19)
...Auxiliary transformer, '(20)...Primary winding,
(21)... Auxiliary switching element (MOSFET), (22
)...Secondary winding, (26)...Auxiliary power supply section, (3)
···choke coil. Applicant Nemic Lambda Co., Ltd. Densetsu Co., Ltd.
Claims (5)
を直流電源に結合し、前記主トランスの２次巻線を整流
ろ波回路を介して出力端子に結合し、この出力端子に結
合した検出増幅回路を、アイソレータと時比率制御ＩＣ
を介して前記主開閉素子の開閉を制御するようにしたス
イッチング電源において、前記主開閉素子の両端に、ダ
イオードとコンデンサの直列回路を結合し、このダイオ
ードとコンデンサの結合点と前記直流電源の一端との間
に、補助トランスの１次巻線と補助開閉素子との直列回
路を結合し、前記補助トランスの２次巻線を、整流ろ波
回路を介して電力回生利用個所に結合してなることを特
徴とするスイッチング電源のスナバー回路。(1) A series circuit of the primary winding of the main transformer and the main switching element is coupled to a DC power supply, the secondary winding of the main transformer is coupled to an output terminal via a rectifying filter circuit, and this output terminal The detection amplifier circuit coupled to the isolator and duty ratio control IC
In the switching power supply, a series circuit of a diode and a capacitor is connected to both ends of the main switching element, and a connection point between the diode and the capacitor and one end of the DC power supply are connected to the connecting point of the diode and the capacitor. A series circuit of the primary winding of an auxiliary transformer and an auxiliary switching element is coupled between the transformer and the auxiliary switching element, and the secondary winding of the auxiliary transformer is coupled to a power regeneration utilization point via a rectifying filter circuit. A snubber circuit for a switching power supply characterized by:
ダンス素子を挿入してなる特許請求の範囲第１項記載の
スイッチング電源のスナバー回路。(2) A snubber circuit for a switching power supply according to claim 1, which comprises a suitable impedance element inserted in series with the primary winding of an auxiliary transformer.
して電力帰還してなる特許請求の範囲第１項記載のスイ
ッチング電源のスナバー回路。(3) A snubber circuit for a switching power supply according to claim 1, in which the secondary winding of the auxiliary transformer is connected in parallel to the DC power supply for power feedback.
して電力帰還してなる特許請求の範囲第１項記載のスイ
ッチング電源のスナバー回路。(4) A snubber circuit for a switching power supply according to claim 1, wherein the secondary winding of the auxiliary transformer is connected in series to a DC power supply and returns power.
帰還してなる特許請求の範囲第１項記載のスイッチング
電源のスナバー回路。(5) A snubber circuit for a switching power supply according to claim 1, wherein the secondary winding of the auxiliary transformer is coupled to the load side for power feedback.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62134397A JPH07123349B2 (en) | 1987-05-29 | 1987-05-29 | Snubber circuit of switching power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62134397A JPH07123349B2 (en) | 1987-05-29 | 1987-05-29 | Snubber circuit of switching power supply |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63302759A true JPS63302759A (en) | 1988-12-09 |
| JPH07123349B2 JPH07123349B2 (en) | 1995-12-25 |
Family
ID=15127442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62134397A Expired - Lifetime JPH07123349B2 (en) | 1987-05-29 | 1987-05-29 | Snubber circuit of switching power supply |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07123349B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102484421A (en) * | 2009-09-08 | 2012-05-30 | 皇家飞利浦电子股份有限公司 | Switching Device For An X-Ray Generator |
| EP2884646A3 (en) * | 2013-12-13 | 2015-08-05 | LG Innotek Co., Ltd. | Multiple-output DC/DC converter and power supply having the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS583787U (en) * | 1981-06-29 | 1983-01-11 | 富士電気化学株式会社 | DC-DC converter circuit |
-
1987
- 1987-05-29 JP JP62134397A patent/JPH07123349B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS583787U (en) * | 1981-06-29 | 1983-01-11 | 富士電気化学株式会社 | DC-DC converter circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102484421A (en) * | 2009-09-08 | 2012-05-30 | 皇家飞利浦电子股份有限公司 | Switching Device For An X-Ray Generator |
| EP2884646A3 (en) * | 2013-12-13 | 2015-08-05 | LG Innotek Co., Ltd. | Multiple-output DC/DC converter and power supply having the same |
| US9490708B2 (en) | 2013-12-13 | 2016-11-08 | Lg Innotek Co., Ltd. | Multiple-output DC/DC converter and power supply having the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07123349B2 (en) | 1995-12-25 |
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