JPS63302632A - Signal discrimination circuit - Google Patents
Signal discrimination circuitInfo
- Publication number
- JPS63302632A JPS63302632A JP62139238A JP13923887A JPS63302632A JP S63302632 A JPS63302632 A JP S63302632A JP 62139238 A JP62139238 A JP 62139238A JP 13923887 A JP13923887 A JP 13923887A JP S63302632 A JPS63302632 A JP S63302632A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- circuit
- counter
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims abstract description 10
- 230000007257 malfunction Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Stereo-Broadcasting Methods (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、所定周波数の識別信号の存在を判別する信号
判別回路に関するもので、特に前記識別信号の存在を、
カウンタを用いて判別する信号判別回路の誤動作を防止
せんとするものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a signal discrimination circuit for discriminating the presence of an identification signal of a predetermined frequency.
This is intended to prevent malfunction of a signal discrimination circuit that discriminates using a counter.
（ロ）従来の技術
ＦＭステレオ放送のＳ／Ｎの改善を計り、サービスエリ
アの拡大を計ったものとして、１ＭＸステレオ放送が提
案されている。前記２ＭＸステレオ放送は、従来のＦＭ
ステレオ放送の送信信号に加えて、圧縮されたステレオ
差信号を同時に送信するもので、前記圧縮されたステレ
オ差信号はステレオ差信号がＡＭ変調される３８ＫＨｚ
副搬送波に直交関係に変調きれている。また、２ＭＸス
テレオ放送の送信信号中には、通常のＦＭステレオ放送
と区別する為、１０Ｈｚの識別信号が含まれている。従
って、ＦＭＸステレオ受信を行なう為には、前記識別信
号の検出を行ない、受信機の受信モードをＦＭＸステレ
オ受信に適する様切換える必要がある。(b) Conventional technology 1MX stereo broadcasting has been proposed as a way to improve the S/N ratio of FM stereo broadcasting and expand the service area. The 2MX stereo broadcast is the conventional FM
In addition to the stereo broadcast transmission signal, a compressed stereo difference signal is simultaneously transmitted, and the compressed stereo difference signal is a 38KHz AM modulated stereo difference signal.
It can be modulated orthogonally to the subcarrier. Furthermore, the transmission signal of the 2MX stereo broadcast includes a 10 Hz identification signal to distinguish it from normal FM stereo broadcast. Therefore, in order to perform FMX stereo reception, it is necessary to detect the identification signal and switch the receiving mode of the receiver to be suitable for FMX stereo reception.
尚、２ＭＸステレオ放送については、雑誌ｒ ＪＡＳＪ
ＯＵＲＮＡＬＪ １９ Ｂ ６年９月号第１１頁乃至第
１５頁に詳述きれている。Regarding 2MX stereo broadcasting, please refer to the magazine r JASJ.
A detailed explanation can be found in OURNALJ 19B September 6th issue, pages 11 to 15.
ところで、前記１０）１ｚの識別信号を検出する為には
、第２図に示す如き信号判別回路を用いればよい、第２
図において、第１入力端子（１）に印加される１９ＫＨ
ｚステレオパイ只ット信号は、第１分周回路（２）で約
７４Ｈｚに分周され、クロック信号としてカウンタ（３
）に印加される。−１第２入力端子（４）に印加される
１０Ｈｚ識別信号は、バンドパスフィルタ（５）を介し
てパルス発生回路（６）に印加される為、該パルス発生
回路（６）から識別信号と等しい周波数のパルス信号が
発生する。前記パ１ルス信号は、第２分周回路（７）で
分周されカウンタ（３）に動作信号として供給される。By the way, in order to detect the identification signal of 10) 1z, it is sufficient to use a signal discrimination circuit as shown in FIG.
In the figure, 19KH applied to the first input terminal (1)
The frequency of the z stereo pilot signal is divided by the first frequency dividing circuit (2) to approximately 74Hz, and the frequency is divided to approximately 74Hz by the first frequency dividing circuit (2).
) is applied to -1 The 10Hz identification signal applied to the second input terminal (4) is applied to the pulse generation circuit (6) via the bandpass filter (5), so the identification signal and Pulse signals of equal frequency are generated. The pulse signal is frequency-divided by a second frequency dividing circuit (7) and supplied to the counter (3) as an operation signal.
その為、前記カウンタ（３）において、前記パルス信号
のｒＨ，期間中クロック信号の計数が行なわれ、前記カ
ウンタ（３）の計数値が所定値か否かが検出回路（８〉
で検出される。Therefore, the counter (3) counts the rH of the pulse signal and the clock signal during the period, and the detection circuit (8) determines whether the counted value of the counter (3) is a predetermined value.
Detected in
（ハ）発明が解決しようとする問題点
しかしながら、カウンタを用いて識別信号の存在を判別
する方法においては、識別信号が判別回路に印加されな
くなったとき、カウンタの計数が停止し、判別回路が前
の状態を維持したままになるという問題があった。例え
ば、急激な離調が行なわれたり、車載用受信機において
トンネルに入り信号の遮断が行なわれたりした場合、識
別信号が存在しなくなったにも関わらず、受信機が識別
信号の存在時と同じ状態を保ち、インジケータの誤点灯
等の誤動作を生じていた。(c) Problems to be solved by the invention However, in the method of determining the presence of an identification signal using a counter, when the identification signal is no longer applied to the discrimination circuit, the counter stops counting and the discrimination circuit stops. There was a problem that the previous state was maintained. For example, if a sudden detuning occurs, or if an on-vehicle receiver enters a tunnel and the signal is cut off, the receiver may detect the presence of an identification signal even though the identification signal no longer exists. The condition remained the same, causing malfunctions such as incorrect lighting of indicators.
（ニ）問題点を解決するための手段
本発明は、上述の点に鑑み成されたもので、カウンタに
動作信号として印加される識別信号に応じたパルス信号
よりも長い周期のクロック信号を発生するクロック信号
発生回路と、前記パルス信号と前記クロック信号とを演
算し、識別信号の有無に応じた出力信号を発生し、前記
カウンタの出力信号が印加される検出回路を強制駆動す
る演算回路とを備える点を特徴とする。(d) Means for Solving the Problems The present invention has been made in view of the above points, and generates a clock signal with a longer period than the pulse signal corresponding to the identification signal applied to the counter as an operation signal. an arithmetic circuit that calculates the pulse signal and the clock signal, generates an output signal depending on the presence or absence of an identification signal, and forcibly drives a detection circuit to which the output signal of the counter is applied; It is characterized by having the following.
（＊）作用
本発明に依れば、識別信号に応じたパルス信号と、該パ
ルス信号よりも長い周期のクロック信号とを演算し、強
制駆動信号を発生する様にしているので、識別信号が存
在しなくなったとき、カウンタの出力信号の状態に関わ
らず、検出回路を強制駆動することが出来る。(*) Effect According to the present invention, a pulse signal corresponding to an identification signal and a clock signal with a longer period than the pulse signal are calculated to generate a forced drive signal, so that the identification signal is When it no longer exists, the detection circuit can be forced to drive regardless of the state of the output signal of the counter.
（へ）実施例
第１図は、本発明の一実施例を示す回路図で、（９）乃
至（１２）は縦続接続され分周回路を構成する第１乃至
第４７−ＦＦ、（１３）は第４Ｔ−、ＦＦ（１２）の出
力信号とパルス発生回路（６）の出力信号との論理積を
とる第１アンドゲート、（１４）は前記第１乃至第４Ｔ
−ＦＦ（９）乃至（１２）の論理積をとる第２アンドゲ
ート、（１５）は前記第１アンドゲート（１３）の出力
をクロック信号とし、前記第２アンドゲート（１４）の
出力をリセット信号とする第１ 、Ｄ −ＦＦ、及び（
１６）は該第１ Ｄ ７ Ｆ Ｆ（１５）のＱ串力をＤ
入力とし、前記第４ Ｔ−Ｆ Ｆ（１２）の出力をクロ
ック信号とする第２Ｄ−ＦＦである。尚、第１図におけ
る他の回路は、第２図と同一に付説明を省略する。(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which (9) to (12) are the first to 47th FFs connected in cascade to form a frequency dividing circuit, and (13) is the first AND gate that takes the logical product of the output signal of the fourth T-, FF (12) and the output signal of the pulse generation circuit (6), and (14) is the first to fourth T-
- A second AND gate that takes the AND of FFs (9) to (12); (15) uses the output of the first AND gate (13) as a clock signal and resets the output of the second AND gate (14); Let the signals be the first, D-FF, and (
16) is the Q skewer force of the first D 7 F F (15).
This is a second D-FF which uses the output of the fourth TFF (12) as an input and a clock signal. Note that the other circuits in FIG. 1 are the same as those in FIG. 2, and their explanations will be omitted.
第１入力端子（１）に印加される１９ＫＨｚステレオパ
イロツト信号は、分周回路（２）で分周され、クロック
信号としてカウンタ（３）に印加されるとともに、第１
Ｔ−ＦＦ（９）に印加され、第１乃至第４７−ＦＦ（９
）乃至（１２）で更に分周される。その為、第４７−
Ｆ Ｆ（１２）の出力端には、識別信号の周波数の１７
２よりも低い約４ 、６ Ｈｚのクロック信号が発生す
る。前記４ 、６ Ｈｚのクロック信号は、パルス発生
回路（６）から得られる１０Ｈｚの識別信号に応じたパ
ルス信号とともに第１アンドゲート（１３）に印加され
る。パルス発生回路（６）の出力信号は、第３図（イ）
の如くなり、第４Ｔ−ＦＦ（１２）の出力信号は第３図
（ロ）の如くなるので、第１アンドゲート（１３）の出
力信号は第３′ｆｙＪ（八）の如くなる。また、入力が
一第１乃至第４Ｔ−ＦＦ（９）乃至（１２）の出力に接
続された第２アンドゲート（１４）からは、第３図（＝
）に示すリセット信号が発生し、このリセット信号が第
１ Ｄ−Ｆ Ｆ（Ｉｓ）のリセット端子に印加詐れる。The 19KHz stereo pilot signal applied to the first input terminal (1) is frequency-divided by the frequency divider circuit (2) and applied to the counter (3) as a clock signal.
It is applied to T-FF (9), and the first to 47th-FF (9
) to (12). Therefore, the 47th-
At the output terminal of F F (12), 17 of the frequency of the identification signal is
A clock signal of approximately 4,6 Hz, which is lower than 2, is generated. The 4 and 6 Hz clock signals are applied to the first AND gate (13) together with a pulse signal corresponding to a 10 Hz identification signal obtained from the pulse generation circuit (6). The output signal of the pulse generation circuit (6) is shown in Figure 3 (a).
Since the output signal of the fourth T-FF (12) is as shown in FIG. 3 (b), the output signal of the first AND gate (13) is as shown in the third'fyJ (8). In addition, from the second AND gate (14) whose inputs are connected to the outputs of the first to fourth T-FFs (9) to (12), as shown in FIG.
) is generated, and this reset signal is applied to the reset terminal of the first DFF (Is).
その為、第１Ｄ−ＦＦ （１５）のＱ出力には、第３図
（＊）に示す如く、前記リセット信号に応じて「Ｌ」に
なり、第１アンドゲート（１３）の出力信号（第３図（
八））の立下りでｒＨ，となる出力信号が発生する。第
２Ｄ−ＦＦ（１６）のＤ入力には、第１ Ｄ −Ｆ Ｆ
（１５）のＱ出力が接続され、前記第２Ｄ−ＦＦ（１６
）のクロック入力には第４ Ｔ−Ｆ Ｆ（１２）の出力
が接続されている。Therefore, the Q output of the first D-FF (15) becomes "L" in response to the reset signal, as shown in FIG. Figure 3 (
8) At the falling edge of (8)), an output signal of rH is generated. The D input of the second D-FF (16) has the first D-FF
(15) is connected, and the second D-FF (16
) is connected to the output of the fourth TFF (12).
その為、前記第２Ｄ−ＦＦ（１６）のＱ出力には、第３
図（へ）に示す如く、第１アンドゲート（１３）の出力
信号が間欠的に発生している限りｒＨ，となる出力信号
が得られる。前記第２Ｄ−ＦＦ（１６）の出力信号は、
第１アンドゲート（１３）の出力信号が発生しなくなる
と、すなわち第２入力端子（４）に識別信号が印加され
なくなると「Ｌ」になる。従って、前記第２Ｄ−ＦＦ（
１６）の出力信号により、識別信号の有無を表わすこと
が出来る。前記第２Ｄ−Ｆ Ｆ （１６）の出力信号は
、検出回路（８）に強制切換信号として印加される。そ
の為、カウンタ（３）の出力信号の状態に関わらず、検
出回路（８）から１Ｌ」の出力信号が発生し、前記ｒ
Ｌ 、の出力信号が受信機の各部に印加きれ、前記受信
機の切換えが行なわれる。Therefore, the Q output of the second D-FF (16) has the third
As shown in the figure (f), as long as the output signal of the first AND gate (13) is generated intermittently, an output signal of rH can be obtained. The output signal of the second D-FF (16) is
When the output signal of the first AND gate (13) is no longer generated, that is, when the identification signal is no longer applied to the second input terminal (4), it becomes "L". Therefore, the second D-FF (
The output signal of 16) can indicate the presence or absence of the identification signal. The output signal of the second DFF (16) is applied to the detection circuit (8) as a forced switching signal. Therefore, regardless of the state of the output signal of the counter (3), an output signal of 1L is generated from the detection circuit (8), and the r
The output signal of L is applied to each part of the receiver, and the receiver is switched.
（ト）発明の効果
本発明に依れば、識別信号の存在時には、カウンタによ
り前記識別信号の判別が行なわれるので、雑音等を識別
信号と誤って判断する誤動作を防止出来る。また、識別
信号が無くなると、演算回路の出力信号により検出回路
を強制的に切換制御しているので、カウンタのロックに
起因する誤動作を防止出来る。従って、本発明に依れば
、識別信号の有無を正確に判別し得る信号判別回路を提
供出来、特にＦＭＸステレオ放送受信機に用い−て好適
である。(g) Effects of the Invention According to the present invention, when an identification signal is present, the identification signal is discriminated by the counter, so that it is possible to prevent a malfunction in which noise or the like is mistakenly judged as an identification signal. Furthermore, when the identification signal disappears, the detection circuit is forcibly switched and controlled by the output signal of the arithmetic circuit, so that malfunctions due to counter lock can be prevented. Therefore, according to the present invention, it is possible to provide a signal discrimination circuit that can accurately discriminate the presence or absence of an identification signal, and is particularly suitable for use in an FMX stereo broadcast receiver.
第１図は、本発明の一実施例を示す回路図、第２図は従
来の信号判別回路を示す回路図、第３図（イ）乃至（へ
）は本発明の説明に供する為の特性図である。
（３）・・・カウンタ、（６）・・・パルス発生回路、
（８）・・・検出回路、 （９）（１０）（１１）（１
２）・・・Ｔ−ＦＦ、（１３）（１４）・・・アンドゲ
ート、 （１５）（１６）・・・Ｄ−ＦＦ。
第１図
第３図
（へ）Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing a conventional signal discrimination circuit, and Figs. 3 (A) to (F) show characteristics for explaining the present invention. It is a diagram. (3)...Counter, (6)...Pulse generation circuit,
(8)...Detection circuit, (9)(10)(11)(1
2)...T-FF, (13)(14)...AND gate, (15)(16)...D-FF. Figure 1 Figure 3 (to)
Claims (1)
路と、該パルス発生回路の出力パルスに応じてクロック
信号を計数するカウンタと、該カウンタの計数値により
前記識別信号の存在を検出する検出回路とから成る信号
判別回路において、前記パルス発生回路の出力パルスの
周期よりも長い周期のクロック信号を発生するクロック
信号発生回路と、前記パルス発生回路及びクロック信号
発生回路の出力信号を演算して出力信号を発生する演算
回路とを備え、前記演算回路の出力信号により前記検出
回路を強制駆動する様にしたことを特徴とする信号判別
回路。(1) A pulse generation circuit that generates pulses according to the identification signal, a counter that counts clock signals according to the output pulses of the pulse generation circuit, and a detection that detects the presence of the identification signal based on the count value of the counter. a clock signal generating circuit that generates a clock signal with a period longer than the period of the output pulse of the pulse generating circuit; and a signal discriminating circuit that calculates the output signals of the pulse generating circuit and the clock signal generating circuit. 1. A signal discrimination circuit comprising: an arithmetic circuit that generates an output signal; and the detection circuit is forcibly driven by the output signal of the arithmetic circuit.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62139238A JPH07120985B2 (en) | 1987-06-03 | 1987-06-03 | Signal discrimination circuit |
| US07/199,935 US4914680A (en) | 1987-06-03 | 1988-05-27 | Signal distinction circuit |
| DE3852718T DE3852718T2 (en) | 1987-06-03 | 1988-06-01 | Signal detection circuit. |
| EP88108802A EP0293873B1 (en) | 1987-06-03 | 1988-06-01 | A signal distinction circuit |
| CA000568484A CA1314075C (en) | 1987-06-03 | 1988-06-02 | Signal distinction circuit |
| KR88006611A KR960009449B1 (en) | 1987-06-03 | 1988-06-02 | Signal distinction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62139238A JPH07120985B2 (en) | 1987-06-03 | 1987-06-03 | Signal discrimination circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63302632A true JPS63302632A (en) | 1988-12-09 |
| JPH07120985B2 JPH07120985B2 (en) | 1995-12-20 |
Family
ID=15240685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62139238A Expired - Lifetime JPH07120985B2 (en) | 1987-06-03 | 1987-06-03 | Signal discrimination circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07120985B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61289738A (en) * | 1985-06-18 | 1986-12-19 | Sanyo Electric Co Ltd | Am stereoscopic receiver |
-
1987
- 1987-06-03 JP JP62139238A patent/JPH07120985B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61289738A (en) * | 1985-06-18 | 1986-12-19 | Sanyo Electric Co Ltd | Am stereoscopic receiver |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07120985B2 (en) | 1995-12-20 |
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