JPS63302492A - Sense amplifier circuit - Google Patents

Abstract

PURPOSE:To obtain the compatibility of the possession of a noise margin with an optimum level and the fast detection of a signal, by correcting the bias of an input signal by superposing a potential difference on the input signal when the input level of a sense amplifier circuit is biased to one side. CONSTITUTION:An offset voltage is supplied to the input terminal of a first inverter circuit 10 during the reset operation of the first inverter circuit 10 by supplying a logical threshold value different from that of the first inverter circuit 10 to a second inverter circuit 11 which feeds back the output of the first inverter circuit 10 to the input of the circuit 10. In such a way, it is possible to obtain the sense amplifier circuit in which the compatibility of the possession of the optimum noise margin without generating malfunction and the fast detection of the signal can be obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a sense amplifier circuit, and in particular to a sense amplifier circuit that performs high-speed amplification and reliable (no malfunction) detection in a single bit line readout type memory. It is related to.

[Prior Art] CMO3 type static memory with so-called single bit line readout method CMO3 type static memory with dual bit line readout method which is often used It has the advantage of being small in size. but,
Since there is only one bit line for each column of memory cells, a differential detection method cannot be used unlike the dual bit line method, which has two bit lines for each column of memory cells. This has made it difficult to design a sense amplifier circuit for accurately amplifying and detecting signals read from memory cells.

As a specific example of the structure of a single-bit line readout memory with a built-in sense amplifier circuit according to the conventional method, R,
Memory by J, IIollingsworth et al.
EEE, Journal of 5olid-5ta
tes C1rcuits.

Vol, 13. No. 5.1978. p, 866)
is shown in Figure 4.

The memory shown in FIG. 4 has an inverter circuit 10.11.
and a memory cell 201 (202, 203, 204, . . . ) consisting of an N-type MOS transistor 12, a row selection circuit 120, a column selection circuit 130, and a write circuit 1.
10, and a sense amplifier circuit 100 consisting of a P-type MoS transistor 1 and an N-type MOS transistor 2.3.

Next, the operation of this memory will be explained. Row selection circuit 120
If we consider a case where the row connected to node a is selected by and the column connected to bit line d is selected by column selection circuit 130, both row selection transistor 12 and column selection transistor 13 become conductive. , the information stored in the memory cell 201 is transmitted to the sense amplifier circuit 10 via the bit line d, the transistor 13 and the node e.
0 input terminal (node Tl). In addition, in the sense amplifier circuit 100, as shown in FIG. 6, a voltage is applied to the terminal (node T3) to make the reset transistor 3 conductive for a certain period of time prior to the detection of a signal. is erased, and then a voltage that makes the reset transistor non-conductive is applied to node T3, thereby performing an amplification action thereafter.

In FIG. 6, from a state where node Tl is at high level, node a is selected, first bit line C is selected and memory cell 204 (low level) is read, then bit line d is selected and the memory cell 201 (high level) indicates a read state.

Next, the operation of the sense amplifier circuit 100 will be explained using the voltage/current characteristics shown in FIG. This figure shows the voltage/current characteristics when looking at the memory cell, bit line, or sense amplifier circuit from each node in the block diagram shown in FIG. 4.

First, the characteristics when looking at the memory cell 201 from the node m are shown at 51 and 52. 51 is a case where the data in the memory cell is at a low level, and 52 is a case where the data in the memory cell is at a high level. Characteristics 53 and 54 show the characteristics when the memory cell 201 is viewed from the node e through the MO5I transistor 13 and the bit line d. 53 and 54 correspond to 51 and 52 respectively, 53 is a low level memory data, 54 is
is when the data in memory is at a high level. The currents shown at 53 and 54 are reduced compared to the currents shown at 51 and 52, which is due to the MOS transistors 12 and 13 in FIG.
This is due to the series resistance of . Note that in the characteristic indicated by 54, the voltage v1 at which the current begins to flow is lower than the power supply voltage VOO because of the substrate bias effect of the MOS transistors 12 and 13. 55 shows the characteristics of the sense amplifier circuit 100 when the reset transistor 3 is in a conductive state as viewed from the node T1.

Here, the operating points of the sense amplifier circuit 100 shown in FIG. 7 will be explained with reference to FIG. When the reset transistor 3 of the sense amplifier circuit 100 is in a non-conductive state, the human power node T of the inverter circuit consisting of the MOS transistors 1.2
The voltage transfer characteristics of the pair of output nodes T2 are as shown in FIG.
The definition of the logical threshold is given below by equation (5)), and the transfer characteristic shows a sudden change. In the sense amplifier circuit 100, when the reset transistor 3 is made conductive, the input and output voltages become almost equal and reach equilibrium, but this voltage is shown at the intersection of the 45° dashed line and the transfer characteristic shown in FIG. 8, and the logical threshold value V
Matches TL.

The voltage at which characteristic 55 shown in FIG. 7 intersects the horizontal axis is also the logic threshold shown in FIG. Now, the voltages at which characteristics 53 and 54 intersect with characteristic 55 are the low level and high level signal voltages (of the memory cell) applied to the sense amplifier circuit 100 when the reset transistor 3 is conductive, and are represented by symbols VSO and VSI. shown. The potential difference between VSO and VSI is the voltage V generated in the memory cell. and V,
The difference is usually at a small level of 1/10 or less. One of the roles of the sense amplifier circuit is to control this small level (Vs+
-Vso) to the level of the memory cell at high speed.

As a second specific example of the conventional sense amplifier circuit, K
, Sense Amplifier Circuit by Goster et al. (IEEE.

Journal of 5solid-5tate C1
rcuits, Vol. 5, 1972゜p, 325)
is shown in Figure 5.

This sense amplifier circuit includes P-type MOS transistors 1,
4 and an N-type MOS transistor 2°3.5. In addition to the sense amplifier circuit shown in Figure 4, this is a so-called flip-flop circuit in which an inverter circuit consisting of 4.5 MoS transistors is provided, and the output of one inverter circuit is connected to the power of the other inverter circuit. ing. This circuit amplifies the minute signal level applied to the input terminal T1 with a two-stage inverter circuit, and feeds back the output to the input terminal T1.
This enables faster signal detection than the sense amplifier circuit shown in FIG. In this case as well, the voltage obtained by making the reset transistor 3 conductive and balancing the input and output terminals is shown in the voltage transfer characteristic of Fig. 8 used to explain the sense amplifier circuit shown in Fig. 4. It will be the same as the value.

[Problems to be Solved by the Invention The cosense amplifier circuit is capable of receiving weak high-level or low-level signals applied from memory cells to the input terminal of the sense amplifier circuit stably without being affected by noise. Also, ■High-speed amplification and detection functions are required. However, in conventional sense amplifier circuits, it has been difficult to satisfy both of the above two terms.

Before explaining the shortcomings of the prior art, the properties of MoS transistors will first be explained using a simple equation.

For example, the P-type Mos transistor and N
The relationship between the voltage and saturation current of a type MOS transistor is given by the following equation.

μ,・WP'C0X Ip'' (Voo -Va -VTP)
2 (1) μN'WN'C0X IN = (VG VTN) 2 (2) Here, I: Current flowing through the MOS transistor, μ: Mobility of carriers in the MOS transistor, W: Channel width of the MOS transistor, L : channel length of MOS transistor, Cox: capacitance of gate oxide film of MOSl-transistor, VG: gate voltage of MOS transistor, Va: MOS
The threshold voltage of the transistor, Voo: voltage rA, where the subscripts P and N indicate the case of a P-type MOS transistor and an N-type MOS transistor, respectively. μ is a physical constant and has the following relationship.

W, GoX+L, and vT are structural constants of individual transistors, but COX and L are usually equal for P-type and N-type, and only W and vA are included in the design.

The logical threshold value vTL of the CMOS inverter circuit already shown in FIG. 8 is defined as the gate voltage when the current given by equations (1) and (2) are equal to ■8, and it becomes . Here, .

Next, the relationship between noise margin and speed in the sense amplifier circuit as shown in FIG. 4 will be explained using equations (1) to (6) and FIG. 7. First, sense amplifier circuit 1
In order to prevent the sense amplifier circuit from operating incorrectly, it is desirable that the high-level human input signal and the low-level human input signal applied at the time of reset have equal noise margins, that is, have an appropriate noise margin. The VTL shown in the figure is located between VSO and VS+ (center).
This is achieved by placing the Also, this means that VTL is vl and ν.

It is almost equivalent to placing it in the middle of (-OV). This relationship is shown by modifying equation (5).

β=(−上と塡−−”) ' (7) voo−
vTp -vTp Here, to show specific examples of the voltage values shown in FIG. 7, Vl-3V, VO-GV, VTP-VTN-I
V, VDD-5V.

3+0 VTL--1,5V Tonal. Therefore, in order to obtain an appropriate noise margin at reset in the sense amplifier circuit 100, P-type MO3)
- It is necessary to make the channel width of the transistor extremely small, which is 3725 mm, which is the channel width of the N-type MOS transistor.

On the other hand, the load driving power of the transistor is (1), (2
) is proportional to μXW as shown in the equation. Therefore, from the viewpoint of speed, it is desirable to set β shown in equation (6) to 1 so that the driving power of the P-type MOS transistor and the driving power of the N-type MOS transistor are made equal.

In other words, β determined from the viewpoint of the desired noise margin is approximately one order of magnitude different from β determined from the viewpoint of speed (high-speed amplification/detection).
It is clear that it is difficult to achieve both noise margin and speed with the sense amplifier circuit shown in the figure.

In addition, in the second conventional sense amplifier circuit shown in Fig. 5, since feedback is applied to human power, the first
Although faster detection is possible than in the example (FIG. 4), it is not possible to obtain an appropriate (sufficient) noise margin at the time of reset (state). The reason is as follows.

That is, FIG. 9 shows the concept of the second example sense amplifier circuit shown in FIG. 5, and is expressed by two inverter circuits 10 and 11 and a reset switch 31. In addition, the two inverter circuits 10 and 11 are composed of transistors having the same conditions (that is, they constitute a balanced flip-flop circuit), and as shown by curves 42° and 43 in FIG. Equal voltage transfer characteristics are exhibited at node T2.

The point where the two transfer characteristics intersect, ie, the 0 point, is a metastable point that provides a measure of the stability of the operation of the sense amplifier circuit.

Further, the operating point when the switch of the reset circuit shown in FIG. 9 is closed in an ideal state where no input voltage is applied from the memory cell is indicated by point Q. In this case, since nodes T1 and T2 are forcibly short-circuited, the voltage at node T1 and the voltage at node T2 reach equilibrium during the reset period, and Q
It converges to a point indicated by a dot. Moreover, this point is on the 45° straight line as shown in FIG. 1O. In this case, the Q point and the 0 point match.

Next, consider a case where a voltage from a memory cell is applied to a sense amplifier circuit in a reset state.

Symbol v0. shown in FIG. 1O. The voltage values indicated by v, +vSO+vSl are the same as those shown in FIG. That is, the high level output V of the memory cell gives a level shown by vsl to the human power of the sense amplifier circuit in FIG. 5, which corresponds to the operating point shown by point A on the transfer characteristic diagram in FIG. 1O. Similarly, the low level output v0 is . A level shown by is applied to the human power of the sense amplifier circuit shown in FIG. 5, which corresponds to operating point B. This voltage vS O* V S I is
The impedance of the sense amplifier circuit in the reset state,
It is determined by the ratio to the series impedance of the memory cell, row selection switch, and column selection switch transistors. Generally, vo and V.

The relationship between Vl and VSI is as shown in FIG. 1O. This is because the impedances of the row selection switch and column selection switch transistors are higher when the signal from the memory cell is on the high level side than when it is on the low level side.

Next, the noise margin will be explained. First, at least 2 is surrounded by the curves 42 and 43 that intersect at the 0 point mentioned earlier.
The existence of points A and B in each of the two closed curves (denoted by CDE and CFG) is necessary to ensure reset operation, but on the other hand, points A and B are relative to zero point. in an asymmetrical position. Therefore, the potential difference between point A and point 0, which is closer to point 0, is smaller than the potential difference between point B and point 0, and the noise resistance is determined by this smaller value (potential difference between point A and point 0). It will be decided. Therefore, even in the sense amplifier circuit of FIG. 5, the problem of noise margin is still unsolved.

An object of the present invention is to overcome the drawbacks of the conventional method as described above, that is, to overcome the inability to ensure an appropriate noise margin and high-speed signal detection at the same time.

[Means for Solving the Problems] The present invention includes a first inverter circuit that manually inputs a signal from a memory cell, and a reset switch that resets the first inverter circuit by making the input and output terminals of the first inverter circuit conductive. , having an output end of the first inverter circuit as an input end, and an output end connected to the input end of the first inverter circuit,
a second inverter circuit that has a logic threshold different from that of the first inverter circuit and applies an offset voltage to the input terminal of the first inverter circuit during a period in which the reset switch is conductive; .

[Function] According to the present invention, the first inverter circuit feeds back the output of the first inverter circuit to the input of the circuit.
By providing a logic threshold different from the logic threshold of the inverter circuit, an offset voltage is applied to the input terminal of the first inverter circuit during the reset operation of the first inverter circuit to ensure appropriate noise margin and high-speed operation. .

[Embodiment 1] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a first embodiment of a sense amplifier circuit according to the present invention.

The first embodiment includes an inverter circuit 10 consisting of a P-type MoS transistor 1 and an N-type MoS transistor 2 whose drains are connected together, and an inverter circuit consisting of a P-type MOS transistor 4 and an N-type MOS transistor 5 whose drains are also connected together. The input of the inverter circuit IO is connected to the node Tl, the output of the circuit 10 is connected to the node T2 and the input of the inverter circuit 11, and the output of the inverter circuit 11 is connected to the node Tl, A MOS transistor (reset transistor) 3 is connected between nodes T1 and 12, an N-type MOS transistor 6 (details will be described later) is connected between node T2 and the negative power supply, and a P-type MOS transistor (reset transistor) 3 is connected between nodes T1 and 12. ) is connected between the positive power supply and node T1.

This configuration will be explained in more detail. MOS transistor 1
, 2, 4.5 constitute a flip-flop circuit, and this flip-flop circuit is reset when the MoS transistor 3 becomes conductive. In addition, MoS transistors 1 and 4 and 2 and 5 form a balanced flip-flop circuit, and the part in which the reset transistor 3 is added has the same configuration as the sense amplifier circuit of the second example of the conventional method. (i.e. these transistors 1°2.3,
4.5 alone, the characteristics shown in Fig. 1θ can be obtained).

The feature of the present invention is that MOS is used in such a sense amplifier circuit.
By adding the transistors 6.7, the two voltage transfer characteristics (logical thresholds) of the two inverter circuits forming the flip-flop circuit are made different from each other.

That is, conceptually, the sense amplifier circuit according to the present invention, as shown in FIG. 11, is a means for generating a potential difference vS in a balanced flip-flop circuit and a reset circuit consisting of two inverter circuits (details will be described later). is added. Thereby, when the human power level of the sense amplifier circuit is biased to one side, this potential difference vS is superimposed on the human power signal, making it possible to correct the bias in the human power signal. This requires (in order to obtain an appropriate noise margin) that the logic threshold of the inverter circuit that makes up the flip-flop circuit is significantly different from the logic threshold of the two inverter circuits that make up the balanced flip-flop circuit. Therefore, high-speed signal detection is possible.

That is, compared to the two logic thresholds shown in FIG. 10, the logic threshold vTL1 of one inverter circuit 10 is slightly shifted to the lower level side as shown in FIG. Slightly shift the logic threshold VTL2 to the high level side. By reversing the directions in which the logical thresholds are shifted in this way, by slightly shifting the two logical thresholds, the metastable point C can be greatly shifted and placed midway (center) between points A and B. Therefore, an appropriate noise margin can be secured.

As shown in FIG. 12, compared to FIG.
is shifting to As a result, the metastable point C where the two intersect
will no longer lie on the 45° straight line.

In an ideal state where the memory cell is disconnected and no input voltage is applied to the sense amplifier circuit, the operating point when the reset switch is closed is on the 45° line and is given by Q. The potential difference between the Q point and the 0 point corresponds to the potential difference vS in FIG. 11, and this becomes the offset voltage.

Next, the operation of this sense amplifier circuit will be explained.

The high level output v1 of the memory cell gives a level indicated by Vlil to the sense amplifier input, which corresponds to point A on the transfer characteristic diagram. Similarly, the low level output v0 is VSO
The operating point B is given through . The major difference compared to FIG. 10 is the magnitude relationship between point Q and point 0. In other words, since the Q point is shifted toward the high level side with respect to the 0 point, even if the high level input to the sense amplifier circuit is biased toward the low level side, this is corrected and the operating point is symmetrical with respect to the 0 point. B and A can be given.

Furthermore, in comparison with FIG. 1O, in FIG. 12, as mentioned above, it is only necessary to shift VTL l and VTL2 slightly in the direction of mutually opposite levels, so the metastable point indicated by the 0 point is the inverter circuit's metastable point. Voltage that ensures high speed performance, that is, V
It is possible to take it near dd/2.

The first embodiment applies the above concept, and then provides a quantitative explanation with a logical threshold (5)
Or, it will be explained using equation (7). The first example is %
In order to shift the logic thresholds of two inverter circuits to opposite levels (to make them different), another transistor is added to one of the pair of transistors that make up the inverter circuit, and the The channel widths are different. That is, for this purpose the first
As shown in the figure, in one inverter circuit 10, another transistor 6 is connected to the N-type MOS transistor 2.
In the other inverter circuit 11, the P-type MOS l-
Add another transistor 7 to transistor 4. By doing so, the present invention is characterized in that β of the inverter circuit is changed by a minute amount. Therefore, is derived.

A second embodiment of the sense amplifier circuit according to the present invention will be described with reference to a pattern diagram shown in FIG.

The second embodiment includes an inverter circuit 10' consisting of a P-type MOS transistor 1'' and an N-type MOS transistor 2° whose drains are connected together, and an inverter circuit 10' consisting of a P-type MOS transistor 4° and an N-type MOS transistor whose drains are connected together.
The input of the inverter circuit 10° is connected to the node Tl', the output is connected to T2' and the human power of the inverter circuit 11°, and the output of the inverter circuit 11' is connected to the node T1'. node T,
and connect the MOS transistor 3 to the node Tl.
° and T2°.

This configuration will be explained in more detail. MOS transistor 1
degrees, 2 degrees, 4 degrees, and 5 degrees constitute a flip-flop circuit, and this flip-flop circuit is reset when MOS1-transistor 3 degrees conducts. However, as shown in the figure, the channel width of the P-type MOS transistor 4° is
The channel width of the N-type MO3I transistor 2° is wider than the channel width of the S transistor 1′, and the channel width of the N-type MO3I transistor 2° is wider than the channel width of the N-type MOS transistor 5°.

Next, it will be shown that the second embodiment is completely equivalent to the first embodiment in terms of an equivalent circuit. As shown in equations (1) and (2), the current of the MOS transistor is proportional to the channel width W. For example, the P-type MO5 transistor 1. shown in FIG.
4.7 channel widths WP++”P4.Wp7 respectively
Then, the channel width of transistors 4 and 7 connected in parallel is WP4+WP? can be replaced with one transistor equal to . Therefore, the transistor l', 4 in FIG.
' channel widths are WP+, WP4+WP7, respectively.
(N-type MoS transistors 2, 6.5 and 2
5°), the second embodiment becomes completely equivalent to the first embodiment. Therefore, the formula (lO) is also applied to this second embodiment.

A third embodiment of the sense amplifier circuit according to the present invention will be described with reference to FIG. The third embodiment is constructed with exactly the same circuit connections as the second embodiment. However, in this case, the threshold voltage of the P-type MoS transistor 4'' is set lower than the threshold voltage of the P-type MOS transistor 1°, and the threshold voltage of the N-type MOS transistor 2'' is set to N. The threshold voltage is set lower than the threshold voltage of a 5° type MOS transistor. The threshold voltage can be easily controlled by the usual method of changing the impurity concentration in the channel region of the MOS transistor.

The operation of this configuration will be explained. As shown in equations (1) and (2), lowering the threshold voltage VT of the MOS transistor increases the current value. Therefore, the effects of the second and third embodiments are almost the same, but the difference is that in the second embodiment, the current changes linearly with changes in the channel width, whereas in the third embodiment, the current changes linearly with respect to changes in the channel width. In this embodiment, the current varies proportionally to the square of the threshold change.

Next, since the third embodiment corresponds to changing the threshold value vTP+VTN of the MOS1- transistor by a minute amount in order to shift the logical threshold values of the two inverter circuits, the following equation is derived.

This will be explained more specifically using the formula (lO).

VtL-Voo/2. VTP-TTN-IV, VD
Assuming that D-5V and shifting the logical threshold by 0.1v, Δβ=0.26 from equation (12). Since VTL is set near Voo/2, it becomes βLr1, and as already mentioned, P-type MO3)-transistor and N-type M
The speed balance of the oS transistors has been ensured. Then, if β of one of the two inverter circuits is increased by 26% and β of the other is decreased by 26% with β=1 as the center, an operating point with a sufficient noise margin can be obtained.

This will be specifically explained using the same formula (11). β=1
And when shifting the logical threshold by 0.1v,
ΔTP−ΔTN=0.2V. That is, β=1
Therefore, while balancing the speeds of the P-type MOS1 transistor and the N-type MOS transistor, the threshold value of the P-type MO3) transistor constituting one inverter circuit is lowered by 0.2V, and the N of the other inverter circuit is also lowered by 0.2V. Type MO
By lowering the threshold value of the S transistor by 0.2V, an operating point with a good noise margin can be secured.

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide a sense amplifier circuit that achieves both of ■Securing an appropriate noise margin (without fear of malfunction) and ■High-speed signal detection. can.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing a first embodiment of the sense amplifier circuit according to the present invention, FIG. 2 is a pattern diagram of an integrated circuit showing a second embodiment of the sense amplifier circuit according to the present invention, and FIG. The figure is a pattern diagram of an integrated circuit showing the third embodiment of the sense amplifier circuit according to the present invention, and FIG. FIG. 5 is a logic circuit diagram showing a second example of the sense amplifier circuit according to the conventional method; FIG. 6 is a signal waveform diagram for explaining the operation of the sense amplifier circuit shown in FIG. 4; The figure is a voltage/current characteristic diagram for explaining the operation of the memory sense amplifier circuit shown in Figure 4, and Figure 8 is a CMOS
Figure 9 is a conceptual diagram of the sense amplifier circuit shown in Figure 5. Figure 1O is a diagram explaining the operation of the sense amplifier circuit shown in Figure 9. 11 is a conceptual diagram of the sense amplifier circuit shown in FIG. 1, and FIG. 12 is a diagram for explaining the operation of the sense amplifier circuit shown in FIG. 11. 1.4, 7, 1°, 4°, 4"...P-type MOS transistor, 2.3, 5, 6.2', 3°, 5°, 1
2.13... N-type MOS transistor, T, , TI'... input terminal, T2, T2°... output terminal, T3. T3°...Reset terminal, VDD, vss...Power supply terminal, 10.11.10', 11"...Inverter circuit,
100...Sense amplifier circuit, 110...Write circuit, 120...Row selection circuit, 130...Column selection circuit, 201.202.203.204...Memory cell, 4
1.42, 43, 44.45 --- Voltage transfer characteristics of CM OS inverter circuit, VTL, VTL,, VTL2- CM OS inverter circuit'llr logic IN threshold, 51.52...4th Voltage/current characteristics as seen from the node m of the memory cell shown in the figure, 53.54... Voltage/current characteristics seen from the memory cell side from the node e shown in Fig. 4, 55... Shown in Fig. 4 Voltage/current characteristics of the sense amplifier circuit viewed from node T, VSO+V! 11... Voltage applied to the input terminal of the memory cell, 31... Reset switch, 32... Voltage source, A, B... Operating point applied to the sense amplifier circuit, C
...Equilibrium point of the sense amplifier circuit, Q...Operating point at reset of the sense amplifier circuit.

Claims (1)

[Claims] A first inverter circuit that inputs a signal from a memory cell; and an input/output terminal of the first inverter circuit that is connected to the first
a reset switch that resets the inverter circuit; and an output end that takes the output end of the first inverter circuit as an input end and is connected to the input end of the first inverter circuit, and has a logic threshold of the first inverter circuit. a second inverter circuit that has a logic threshold different from the value and applies an offset voltage to the input terminal of the first inverter circuit during the period when the reset switch is conductive. amplifier circuit.