JPS63301619A - Pre-drive circuit - Google Patents

Abstract

PURPOSE:To prevent the heating damage of a field effect transistor by providing an electric potential shift means between a transistor for an input signal impressing and the gate of the field effect transistor. CONSTITUTION:Between a transistor Q5 for an input signal impressing and the gate of field effect transistor Q3, an electric potential shift means VS to keep the electric potential of this gate lower than the electric potential of the transistor Q5 for the input signal impressing is provided. Thus, when the transistor Q5 for the input signal impressing is closed and the collector electric potential of the transistor Q5 for the input signal impressing is not even reduced enough, the field effect transistor Q3 is closed and does not stop in a positive area and the field effect transistor Q3 is not heated and damaged, either.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a predrive circuit that supplies power to a pulse transformer, etc., which is a component of a switching regulator, a DC/DC converter, etc.

In particular, the present invention relates to improvements in preventing overheating of field effect transistors constituting the predrive circuit when used in the active region.

[Prior art] An example of a switching regulator according to the prior art is shown in the second example.
This will be explained with reference to the figures.

In the diagram shown in FIG. 2, T is a pulse transformer, and in this example, the primary winding is divided into a first winding Wl and a second winding W2, the polarities of which are as shown in the figure. As in, they are mutually inverted. Further, W3 is a secondary winding, which outputs an output through a parallel circuit of a capacitor CI and a resistor R1, and opens and closes a bipolar transistor Q1 that serves as a load.

Q3 is an N-channel enhancement field effect transistor feeding the first winding Wl, its drain Q3D is connected to one terminal of the first winding W1, its source Q3S is grounded, and its gate Q3G is Resistor R3
It is connected to the power supply (1) via - and also to the collector Q5G of the input signal application transistor Q5 which provides an input signal to this switching regulator. The power supply V is connected to the other terminal of the first winding W1 Q2
is an NPN bipolar transistor feeding the second primary winding W2, its collector Q2C is connected to one terminal of the second primary winding W2, and its emitter Q2E is grounded via a diode D3. There is. The other terminal of the second primary winding W2 is connected to iav. The base Q2B of transistor Q2 is connected to the emitter Q5E of transistor Q5. Note that the base Q2B of the transistor Q2 is grounded via the resistor R4, and at the same time, the base Q2B of the transistor Q2 is connected to the drain Q3D of the field effect transistor Q3 via the diode D2, and the collector of the transistor Q5 is connected to the drain Q3D of the field effect transistor Q3 via the diode D2. Q5
C is connected to collector Q2C of transistor Q2 via diode D1.

When the input signal applying transistor Q5 is open, the power supply voltage V is applied to the gate Q3G of the field effect transistor Q3, the field effect transistor Q3 is closed, and the first winding W1 is not supplied with power. , a voltage is generated in the direction of the dashed arrow in the secondary winding W3, and the load transistor Q1
is open.

When the input signal application transistor Q5 is closed, a low voltage is applied to the gate Q3G of the field effect transistor Q3, the field effect transistor Q3 is opened, and the first winding W1 is not supplied with power. , the base Q2B of the bipolar transistor Q2 is supplied with a current determined by the resistors R3 and R4, the base-emitter resistance of the transistor Q2, and the forward resistance of the diode D3, so that the transistor Q2 is closed and the second primary winding is Power is supplied to the line W2, a voltage is generated in the direction of the solid arrow in the secondary winding W3, and the load transistor Q1 is closed.

When the input signal application transistor Q5 is closed, the base IT current of the bipolar transistor Q2 tries to flow as described above, but the field effect transistor Q3 remains in the closed state until its gate potential drops sufficiently, so the diode D2 The current flows through the field effect transistor Q3 through the diode D2, the base current of the transistor Q2 is limited, and the transistor Q2 is not closed. field effect transistor Q3
The current flowing through the transistor Q2 is stopped, the base current is supplied to the base of the transistor Q2, and the transistor Q2 is closed. As a result, transistor Q2 and field effect transistor Q3
and cannot be closed at the same time.

On the other hand, when the input signal application transistor Q5 is opened, the transistor Q2 is opened with a delay of M product time after the base current stops, and the transistor Q2 remains closed until then. During that period, a current flows through the diode D1, so the potential of the gate Q3G of the field effect transistor Q3 does not rise moderately, and the closing of the field effect transistor Q3 is delayed. As a result, transistor Q2 and field effect transistor Q3 are never closed at the same time.

[Problems to be Solved by the Invention] In particular, when the input signal applying transistor Q5 is closed, the collector-emitter resistance of the transistor Q5 is such that it cannot sufficiently lower the potential of the gate Q3G of the field effect transistor Q3. If it is large, current flows through the field effect transistor Q3 via the first winding W1. In this state, since the field effect transistor Q3 is in the active region, its source/drain resistance is neither zero nor infinite, so it generates a large amount of heat and may be damaged.

An object of the present invention is to eliminate this drawback, and to provide an improvement in a predrive circuit including the above-mentioned circuit to eliminate the risk of overheating when the field effect transistor constituting the circuit is used in the active region. It is about providing.

[Means for solving problems]

The above purpose is to output output signals having mutually different polarities to the secondary side of the pulse transformer (T) in response to an input signal applied by the open/close state of the input signal applying transistor Q5, and to The primary winding of the transformer (T) is
The first winding (W1) is divided into a first winding (W1) and a second winding (W2) having different polarities, and the potential of the gate Q10 of the first winding (W1) is equal to the input voltage. When the signal applying transistor Q5 is in an open state, it has a high potential, and its source Q
3S is supplied with power through the drain Q3D of the N-channel enhancement field effect transistor Q3 which is grounded, and the second winding (W2) is conductive when the input signal application transistor Q5 is in the closed state, and the emitter 92
E is a predrive circuit that is supplied with power via the collector Q2C of the grounded bipolar transistor Q2, and the input signal applying transistor Q5 and the N
Channel enhancement field effect transistor Q
This is achieved by a predrive circuit in which a potential shift means (VS) is interposed between the gate Q3G and the gate Q3G to keep the potential of the gate 93G lower than the potential of the input signal applying transistor Q5.

[Effect]

The cause of the above drawback is the input signal application transistor Q5.
Even if the transistor Q5 is closed, if the emitter-collector resistance of the transistor Q5 is large, the gate potential of the field effect transistor Q3 will not drop sufficiently.

In the present invention, a potential shift means vS is interposed between the input signal application transistor Q5 and the gate Q3G of the field effect transistor Q3 to maintain the potential of the gate Q10 lower than the potential of the input signal application transistor Q5. Therefore, when the input signal applying transistor Q5 is closed,
Even if the collector potential of the input signal applying transistor Q5 does not drop sufficiently, the field effect transistor Q3 will not open and remain in the active region, and there is no risk of the field effect transistor Q3 being overheated and damaged.

〔Example〕

Hereinafter, a predrive circuit according to an embodiment of the present invention will be further explained with reference to the drawings.

In the diagram shown in FIG. 1, T is a pulse transformer, and in this example, the primary winding is divided into a first winding Wl and a second winding W2, the polarities of which are as shown in the figure. As in, they are mutually inverted. Further, W3 is a secondary winding, which outputs an output via a parallel circuit of a capacitor C1 and a resistor R1, and opens and closes a bipolar transistor Ql that serves as a load.

Q3 is an N-channel enhancement field effect transistor that supplies power to the first winding Wl, its drain Q3D is connected to one terminal of the first winding W1, its source Q3S is grounded, and its gate 93G is connected to the power supply v via the potential shift means vS and the resistor R3 according to the gist of the present invention, and is also connected to the collector Q5C of the input signal applying transistor Q5 which provides an input signal to this switching regulator. has been done. The potential shift means vS may be a battery or the like, but in this example, a circuit is used in which a resistor R5 whose other end is grounded is connected to one end of a parallel circuit of a Zener diode ZD and a capacitor C2. There is. In this potential shift means ■S,
During the period when transistor Q5 is open, capacitor C
2 is charged to the Zener voltage of the Zener diode ZD, and when the transistor Q5 is closed, the gate voltage of the field effect transistor Q3 is the same as that of the transistor Q5.
It is the value obtained by subtracting the above Zener voltage from the collector voltage of , and has the function of shifting the voltage. Power supply■
is connected to the other terminal of the first winding W1.

Q2 is an NPN bipolar transistor feeding the second primary winding W2, its collector Q2C is connected to one terminal of the second primary winding W2, and its emitter Q2E
is grounded via diode D3. The other terminal of the second primary winding W2 is connected to the power supply ■. The base of transistor Q2 is the emitter Q of transistor Q5.
Connected to 5E. Note that the base Q2B of the transistor Q2 is grounded via a resistor R4, and the drain Q2 of the field effect transistor Q3 is connected via a diode D2.
3D, and the collector Q of transistor Q5
5C is connected to the collector Q2C of transistor Q2 via diode D1.

When the input signal applying transistor Q5 is open, a voltage f1 is applied to the gate Q3G of the field effect transistor Q3.
1! A voltage obtained by subtracting the voltage of the potential shift means ■S from the voltage is applied, and the field effect transistor Q3 is closed, and the first winding! ! Power is supplied to Wl, and a voltage is generated in the secondary winding W3 in the direction of the dashed arrow, so that the load transistor Q1 is opened.

When the input signal applying transistor Q5 is closed, a voltage obtained by subtracting the voltage of the potential shift means ■S from the collector voltage of the transistor Q5 is applied to the gate Q3G of the field effect transistor Q3, and the field effect transistor Q3 is opened. Therefore, no power is supplied to the first winding W1, while the base Q2B of the bipolar transistor Q2 is connected to the resistors R3 and R4, the base-emitter resistance of the transistor Q2, the forward resistance of the diode D3, and the collector- A current determined by the emitter resistance is supplied to close the transistor Q2, and the second primary winding W2
is supplied with power, a voltage is generated in the direction of the solid arrow in the secondary winding w3, and the load transistor Q1 is closed.

In particular, even if the input signal applying transistor Q5 is closed, if the collector-emitter resistance of the transistor Q5 is large, the collector potential will not be sufficiently lowered, and therefore the potential of the gate Q3G of the field effect transistor Q3 will not be lowered sufficiently. In this embodiment, potential shifting means is interposed between the input signal application transistor Q5 and the gate Q3G of the field effect transistor Q3 to maintain the potential of the gate Q3G lower than the potential of the input signal application transistor Q5. , even if the collector-emitter resistance of transistor Q5 is large, the gate potential of field-effect transistor Q3 becomes sufficiently low, field-effect transistor Q3 is completely opened, and does not remain in the active region, causing field-effect transistor Q3 to overheat. There is no risk of it breaking.

[Effects of the Invention] As explained above, in the predrive circuit according to the present invention, the gate Q3 is connected between the input signal applying transistor Q5 and the gate Q3G of the field effect transistor Q3.
Since there is a potential shift means that keeps the potential of G lower than the potential of the input signal application transistor Q5, when the input signal application transistor Q5 is closed, the collector potential of the input signal application transistor Q5 does not drop sufficiently. Even if the field effect transistor Q3 is opened, the field effect transistor Q3 will not remain in the active region, and there is no risk that the field effect transistor Q3 will overheat and be damaged.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a predrive circuit according to an embodiment of the present invention. FIG. 2 is a block diagram of a predrive circuit according to the prior art. VS... Potential shift means, Q5... Transistor for input signal application, Q3... Field effect transistor, Ql... Transistor, Q2... Bipolar transistor, Dl, D2, D3... Diode, R1 , R2,
R3, R4, R5...Resistor, C1, C2...Capacitor, ZD...Zener diode, T...Pulse transformer, Wl, W2, W3...Winding.

Claims (1)

[Scope of Claims] Output signals having mutually different polarities are output to the secondary side of the pulse transformer (T) in response to an input signal applied according to the open/close state of the input signal application transistor Q5, The primary winding of the pulse transformer (T) is divided into a first winding (W1) and a second winding (W2) having mutually different polarities. ) has its gate Q3G at a high potential when the input signal applying transistor Q5 is open, and its source Q3S is supplied with power through the drain Q3D of the grounded N-channel enhancement type field effect transistor Q3, The second winding (W2) is connected to the collector Q2 of the bipolar transistor Q2, which is conductive when the input signal applying transistor Q5 is closed, and whose emitter Q2E is grounded.
In the predrive circuit, the potential of the gate Q3G is connected between the input signal application transistor Q5 and the gate Q3G of the N-channel enhancement field effect transistor Q3. A predrive circuit characterized in that a potential shift means (VS) is provided to maintain the potential lower than the potential of the transistor Q5.