JPS63301610A - Variable attenuator - Google Patents

Abstract

PURPOSE:To improve an operation in a microwave frequency range by equipping a feedback circuit to feedback the output of a reference cell to the gate of the electric field effect transistor (FET) of an attenuating cell and the reference cell. CONSTITUTION:A reference attenuating cell 12 executes the feedback control of a main attenuating cell 10 through an operational amplifier 14 and this reference cell 12 is designed so as to be electrically equivalent with the attenuating cell 10 in a characteristic impedance. A control signal that an amplifier 60 outputs to an output conductor 38 is changed by an attenuation control signal impressed to the reference output signal of an NORD 44 and a control terminal 16. This control signal is fedback to the gate of a parallel FET 54 and controls a reference circuit operation and the impedance of the NORD 44 is made equal to that of a NORD 46. Since the same control signal is impressed to an FET 34, the attenuating cell 10 and the reference cell 12 are samely operated. Thus, regardless of the change of the attenuating quantity of an attenuator, since the characteristic impedance can be always maintained to be constant, the characteristic is stabilized over a wide range.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to variable attenuators, particularly field effect transistors (FE).
This invention relates to a wideband variable attenuator using T).

[Prior art and its problems] A variable attenuator is generally used to control the gain of a cascade amplifier. To obtain gain flatness (i.e. uniformity of gain over different frequencies) and stability of the amplifier,
This attenuator is related to the attenuation value (VSW of the source and load).
Preferably, R is low. It is also essential to maintain the impedance of the transmission line circuit constant. This precludes the use of reflective attenuators.

The classic bridge-T attenuator is described in the 5th edition of Radio Engineer's Reference Data published by ITT/Howard W. Sams & Company in 1968 and is shown in FIG. 7A. In this circuit, a continuously variable absorbing attenuator can be obtained by changing the series resistance R1 and the parallel resistance R2 so as to satisfy the following equation (1).

RIR2=202(1) where ZO is the desired characteristic impedance. The attenuation degree when matching is given by equation (2) = 201og
((R1/ZO)+1) (2) To make the bridge T-type attenuator a continuously variable type, the series-parallel resistance R shown in Figure 7A
1 and R2 operating in the linear region as shown in Figure 7B.
It would be better to make it ET.

However, in practice, conventional variable FET attenuators experience undesirable impedance changes as the degree of attenuation and operating temperature changes.

Another example of a variable attenuator is by R. Chattopadya et al.19
Proceedings RF Te'710, published in January 1986
XPO86, pages 573-574. This attenuator uses individual PIN diodes as variable resistors to provide an attenuator in the IMHz to 500MHz band. The product of RIR2 is an exponential function as shown in the following equation.

RIR2=1e (K lower IV++ Vz) where, K1
is a constant, T is temperature, and k is Portzmann's constant. This circuit is temperature sensitive and in practice even a constant such as 1 will vary depending on the device used. Additionally, complex active and inductive DC control circuits are required to control and bias the current through the diode. Finally, this circuit is unlikely to work over a wide microwave frequency range.

Gallium arsenide (GaAs) monolithic microwave integrated circuits (MMICs) have recently entered the market from the development stage. Most of the MMICS currently on the market are gain blocks, with some exceptions.

An example of MMICs is L-Larson et al., Proc., 1985.
IEEE GaAs ICSymp-19th~
"rGaAs Differential Amplifier", J. Bouhaus et al., Proc, 1981 IEEE GaAs IC, p.
"Monolithic Dual Cate GaAsFET Digital Phase Filters" in Symp, Paper 35, "A Novel Particularly Monolithic Approach to Microwave Power Amplifiers" in 1983 IEEE Microwave and Millimeter Wave Monolithic Circuits Symposium, pp. 54-58, in D. Publizois et al. March 1984 IEEE of Y., Ayasuri et al.
Trans, Microwave Theory
Tech, Vol, MTT-32 No. 290-2
"R2-20 GHz GaAs Traveling Wave Power Amplifier", p. 95, and Proc of Jones et al., 1985.
I EEE GaAsI CSymp, No. 137-1
“1 in Hermetic Surface Mount Package” on page 40
-10GHz Taper Distributed Amplifier”. Additional microwave "building blocks" are not yet commercially available, primarily because microwave designs are application specific and not general purpose. GaAs
Since MMI Cs have a wide range of applications and bands, standard functional MMICS must be carefully selected. Otherwise, the quantity of MMICs cannot be reduced to achieve low cost per unit, which is one of the main objectives of making circuits monolithic.

Therefore, there is a need for improved variable attenuators, particularly radio frequency variable attenuators that have substantially constant impedance and low return loss over a wide microwave frequency range.

OBJECTS OF THE INVENTION Accordingly, one object of the present invention is to improve the operation of variable FET attenuators, particularly in the microwave frequency range.

Another object of the invention is to minimize the temperature dependence of variable RF attenuators.

Still another object of the present invention is to reduce the dependence of the RF variable attenuator on variations in the parts used.

Another object of the invention is to provide an economical variable attenuator with a wide range of applications.

SUMMARY OF THE INVENTION The variable attenuator of the present invention uses feedback within the control loop to automatically compensate for human power/output return loss when varying the attenuator with a control signal input. In order to properly match the input to the desired attenuation value, the series and parallel variable FETs must be set to positive conductance. According to the invention, the second or reference attenuation circuit provides feedback control of the main attenuation circuit via an operational amplifier.

This reference circuit is designed to be electrically equivalent to the attenuation circuit in terms of characteristic impedance.

The control node and the attenuation control input/output form an operational amplifier,
The reference and main attenuation circuits are connected in parallel so that they operate similarly. This configuration eliminates the need for RF decoupling of the feedback loop from the attenuation circuit. If there is RF coupling, it will change the attenuator's S-parameters with undesirable results.

Preferably, the same circuit as the main attenuation circuit is used for the reference circuit. High precision matching is achieved when both of these circuits are fabricated on the same monolithic integrated circuit (IC) substrate along with the operational amplifier. The present invention is suitable for an attenuator using a bridge T-type variable attenuator, but a symmetric T-type or a symmetric π-type variable FET is suitable.
It may also be an attenuation circuit. A variable attenuator constructed in this manner provides excellent temperature compensation and automatic biasing of the gate voltages of the parallel FETs in both the reference and main attenuation circuits.

In a preferred embodiment, a wideband monolithic GaAs bridge-T variable attenuator is constructed as described above using on-chip GaAs with a characteristic impedance termination, but with a stability band of about 100 MHz, in combination with a similar reference circuit; Internal input/output return loss can be optimized over the -10 GHz band.

[Example] (Description of FET variable attenuator) Prior to explaining the present invention, a general FET variable attenuator will be briefly explained. The channel resistance of a linearly operated FET depends on the gate-source voltage vgs and is determined by approximately 1/Gm5at. Here, G m5at is the mutual conductance in the saturation region. The relationship between drain current Ids and drain voltage Vds is given by the following equation.

Ids=2β0 (Vgs -vp) Vd5W/L'
, Gm5atvds... (3) Here, W and L are the gate width and length of the FET, respectively, and Vp is the pinch-off voltage. For GaAsFETs, the transconductance parameter βO is given approximately by μes/2a, where μ is the channel electron mobility and es is the GaAsFET.
s is the dielectric constant, and a is the channel thickness data. (3
), channel resistance Vds/I ds is GaA
It can be seen that it depends on βO and Vp for the process of s.

The next task is to control the product of the series and parallel channel resistances to achieve the correct attenuation behavior.

To maintain the correct return loss at any degree of attenuation for FETs with equal characteristics, the GaA
The following relationship is required between the voltages applied to the s FETs, ie the series and parallel gate voltages Vgsl and Vgs2.

The attenuation of the column and parallel FETs is given by:

Feedback can be used to control input/output return loss when varying attenuation, regardless of variation.

Next, a description will be given based on a preferred embodiment of the present invention shown in FIG. The figure shows a combination of a bridge T-type attenuator cell 10, a reference attenuation cell 12, and an operational amplifier 14. (Input protection and level shifting circuits for control inputs are not shown.

) The parallel FE of the attenuation cell is arranged so that the impedance for the RF input and output signals of this circuit is, for example, 50Ω.
The gate voltage of T is adjusted according to the gate data voltage change of the series FET.

This circuit has an attenuated signal input 16. This input terminal 1
6 is coupled to the gate of series FET 20 via resistor 18 of damping cell 10. The source and drain of series FET 20 are connected to the RF input/drain via series capacitors 26 and 28.
It is symmetrically connected to output terminals 22-24. These capacitors are for DC blocking, and the circuit performs appropriate level shifting (not shown) to enable operation with a single power supply. To extend the frequency band to low frequencies, these capacitors may be removed. A pair of 50Ω resistors 30-32 are connected from the source and drain of series FET 20 to the drain of parallel FET 34, respectively. Parallel FE
The source of T34 is connected to ground or a suitable reference voltage source (hereinafter referred to as ground). The attenuation cell 10 in this example has 50
have the same input/output impedance of Ω. parallel FET
The gate of 34 is connected to a control signal line 38 via a resistor 36. As discussed below, a control signal is applied via signal line 38 to the gate of parallel FET 34 to control its conductance in response to changes in the attenuator control signal. resistance 1
8 and 36 are for RF attenuation of FETs 20 and 34,
There is no other significant effect on the operation of this attenuation circuit.

Reference (attenuation) cell 12 preferably has the same manpower/power impedance as variable attenuation cell 10 and is configured to be electrically equivalent.

Ideally, this reference attenuation circuit 12 has the same configuration as the main attenuator, and the parameters of the parts used are also the same. The gate of the series FET 40 is connected to the control signal input terminal 16,
The source and drain are connected to nodes 42 and 44, respectively. A pair of 50Ω resistors 50-52 are connected in series to each FET.
40 source node 42 and drain node 44 and parallel FET 54. The source of FET 54 is connected to ground or a suitable reference voltage source, and its gate is connected to control line 38. The source of series FET 40 is node 4
It is terminated by a 50Ω resistor 56 connected between 2 and ground.

Operational amplifier 14 is a differential-to-single-ended conversion type amplifier, and its positive voltage input is connected to node 44 and its negative voltage input is connected to node 46.

A voltage source VDD 62 is connected to each node 44-46 through the same resistor 64-66. Additionally, node 46 is 50Ω
The reference voltage of node 46 is determined by grounding through resistor 68 of node 46 . It also serves to terminate the bridge T attenuator reference cell 12 via amplifier 60. Amplifier 60 receives operating power from a lead 72 to voltage source VDD and a lead 72 to negative power supply -Vss.

FIG. 2 shows a circuit diagram of a GaAs operational amplifier 60 used in the attenuator design of FIG. The amplifier 60 includes an input differential amplifier pair 74.1 having a common mode bias circuit 76, a differential level shift stage 78, a differential-to-single-ended conversion stage (DS
E) 80 and output stage 82 and has an open loop gain of approximately 50 dB. DSE stage 80 is commonly used in NMO3 designs, where GaAs depletion mode technology has recently been established. Since high frequency characteristics are not the goal of this amplifier, sufficient pole compensation limits the band to 100 MH2 or less to improve stability.

This amplifier 60 outputs a control signal on output lead 38.

The control signal is varied by the reference output signal at node 44 and further varied by the attenuation control signal applied to control terminal 16. The control signal on output line 38 is fed back to the gate of parallel FET 54 to control reference circuit operation, and is also applied to the gate of parallel FET 34 via resistor 36. The operational amplifier 60 operates such that the conductance of the parallel FET 54 of the reference cell 12 equalizes the voltages at nodes 44 and 46. As a result, the impedance of node 44 is made equal to that of node 46. The same control signal is sent to FET34
is also applied, causing the attenuation cell 10 to operate in the same manner as the reference cell 12. That is, by controlling the conductance of FET 34, the conductance of FET 34 is
4 and ground is equal to the voltage at 7- nodes 44 and 46.

In the circuit of FIG. 1, the characteristic impedances of both cells 10-12 are made equal regardless of changes in attenuation.

RF attenuation cell 1 using DC parameter feedback of reference cell
The concept of controlling zero was first validated using two GaAs FET bridge T attenuators and a 741 operational amplifier.

This concept was then implemented at a monolithic level with attenuation cell 10, reference cell 12, and operational amplifier 14 formed on a single GaAs chip. The GaAs integrated circuit used high-yield 1 μm ion implantation techniques, NiCr resistors for stable termination, and MIM capacitors for bypass and decoupling capacitors. This circuit is then mounted in a hermetic surface mount package as disclosed in U.S. Pat. No. 4,668,920. Using DC parameters requires applying sufficient voltage to the reference attenuation cell to obtain a signal level that the operational amplifier can detect.
The value must be such that the FET does not depart from the linear operating region. In this design, the source and drain voltages of the FETs are preferably less than 2QQmV and are preferably operated from a single 9-15V power supply using appropriate level shifting circuitry.

There are several considerations when using FETs as series and parallel devices. The gate width of the FET is selected to be sufficiently large so that the insertion loss is small in the lowest attenuation state, but the parallel drain-source capacitance Cds is limited, and as a result, there is sufficient isolation at high frequencies in the maximum attenuation state. Make it so. Therefore, the series and parallel gate widths were selected to be 300 μm. Since the maximum attenuation is most dependent on the Cds of the series FET, the number of gate combs in the device was minimized to reduce the additional source-drain capacitance caused by interconnect parasitics in the comb device structure. Losses due to the metal resistance of the wide gate comb do not affect the RF operation of the attenuator.

FIG. 3 shows the transmission characteristics of the packaged attenuator. The five characteristic curves shown here correspond to five different signal levels. The voltages shown here were level shifted to operate the attenuator from a single supply. The lowest attenuation gain slope is caused by the combination of skin effect losses due to the package and losses of the microstrip structure on GaAs from the gouer end to the RF attenuation cell. Minimum attenuation is 3.5 at IGHz
dB, increasing to 5 dB at 10 GHz.

In this design, the gate-source voltage Vg of both FETs
s must never be positive. If Vgs is made positive near the point of forward conduction, the minimum attenuation is improved by about 1 dB. The effect on the maximum attenuation of the series FET Cds increases visibly at high frequencies.

The attenuation range is 17 dB at IGHz, decreasing to 10 dB at 10 GHz.

FIG. 4 shows the return loss of a packaged attenuator as a function of frequency when using an on-chip correction circuit. Return loss exceeds 12 dB within the 1-10 GHz band. This means that when changing the attenuation, the circuit of Figure 1
It is shown that the output return loss is optimized. Packaged attenuator input/output voltage standing wave ratio (VSWR)
is better than 1.7:1 over the 1-10 GHz range.

Variations As mentioned above, the preferred embodiment of the present invention uses a bridge T-type attenuation circuit and a reference circuit. However, the present invention should not be limited to such embodiments, and various modifications and changes can be made without departing from the gist of the present invention.

The invention can also be implemented using a symmetrical T-shaped circuit as shown in FIG. The general circuit configuration is similar to that of the attenuator shown in FIG. 1, and includes an attenuation cell IOA.

It includes a reference cell 12A and an operational amplifier 14A. Two series-connected FETs 20A are used as series FETs, and the source and drain are connected between RF 11022A and 24A. The gate of each FET is connected to the attenuation control input 16 via an RF isolation resistor 18A. The parallel FET 34A has a drain and a source respectively connected between the connection point of the two series FETs 20A and ground. The same goes for the reference cell 12A, which includes two series FETs.
40A and a parallel FET 54A. Output 38 of operational amplifier 60 is connected to the gate of FET 34A via resistor 36A and also to the gate of FET 54A. Furthermore, as another example, an example of a symmetric π-type variable attenuator is shown in the sixth example.
As shown in the figure. In this circuit, both the attenuation cell IOB and the reference cell 12B have a symmetric π-type circuit configuration using one series FET 2OB and 40B and two parallel FETs 34B and 54B. The output 38 of the operational amplifier 60 is connected to the gates of both FETs 34B via a resistor 36B and connected to the parallel FET 34B.
Also connect to the gate of ET54B.

In each of these other embodiments, the characteristic impedance between the RF Ilo of the attenuator and the ground is the reference node 4 of the attenuation cell 12B.
It is maintained at a constant value determined by the impedance ZO between 6 and ground.

The circuit parameters shown in FIG. 1 are specific examples that yield the test results shown in FIGS. 3 and 4. Of course, this parameter can be freely changed depending on the application. As mentioned above, electrical equalization between the attenuation cell and the reference cell is preferred to obtain the same characteristic impedance and equalize the circuitry of each cell. Equalization can also be achieved by appropriately scaling the FET width and characteristic impedance between both cells. For example, in Figure 1, the resistance of 50Ω is 1
00Ω resistance, and the width of the FET of reference cell 12 is 15
It may be set to 0 μm.

The concept of using the DC parameter feedback of the reference cell 12 to control the attenuation cell 1o is to connect the output of the operational amplifier 60 to a parallel FET.
It is not limited to the case where it is used to control a gate.

Those skilled in the art will readily understand that the same principles can be used to gate the series FETs if the attenuator control signal is applied to the gates of the parallel FETs.

[Effects of the Invention] As is clear from the above description, according to the variable attenuator of the present invention, at least two FETs are inserted into the series and parallel signal paths, respectively, and the attenuation amount is made continuous or stepwise by controlling the gate voltage. By using a similar reference cell to which the same control signal is applied and feeding its output back to the attenuator, the characteristic impedance can be maintained constant regardless of changes in the attenuation amount of the attenuator. A remarkable effect is that an attenuator with stable characteristics can be obtained over a wide range of 1 to 10 GHz or more.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a preferred embodiment of the variable attenuator according to the present invention, FIG. 2 is a circuit example of the operational amplifier used in FIG. 1, and FIGS. 3 and 4 are electrical diagrams of the variable attenuator of FIG. Figures 5 and 6 are circuit diagrams of other embodiments of the variable attenuator of the present invention, and Figures 7A and 7B are principle diagrams of conventional fixed and variable attenuators. In the figure, 10 is an attenuation cell, 12 is a reference cell, 14 is a feedback circuit, 16 is an attenuation control input terminal, and 22.24 is an attenuator input/output terminal. Patent applicant: Sony Tektronix Corporation S21
LOG MAG Sll LOG MAG STOP 11.000000000 GHzFIG
, 5 FIG. 6

Claims (1)

[Claims] An attenuation cell and a reference cell having substantially similar configurations each including at least one series FET and one parallel FET, a control terminal that applies the same attenuation control signal to the gates of the series or parallel FETs of both cells, and an output of the reference cell. A variable attenuator comprising a feedback circuit that feeds back to the gates of the parallel or series FETs of both cells.