JPS63301091A - Video data transmission system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video data transmission method, and particularly to a video data transmission method for transmitting and displaying a video signal on a dot rate display device different from the display device to which it is first combined. Regarding the method.

[Conventional technology]

CRT display devices are widely used as display means for processor control systems such as numerical control devices. In these systems, CRT display devices of various sizes are used depending on cost, importance of the display device, etc. For example, if the system does not require many display devices and is simply used to confirm the position of the machine, a monochrome 9-inch C.
An RT display device is used. Conversely, a 14-inch color CRT display is used when there is an interactive input system or when a display is important, such as when displaying very complex graphics.

[Problem that the invention seeks to solve]

However, once a system is configured as a system in which the display device is not very important, it is not rare that a larger CRT display device becomes necessary due to subsequent changes in user requirements, addition of functions, etc. In this case, data representation such as screen size can be solved by adding or changing software.

However, different CR'rT display sizes generally have different dot rate speeds, and this difference cannot be handled by software changes.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a video data transmission system that can easily convert video signals even if the dot rate of a CRT display device changes.

[Means for solving problems]

In the present invention, in order to solve the above problems, as shown in FIG.
) for serial/parallel conversion circuits (11, 13), and a RAM (2) for temporarily storing the converted parallel data.
2) and the data in the RAM (22) to the second dot rate (20
MHz), and a circuit (34, 36) that performs parallel-to-serial conversion, and a circuit (31) that outputs and controls the converted signal at a second dot rate (20 MHz). A video data transmission method with characteristics is provided.

[Effect]

Changes in screen size, display layout, etc. are data processed by software, and a video signal is input at the first dot rate. This video signal is once converted into a parallel signal and stored in the RAM as bit data. By reading the bit data stored in this RAM at the second dot rate, converting it from parallel to serial, and outputting it as a video signal at the second dot rate, the second
video signals of different dot rates can be obtained and displayed on CRT display devices of different dot rates.

〔Example〕

An embodiment of the present invention will be described below based on the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention.

In the figure, 10 is a frequency conversion circuit, which is a circuit that converts an 8 MHz video signal into a 20 MHz video signal. That is, in this embodiment, the initial dot rate is 8MHz.
14 to a device for combining a 9-inch CRT display device
An example of using frequency conversion circuit 10 to couple a 4-inch CRT display is shown. Reference numeral 11 denotes a shift register, into which an 8 MH2 video signal A is manually input. This shift register 11 has an 8 MHz clock at gate 1.
It is input via 2. In addition, the input signal of gate 12 *
DPT is a signal indicating the presence of a video signal. The serially inputted video signal A is outputted as a parallel signal to the latch 13 every 8 clocks by the shift register 11. The latch 13 has an 8MHz clock on the counter 1.
4 gives a countdown clock of one-eighth. That is, when 8 bits of data are accumulated in the shift register 11, the 8 bits are stored in the latch 13. The 8-bit data of this latch 13 is written into the RAM 22. Every time 8 bits of data are written, the counter 15 counts up and amplifies the address of the RAM 22, and the bit data is stored in consecutive addresses of the RAM 22. 21 is a multiplexer which selects whether to access the RAM on the input side or the output side. Reference numeral 23 denotes an arbitration circuit, which arbitrates between writing and reading from the RAM 22 when they overlap. In this way, the 8 MHz video signal A is continuously stored in the RAM 22 as bit data.

Next, reading of bit data stored in the RAM 22 will be described. 31 is a CRTC (CRT control circuit), which supplies a vertical synchronization signal (VSYNC) to the CRT display device;
CRT by sending signals such as horizontal synchronization signal (H3YNC)
This is a circuit that controls the display of a display device. CRTC31 via multiplexer 21, RAM22 which should not be read
Select the address. Bit data of the selected address is read to latch 34. The latch 34 is an 8-bit latch, and transfers 8-bit data input in parallel to the shift register 36 in parallel. A clock oscillator 32 generates a 20MH2 clock. Of course, this must match the second dot rate. A 20 MHz clock is counted down to 1/8 by a counter 35 via a gate 33 and applied to a latch 34, and is output every 1/8 of 20 MHz. The output is input to the shift register 36 in parallel. The shift register 36 outputs bit data input in parallel as a serial output, and outputs 20 M bit data as a serial output.
Outputs at a dot rate of Hz. This means that the 20MHz clock passes through the gate 33 and is input to the shift register 36.
is executed by being given to . Note that the signal *DPT given to the gate 33 by the output of the CRTC is the CRTC3
1 is a signal meaning that a video signal is output.

In this way, the video signal stored as bit data in the RAM 22 is output as a 20 MHz video signal B.

This 20 MHz video signal B is a vertical synchronization signal (VSYNC) from the CRTC31 and a horizontal synchronization signal (H3
YNC), and the necessary images are displayed on the 14-inch CRT display.

In the above explanation, the input video signal is 8 MHz for a 9-inch CRT display, and the output video signal is 20 MHz for a 14-inch. The same applies to frequency. Of course, if the frequencies differ significantly, a special circuit such as an arbitration circuit is required.

〔Effect of the invention〕

As explained above, in the present invention, a video signal of a specific frequency is once stored in RAM as bit data, and is read out at another dot rate and applied to different CRT display devices. Other CRT display devices can be easily replaced and combined with the control device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. 10−・−・−・−・−・−・Frequency conversion circuit 11
−−−−−−−−Shift register 13・・・・・・・−・−・Latch 14−−−−−
−・−−−−−One counter 15−・−・・−・−Counter

Claims (6)

[Claims] (1) A circuit that converts a video input signal of a first dot rate from serial to parallel, a RAM that temporarily stores the converted parallel data, and reads the data in the RAM at a speed synchronized with the second dot rate. A video data transmission system comprising: a circuit for performing parallel-to-serial conversion; and a circuit for controlling output of the converted signal at a second dot rate. (2) The video data transmission system according to claim 1, wherein the serial-to-parallel conversion is comprised of a shift register and a latch. (3) The video data transmission system according to claim 1, wherein the parallel-to-serial conversion is comprised of a latch and a shift register. (4) A video data transmission system characterized in that the serial-to-parallel conversion is performed every 8 bits. (5) The video data transmission system according to claim 1, wherein the parallel-to-serial conversion is performed every 8 bits. (6) The video data transmission system according to claim 1, wherein writing and reading of the RAM is controlled by an arbitration circuit.