JPH10319919A - Transmitting system for display picture data and ic for processing its signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent degradation of display dignity of a display by converting accurately a display signal from a display controller to high speed digital transmission data, in a high speed digital transmission system between a liquid crystal display controller generating a display picture and a display. SOLUTION: This high speed digital transmission system between a liquid crystal display controller 5 and a liquid crystal display 14 is provided with a buffer means constituted with a FIFO memory 7 for storing temporarily in which a liquid crystal display signal from the liquid crystal display controller 5 is written with a dot clock from the liquid crystal display controller 5 and written with a clock signal in which a transmission clock from a high speed digital transmission controller 9 is frequency-divided. And stable high speed digital transmission can be performed even when a dot clock of the liquid crystal display controller is unstable and is not synchronized with a transmission clock of the high speed digital transmission controller 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display image data transmission system for high-speed digital transmission of dot clock synchronous display image data in an EL display device, a liquid crystal display, and a computer device, a signal processing IC used in the transmission system, and a signal processing IC. The present invention relates to a display image data transmission device using a processing IC.

[0002]

2. Description of the Related Art As an example of the prior art, signal processing between a liquid crystal display controller and a TFT liquid crystal display module will be described.

FIG. 5 shows an example in which a high-speed digital transmission system is not used. A liquid crystal display controller (5) controlled by a microprocessor (2) constituting a personal computer (1) stores data in a frame memory (6). Draw display image information. The drawn digital display image data is read out from the frame memory (6) and converted into a 6-bit luminance gradation digital signal for each of RGB, and the TFT liquid crystal display is used.
(14).

A horizontal / vertical synchronizing signal for controlling the display position of the display screen and a liquid crystal dot clock signal synchronized with the luminance gradation digital signal are outputted from a liquid crystal display controller (5), and the TFT liquid crystal display ( 14)
Supplied to (3) is a memory of the personal computer (1), and (4) is an input / output (I / O) device.

In the configuration shown in FIG. 5, the connection between the liquid crystal display controller (5) and the TFT liquid crystal display (14) is made using a total of 21 signal lines.

On the other hand, the liquid crystal display controller (5) and T
An integrated circuit of a high-speed digital transmission system for performing transmission between the FT liquid crystal displays (14) has been developed. FIG. 4 shows an example in which the number of signal lines is reduced by using this integrated circuit as compared with that shown in FIG. .

In the example shown in FIG. 4, a liquid crystal display controller (5) of a personal computer (1) and a TFT
The liquid crystal displays (14) are not directly connected by signal lines, but are connected via a high-speed digital transmission system including a high-speed digital transmission controller (9) and a high-speed digital reception controller (12). This enables high-speed digital transmission controllers
(9) The number of signal cable lines of the high-speed digital reception controller (12) can be reduced.

A liquid crystal display controller (5) controlled by a microprocessor (2) constituting a personal computer (1) draws display image information on a frame memory (6). The drawn digital display image data is read out from the frame memory (6), converted into a 6-bit luminance gradation digital signal of each RBG, and sequentially output to the high-speed digital transmission controller (9).

Further, the liquid crystal display controller (5) transmits a horizontal / vertical synchronizing signal for controlling the display position of the display screen and a liquid crystal dot clock signal synchronized with the luminance gradation digital signal for each RBG to a high-speed digital transmission controller ( 9)
Output to In this case, a total of 21 signal lines are provided.

The high-speed digital transmission controller (9) converts the input 6-bit luminance gradation digital signal of RBG and the horizontal / vertical synchronization signal into three-system high-speed serial data SD.
0, SD1, and SD2, and outputs the latch clock signal SDCK required by the next-stage high-speed digital reception controller (12).
0, SD1, SD2, and SDCK are supplied to the next-stage high-speed digital reception controller (12).

The high-speed digital reception controller (12)
The four signals SD0, SD1, SD2,
A 6-bit luminance gradation digital signal of RBG, a horizontal / vertical synchronization signal, and a dot clock signal are reproduced from SDCK,
It is supplied to the TFT liquid crystal display (14).

FIG. 2 shows a detailed configuration of the high-speed digital transmission controller (9).
A signal of double frequency is generated as a transmission clock signal by a PLL oscillator (19).

The 20 liquid crystal display signals from the liquid crystal display controller (5) are input in three separate ways, and the input three liquid crystal display signals are divided into the transmission clock signal from the frequency divider (18). After sampling into the input latches (15) with the latch clock signal divided by a factor of 7, the parallel-serial converter (16) converts the digital clocks into high-speed serial data SD0, SD1, and SD2.

The high-speed serial data SD0, SD1, and SD2, which are liquid crystal display signals, and the latch clock signal SDCK required for generating a transmission clock in the high-speed digital reception controller (12) are respectively provided by a differential signal driver (1).
7), it is connected to a high-speed digital reception controller (12) by four twisted pair cables (11).

FIG. 3 shows a detailed configuration of the high-speed digital reception controller (12). The high-speed serial data SD0, SD1, and SD2 and the latch clock signal SDCK transmitted from the high-speed digital transmission controller (9) are respectively converted in signal level by a differential signal receiver (20).

A transmission clock required for serial-to-parallel conversion is generated from the latch clock signal SDCK by a PLL oscillator (23) and supplied to each serial-to-parallel converter (21) to be converted into a liquid crystal display signal. Frequency divider for transmission clock signal
The output signals are sampled by the output latches (22) with the latch signals obtained by dividing the frequency by 1/7 in (24), and output to the TFT liquid crystal display (14). Also, TFT liquid crystal display
As the dot clock signal to be given to (14), a latch clock signal obtained by dividing the transmission clock by 7 in the divider (24) is used in consideration of the propagation delay time of the serial-parallel converter (21). .

According to the above configuration, when the high-speed digital transmission system is not used, 21 signal cables are required, but the number can be reduced to 8 signal lines of 4 twisted pairs.

[0018]

However, in the connection between the liquid crystal display controller and the liquid crystal display,
When using a high-speed digital transmission system that generates an integer multiple transmission clock with a PLL oscillator from the liquid crystal display controller's dot clock as in the conventional method, the transmission clock of the high-speed digital transmission controller and the liquid crystal If the sample clock for latching the display signal is not completely synchronized, the liquid crystal display signal from the liquid crystal display controller cannot be transmitted correctly, and the display quality of the liquid crystal display is significantly reduced.

With the integration of the liquid crystal display controller, the liquid crystal display controller generates a dot clock by generating a P clock.
It becomes a digital / analog mixed-type IC with a built-in LL circuit, and the PLL oscillator that generates the dot clock is easily affected by voltage fluctuations and noise. In addition, the speeding up of the high-speed digital transmission clock signal is required for high-speed digital transmission systems. Because the dot clock signal specification becomes stricter,
It is technically difficult to generate a stable dot clock from a liquid crystal display controller.

When the dot clock signal from the liquid crystal display controller is used as the transmission clock signal for the high-speed digital transmission controller, the transmission speed is defined by the frequency of the dot clock signal, so that the capability of the high-speed digital transmission system can be utilized. Can not.

According to the present invention, in a high-speed digital transmission system between a liquid crystal display controller for generating a display image and a liquid crystal display, even if the dot clock of the liquid crystal display controller is unstable, the liquid crystal display data from the liquid crystal display controller is transmitted to the high-speed digital transmission data. The purpose is to ensure accurate conversion to the liquid crystal display.

[0022]

In order to achieve the above object, a display image data transmission system according to the present invention converts a display image data generated by a liquid crystal display controller into high-speed serial data by a high-speed digital transmission controller, thereby achieving high-speed transmission. In a display image data transmission method in which high-speed digital transmission is performed to a digital reception controller and high-speed serial data received by the high-speed digital reception controller is returned to the original display image data and supplied to the liquid crystal display, the liquid crystal display is controlled based on a dot clock signal. A liquid crystal display controller for sequentially outputting luminance gradation data and a display control signal for each pixel; and a high-speed digital for parallel-serial conversion output or code conversion output of display image data based on a transmission clock having a higher frequency than the dot clock signal. Liquid between the transmission controller A buffer for absorbing a frequency difference between a dot clock signal from the display controller and a transmission clock signal from the high-speed digital transmission controller is provided, and display image data from the liquid crystal display controller is converted into high-speed digital transmission data via the buffer. It is characterized by the following.

Further, as buffer means for absorbing a frequency difference between the dot clock signal of the liquid crystal display controller and the transmission clock signal of the high-speed digital transmission controller, storage means for temporarily holding display image data of the liquid crystal display controller is provided. The display image data from the liquid crystal display controller is sequentially written and registered in the memory in synchronization with the dot clock signal, and the transmission clock from the high-speed digital transmission controller is synchronized with the read clock signal divided to the same frequency as the dot clock. A series of operations for sequentially reading out and deleting display image data stored in the memory.

Further, monitoring means for monitoring the presence or absence of effective display image data in a memory constituting the buffer means is provided.
A valid identification signal that identifies the validity of the display image data input to the high-speed digital transmission controller is added, and only the valid display image data is input to the liquid crystal display on the high-speed digital reception controller side. It is characterized in that high-speed digital transmission of display image data in which the cycle of the clock signal is not constant can be performed.

Also, as monitoring means for monitoring the presence or absence of valid display image data in the memory, the number of times display image data from the liquid crystal display controller is written into the memory, and the number of display times from the memory input to the high-speed digital transmission controller. A counting means is provided for comparing the number of times image data is read out.

Also, as monitoring means for monitoring the presence or absence of valid display image data in the memory, an address for writing display image data from the liquid crystal display controller to the memory, and a display from the memory to be input to the high-speed digital transmission controller. An address comparing means for comparing read addresses of image data is provided.

The monitoring means for monitoring the presence or absence of valid display image data in the memory includes a display count from the memory which is input to the high-speed digital transmission controller when the number of times of display image data writing from the liquid crystal display controller to the memory is inputted. It is characterized in that an abnormal state of operation exceeding the number of times of reading image data can be detected.

A clock signal source is separately provided and supplied as the reference clock signal of the dot clock signal or the transmission clock, or a PLL for generating an integral multiple frequency from the dot clock signal.
Clock generation means for setting the time constant of the loop filter of the oscillator to a sufficiently large value is provided.

Further, a signal processing IC in which buffer means used for the display image transmission system are integrated, and the signal processing IC
A display image data transmission device using C.

The display image data transmission system configured as described above is a high-speed digital transmission system between a liquid crystal display controller for generating a display image and a liquid crystal display.
Since buffer means including a memory for temporarily storing the liquid crystal display data state is provided, the liquid crystal display data is written from the liquid crystal display controller to the memory in synchronization with the dot clock signal, and the transmission clock signal from the high-speed digital transmission controller is divided. The liquid crystal display data can be read from the memory by using the circulated signal, and even if the dot clock of the liquid crystal display controller is unstable, the liquid crystal display data from the liquid crystal display controller can be accurately converted into high-speed digital transmission data.

Further, a monitoring means for monitoring the presence or absence of valid display data in a memory constituting the buffer means is provided, and when the liquid crystal display data is input to the high-speed digital transmission controller, whether the liquid crystal display data is valid or invalid is identified. Since the identification signal to be performed is added, only the effective display data can be intermittently transmitted. Even if the period of the dot clock signal from the liquid crystal display controller is not constant, high-speed digital transmission can be performed without error.

In the above buffer means, an additional circuit for monitoring the presence or absence of valid liquid crystal display data in the memory may be provided.
There is provided a counting means for comparing the number of times the liquid crystal display data from the liquid crystal display controller is written into the memory with the number of times the liquid crystal display data is read out from the memory for input to the high-speed digital transmission controller, or the liquid crystal display data from the liquid crystal display controller. Address comparison means for comparing the address pointer value to be written to the memory with the address pointer value for reading the liquid crystal display data from the memory for input to the high-speed digital transmission controller, so that the number of times of writing the display image data from the liquid crystal display controller to the memory is provided. Causes the LCD to exceed the read count for reading the LCD display data from the memory to input to the high-speed digital transmission controller, or that the write address pointer value to the memory differs from the read address pointer value. It can be out.

A PL that generates a dot clock signal or a transmission clock signal by separately providing a clock signal source
Generate a stable transmission clock signal by supplying it as the reference clock signal of the L oscillator or by setting the time constant of the loop filter of the PLL oscillator that generates an integer multiple frequency from the liquid crystal dot clock signal to be sufficiently large. Can be.

[0034]

FIG. 1 is a block diagram of an embodiment of the present invention. 2 and 3 are block diagrams of a high-speed digital transmission / reception controller used in a high-speed digital transmission system.

In this embodiment, a liquid crystal display controller
Using a FIFO (Fast in Fast out) as a memory interposed between (5) and the high-speed digital transmission controller (9), the reference clock signal source of the PLL oscillation circuit for generating the transmission clock of the high-speed digital transmission controller (9) is removed. With this arrangement, the frequency difference between the dot clock signal from the liquid crystal display controller (5) and the transmission clock signal is absorbed, so that the display quality of the liquid crystal display is not degraded.

In FIG. 1, a personal computer (1)
A liquid crystal display controller (5) controlled by a microprocessor (2) constituting the above draws display image information in a frame memory (6). The rendered digital display image data is read out from the frame memory (6), converted into a 6-bit luminance gradation digital signal for each of RGB, and output in order.

The liquid crystal display controller (5) outputs a horizontal / vertical synchronizing signal for controlling the display screen position, and a liquid crystal dot clock signal synchronized with the above-mentioned RGB luminance gradation digital signal. A total of 20 liquid crystal display signals comprising the 6-bit RGB signals and the horizontal / vertical synchronization signals are supplied to a 20-bit input FIFO memory (7) for temporarily storing display screen data.

The liquid crystal display controller (5) sends the
The 20 liquid crystal display signals supplied to the O memory (7) are sequentially written to the FIFO memory (7) by the dot clock signal, and the liquid crystal display signal written to the FIFO memory (7) is a high-speed digital signal. The data is sequentially read from the FIFO memory (7) by the latch clock frequency-divided to 1/7 of the transmission clock by the frequency divider (18) of the transmission controller (9).

In this case, the liquid crystal display signal from the liquid crystal display controller (5) is converted to the above F based on the dot clock signal.
The address pointer value of the write address to be sequentially written is stored in the IFO memory (7). A latch clock signal obtained by dividing the transmission clock signal of the next-stage high-speed digital transmission controller (9) by one seventh is output from the FIFO memory (7) for output to the high-speed digital transmission controller (9). An address pointer value of the address of the liquid crystal display signal to be read is detected. And the above FIFO
The address pointer values of the write address and the read address to the memory (7) are compared, and when they match, a valid identification signal indicating valid display data is generated.

The timing signal for writing the liquid crystal display signal from the liquid crystal display controller (5) to the FIFO memory (7) is used as a count-up signal, and is input from the FIFO memory (7) to the high-speed digital transmission controller (9). A counter (8) for counting a timing signal for reading the liquid crystal display signal as a countdown signal,
In addition to detecting an abnormal state in which the number of times of writing data to the FIFO memory (7) exceeds the number of times of reading data,
A valid identification signal for detecting that valid display data is present in the FO memory (7) is generated. The FIFO memory (7) and the valid identification signal detecting circuit for detecting the valid display data may be formed as independent ICs or the same IC.

FIG. 2 shows the configuration of the high-speed digital transmission controller (9). An external reference clock signal source (10) is separately provided, and a reference clock signal supplied from the reference clock signal source (10) is provided. Based on the signal, the dot clock signal or a transmission clock signal having a frequency seven times that of the dot clock signal
Generated by the LL oscillator (19). The PLL oscillator (1
The time constant of the loop filter of 9) is set to a sufficiently large value.

R output from the FIFO memory (7)
The high-speed digital transmission controller converts 7-bit signals of G, a horizontal synchronization signal, G and a horizontal synchronization signal, and B and the data identification signal into high-speed digital serial data.
(9) includes three input latches (15) for inputting the respective 7-bit signals, and three parallel-serial converters (16) for parallel-to-serial conversion of the respective outputs of the input latch (15). ), And the three liquid crystal display signals of 7 bits each and the valid identification signal thereof are input by the latch clock signal divided by a frequency divider (18) to one seventh of the transmission clock. After sampling into the latch (15), the parallel-serial converter
At (16), the data is converted into high-speed digital serial data.

The high-speed digital serial data converted by the parallel-to-serial converter (16) and the latch clock signal output from the frequency divider (18) are a differential signal driver.
The signals are level-converted in (17), and are output as high-speed serial data SD0, SD1, and SD2, which are liquid crystal display signals, and a latch clock signal SDCK required to generate a transmission clock in the high-speed digital reception controller (12). The high-speed serial data SD0, SD1, and SD2 output from the differential signal driver (17) and the latch clock signal SDCK are converted into high-speed digital reception controllers (12) through four twisted pair cables (11) as high-speed digital differential signals. Connected to

FIG. 3 shows the configuration of the high-speed digital reception controller. In this high-speed digital reception controller (12), the high-speed serial data SD0, SD1, SD2 received by the differential signal receiver (20) and the latch clock The signal level of each signal of the signal SDCK is converted.

From the latch clock signal derived from the differential signal receiver (20), a PLL clock (23) generates a transmission clock signal of seven times the frequency from the latch clock signal, and uses the generated transmission clock signal to generate a serial-parallel converter ( At 21), each high-speed serial data SD0, SD1, SD2 derived from the differential signal receiver (20) is converted into a 7-bit liquid crystal display signal.

The transmission clock signal derived from the PLL oscillator (23) is frequency-divided by a frequency divider (24) to 1/7 to form a latch clock signal, and the latch clock signal is converted into the above 7-bit signal. After sampling each of the obtained liquid crystal display signals into an output latch (22), a horizontal / vertical synchronization signal for controlling a display screen position and a TFT liquid crystal display (1) as a 6-bit luminance gradation digital signal for each of RGB.
Supply to 4).

The dot clock signal to be supplied to the TFT liquid crystal display (14) is obtained by dividing the transmission clock by 7 in the frequency divider (24) of the high-speed digital reception controller (12) into a gate circuit (7). In 13), a signal gated by the valid identification signal of the display data is used. Therefore, only valid liquid crystal display data can be input to the TFT liquid crystal display (14).

In this embodiment, a TFT liquid crystal display is described as an example, but the present invention can be widely applied to a display device in which luminance gradation data is output in synchronization with a dot clock.

[0049]

Since the present invention has the above configuration,
In a high-speed digital transmission method between a display controller and a display for generating a display image, even if the dot clock of the display controller is unstable, a display signal from the display controller can be accurately converted to high-speed digital transmission data. Since only effective display data can be intermittently transmitted, high-speed digital transmission can be performed even for display signals in which the period of the dot clock signal from the display controller is not constant.

If the number of times the display signal is written from the display controller to the memory exceeds the number of times the display signal is read from the memory input to the high-speed digital transmission controller, it can be detected as an abnormal state. Can be prevented from decreasing.

Further, since the luminance gradation data is transmitted in a digital amount, it is possible to perform accurate color development and gradation image transmission without being affected by the linearity and conversion speed of the DA converter and the AD converter. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram of an apparatus using a display image data transmission system of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a high-speed digital transmission controller.

FIG. 3 is a block diagram illustrating a configuration of a high-speed digital reception controller.

FIG. 4 is a block diagram showing a conventional image data transmission method using a high-speed digital transmission method.

FIG. 5 is a block diagram showing a conventional image data transmission system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Personal computer 2 Microprocessor 5 Liquid crystal display controller 6 Frame memory 7 FIFO memory 8 Counter (memory monitoring additional circuit) 9 High speed digital transmission controller 10 Reference clock signal source 11 Twisted pair cable 12 High speed digital reception controller 13 Gate circuit 14 TFT liquid crystal display 15 Input latch 16 parallel-serial converter 17 differential signal driver 18 frequency divider 19 PLL oscillator 20 differential signal receiver 21 serial-parallel converter 22 output latch 23 PLL oscillator 24 frequency divider

Claims (9)

[Claims] 1. A high-speed digital transmission controller converts display image data generated by a liquid crystal display controller into high-speed serial data and transmits the high-speed digital data to a high-speed digital reception controller. A display image data transmission system for returning to the display image data of the liquid crystal display and supplying the same to the liquid crystal display; a liquid crystal display controller for sequentially outputting luminance gradation data and a display control signal of each pixel of the liquid crystal display based on a dot clock signal; A dot clock signal from the liquid crystal display controller and a high-speed digital transmission controller are connected between the high-speed digital transmission controller that outputs parallel-to-serial conversion or code conversion of display image data based on a transmission clock having a higher frequency than the clock signal. Transmit buffer means for absorbing the frequency difference between the clock signal provided, the display image data transmission method which the display image data from the LCD controller and converting the high-speed digital transmission data through the buffer means. 2. A storage means for temporarily storing display image data of a liquid crystal display controller as buffer means for absorbing a frequency difference between a dot clock signal of a liquid crystal display controller and a transmission clock signal of a high-speed digital transmission controller, The display image data from the liquid crystal display controller is sequentially written and registered in the memory in synchronization with the dot clock signal, and the transmission clock from the high-speed digital transmission controller is synchronized with the read clock signal divided to the same frequency as the dot clock. 2. A display image data transmission system according to claim 1, wherein a series of operations for sequentially reading and deleting display image data stored in the memory are repeatedly performed. 3. A monitoring means for monitoring presence or absence of valid display image data in a memory constituting said buffer means, and a valid identification signal for identifying validity / invalidity of display image data inputted to a high-speed digital transmission controller is added. In addition, the high-speed digital reception controller can input only valid display image data to the liquid crystal display, and perform high-speed digital transmission of display image data in which the period of the dot clock signal from the liquid crystal display controller is not constant. 3. The display image data transmission method according to claim 2, wherein: 4. A monitoring means for monitoring the presence or absence of valid display image data in the memory, the number of times display image data from a liquid crystal display controller is written to the memory, and the number of display times from the memory input to a high-speed digital transmission controller. 4. The display image data transmission system according to claim 3, further comprising a counting means for comparing the number of times image data is read out. 5. An address for writing display image data from a liquid crystal display controller to said memory, and a display from said memory to be input to a high-speed digital transmission controller, as monitoring means for monitoring the presence or absence of valid display image data in said memory. 4. A display image data transmission system according to claim 3, further comprising an address comparison means for comparing read addresses of the image data. 6. A monitor for monitoring the presence or absence of valid display image data in the memory, wherein the number of times of writing display image data from the liquid crystal display controller to the memory is:
4. The apparatus according to claim 3, wherein an abnormal state of the operation exceeding the number of readings of the display image data from the memory input to the high-speed digital transmission controller can be detected.
And 4. The display image data transmission method according to 4. 7. A clock signal source is separately provided and supplied as a reference clock signal of the dot clock signal or the transmission clock, or a loop filter of a PLL oscillator that generates an integer multiple frequency from the dot clock signal. 7. A display image data transmission system according to claim 1, further comprising a clock generation means for setting a constant to a sufficiently large value. 8. A signal processing IC in which buffer means used for the display image data transmission system according to claim 1 are integrated. 9. A display image data transmission device using the signal processing IC according to claim 8.