TWI771716B - Source driver circuit, flat panel display and information processing device - Google Patents

Abstract

A source driving circuit, having a plurality of channel driving units to drive a display panel, is characterized in that: each of the channel driving units has a display data latch circuit and a pulse signal transmission circuit; each of the display data latches The circuits are all coupled with a display data bus, and all act according to an enable signal to latch the data on the display data bus; and a plurality of the pulse signal transmission circuits are controlled by a selection signal to make one selected The pulse signal transmission circuit generates the enable signal and a pulse signal according to an initial pulse signal, and makes a plurality of the pulse signal transmission circuits after the selected pulse signal transmission circuit transmit the pulse therebetween in a ripple manner and each generates the enabling signal according to the pulse signal.

Description

Source driver circuit, flat panel display and information processing device

The present invention relates to the technical field of display panel driving, and more particularly, to a source driving circuit which can support display panels with arbitrary resolutions.

It is known that a liquid crystal display (LCD) has the advantages of thin volume, light weight and low radiation, and is currently the most widely used flat panel display. FIG. 1 is a circuit block diagram of a conventional liquid crystal display. Electronic engineers familiar with the design and manufacture of liquid crystal displays must know that the conventional liquid crystal display 1a mainly includes: a liquid crystal display panel 11a, a gate driver circuit 12a, a source driver circuit 14a, a timing controller 13a, and a Gamma voltage generating unit 15a.

FIG. 2 is a first circuit block diagram of a liquid crystal display panel and a source driving circuit of a conventional liquid crystal display. As shown in FIG. 2, the conventional source driver circuit 14a generally includes: Y shift registers 141a, Y latches 142a, and Y channel drivers 143a. The Y channel drivers 143a are respectively coupled to the Y row driving signal input channels of the liquid crystal display panel 11a, the Y latches 142a are each coupled to one of the Y channel drivers 143a, and the Y Each of the shift registers 141a is coupled to a latch 142a.

During normal operation, the first shift register 141a of the source driving circuit 14a will receive a start pulse signal STP generated by the timing controller 13a (commonly referred to as Tcon) under the control of a shift clock signal CLK and according to the In order to generate an internal pulse signal and an enable signal En, the following plurality of shift registers 141a will receive the internal pulse signal in the form of ripples under the control of the shift clock signal CLK, and each generate an internal pulse signal accordingly. Enable signal En. According to the enable signal En, the latch (or data register) 142a receives and buffers display data from a data bus for the channel driver 143a to convert the display data into an analog signal In order to drive the liquid crystal display panel 11a to display a picture.

Currently, high-end smartphones are equipped with high-resolution (Resolution) display screens. However, limited by the circuit design of the source driving circuit, the operating system of the mobile phone usually only provides several resolutions for the user to choose to decide the resolution of the display screen. For example, it is known that commercially available smartphones provide three resolutions: HD+ (1480×720), FHD+ (2220×1080) and WQHD+ (2960×1440) for users to choose from. Of course, commercially available smartphones can also provide other resolutions. Specifications of resolution for users to choose. Wherein, for the resolution of 2220×1080, the source driver circuit 14a must have 3240 output channels (channel driver 143a).

3 is a second circuit block diagram of a liquid crystal display panel and a source driving circuit of a conventional liquid crystal display. It should be noted that when controlling the liquid crystal display panel 11a to display an image with a resolution of 1480×720, the source driver circuit 14a only needs to use 2160 output channels (channel driver 143a). In this case, as shown in FIG. 3, the timing controller 13a uses the shift clock signal to make each of the shift registers 141a count-up within a certain period, thereby controlling each of the shift registers 141a at intervals. The channel driver 143a outputs driving signals to the liquid crystal display panel 11a. In more detail, the shift register 141a represented by the dotted line in FIG. 3 means that it does not transmit the corresponding enable signal En to the latch 142a according to the control of the shift clock signal during the specific period. Therefore, the latch 142a will not receive and buffer the display data of the next row from the data bus, and the channel driver 143a will not receive the display data transmitted by the latch 142a.

The resolution adjustment described above is achieved by performing a shift interval processing on a plurality of the selected shift registers 141a, and this resolution adjustment method has been widely used in commercially available source driving chips. Unfortunately, if the user requires the display panel to display images at any resolution due to special needs, such as a resolution of 1480×828, the conventional resolution adjustment method cannot meet this requirement. Therefore, the chip design company needs to specially design the source driver chip supporting this resolution according to the customized method.

It can be seen from the above description that there is an urgent need for a new type of source driver circuit in the art.

The main purpose of the present invention is to provide a source driver circuit, which can be applied in a source driver chip or a flat panel display. Under the premise of not needing special customized circuit design, the source driving circuit of the present invention can correspondingly drive a display panel with any resolution for image display, so it has the advantages of low R&D cost and easy application.

In order to achieve the above object, a source driving circuit is proposed, which has a plurality of channel driving units to drive a display panel, and is characterized in that:

Each of the channel driving units has a display data latch circuit and a pulse signal transmission circuit;

each of the display data latch circuits is coupled to a display data bus and operates according to an enable signal to latch data on the display data bus; and

A plurality of the pulse signal transmission circuits are controlled by a selection signal so that a selected pulse signal transmission circuit generates the enable signal and a pulse signal according to a start pulse signal, and enables the selected pulse signal transmission circuit in the selected pulse signal transmission circuit. The subsequent plurality of the pulse signal transmission circuits transmit the pulse signal therebetween in the form of ripples, and each generates the enable signal according to the pulse signal.

In one embodiment, each of the display data latch circuits has a channel driver and a latch, and the channel driver is used to provide a pixel driving signal according to the data latched by the latch; And each of the pulse signal transmission circuits has an address decoding transmission circuit and a shift register, the address decoding transmission circuit is used to perform a decoding operation on the selection signal according to the content of an address, and in the decoding operation When the result of is true, the start pulse signal is sent to the shift register so that the shift register generates the enable signal and the pulse signal accordingly.

In one embodiment, when a horizontal resolution of the display panel is set to K, where K is a positive integer greater than 1, there will be at least K-1 of the pulse signals after the selected pulse signal transmission circuit. The transmission circuit transmits the pulse signal therebetween in the form of ripples and generates the enabling signal according to the pulse signal.

In one embodiment, the selection signal and the start pulse signal are sent from a timing controller.

In order to achieve the above object, the present invention further provides a flat panel display, which has a display panel and a source driving circuit for driving the display panel, the source driving circuit has a plurality of channel driving units to drive the display panel, and It is characterized by: Each of the channel driving units has a display data latch circuit and a pulse signal transmission circuit;

each of the display data latch circuits is coupled to a display data bus and operates according to an enable signal to latch data on the display data bus; and

A plurality of the pulse signal transmission circuits are controlled by a selection signal so that a selected pulse signal transmission circuit generates the enable signal and a pulse signal according to a start pulse signal, and enables the selected pulse signal transmission circuit in the selected pulse signal transmission circuit. The subsequent plurality of the pulse signal transmission circuits transmit the pulse signal therebetween in the form of ripples, and each generates the enable signal according to the pulse signal.

In one embodiment, each of the display data latch circuits has a channel driver and a latch, and the channel driver is used to provide a pixel driving signal according to the data latched by the latch; And each of the pulse signal transmission circuits has an address decoding transmission circuit and a shift register, the address decoding transmission circuit is used to perform a decoding operation on the selection signal according to the content of an address, and in the decoding operation When the result of is true, the start pulse signal is sent to the shift register so that the shift register generates the enable signal and the pulse signal accordingly.

In one embodiment, when a horizontal resolution of the display panel is set to K, where K is a positive integer greater than 1, there will be at least K-1 of the pulse signals after the selected pulse signal transmission circuit. The transmission circuit transmits the pulse signal therebetween in the form of ripples and generates the enabling signal according to the pulse signal.

In one embodiment, the selection signal and the start pulse signal are sent from a timing controller.

In order to achieve the above object, the present invention further provides an information processing device having the aforementioned flat panel display.

In a possible embodiment, the information processing device may be a smart phone, a tablet computer, a notebook computer, an all-in-one computer, a smart watch or an access control device.

In order to enable your examiners to further understand the structure, characteristics, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred embodiments are attached as follows.

A source driver circuit of the present invention can be applied to a source driver chip or a flat panel display, which includes but is not limited to a liquid crystal display device, an LED display device and an OLED display device. In particular, the source driver circuit of the present invention supports the display panel of the flat panel display to display images at any resolution. Since the source driver circuit of the present invention does not need to be specially designed in a customized manner, the flat panel display including the source driver circuit of the present invention can realize image display with any resolution under the premise of low R&D cost function.

4 is a circuit block diagram of a flat panel display including a source driver circuit of the present invention. As shown in FIG. 4 , the flat panel display 1 mainly includes: a display panel 11 , a gate driving circuit 12 , a source driving circuit 14 , a timing controller 13 , and a gamma voltage generating unit 15 . Please also refer to FIG. 5 , which is a first circuit block diagram of the source driver circuit and the display panel of the present invention. As shown in FIG. 5 , the source driver circuit 14 of the present invention includes Y channel drivers 143 , Y latches 142 , Y shift registers 141 , and Y signal transmission units 140 . According to the design of the present invention, the Y channel drivers 143 are used for coupling to a source driving signal input terminal of the display panel 11 , and Y is a positive integer. In addition, the Y latches 142 are respectively coupled to the Y channel drivers 143 , and the Y shift registers 141 are respectively coupled to the Y latches 142 . On the other hand, the Y signal transfer units 140 are respectively coupled to a shift register 141 , a selection signal SEL and a start pulse signal STP.

If the optimal resolution supported by the flat panel display 1 including the source driver circuit 11 of the present invention is FHD+ (2220×1080), the source driver circuit 11 of the present invention includes a total of 3240 output channels (channel drivers 143 ). In the case where a horizontal resolution of the display panel 11 is set to K=3240, as shown in FIG. 5 , the timing controller 13 sets the content of the selection signal SEL to enable the first signal transmission unit 140 and disable the others The signal transmission unit 140. Accordingly, the first signal transmission unit 140 will transmit the start pulse signal STP to the first shift register 141, and under the control of the shift clock signal CLK, the first shift register 141 will generate a The internal pulse signal and an enable signal En are then transmitted from the second shift register 141 to the 3240th shift register 141 in the form of ripples under the control of the shift clock signal CLK, and each The shift register 141 will generate an enable signal En when receiving the internal pulse signal, thereby enabling 3240 of the shift registers 141 , 3240 of the latches 142 and 3240 of the channel drivers 143 .

As shown in FIG. 5 , each shift register 141 not only transmits the internal pulse signal to the right, but also simultaneously transmits an enable signal En to the latch 142 coupled thereto. After receiving the enable signal En, the latch 142 receives and buffers a display data from a data bus, and the channel driver 143 converts the display data into an analog signal to drive the display panel 11 Display the screen.

In short, the timing controller 13 makes each signal transmission unit 140 receive a start pulse signal STP and a selection signal SEL, and makes each shift register 141 receive a shift clock signal CLK. In addition, when a horizontal resolution of the display panel 11 is set to K=3240, the timing controller 13 sets the content of the selection signal SEL to select the first signal among the Y signal transmission units 140 The transmission unit 140, so that the first signal transmission unit 140 transmits the start pulse signal STP to the first shift register 141, and the first shift register 141 will generate the start pulse signal STP after receiving the start pulse signal STP. Enable signal En and transmit the internal pulse signal to the second shift register 141; each shift register 141 in the second to 3239th shift registers 141 will generate an enabling signal after receiving the internal pulse signal enable signal En and transmit the internal pulse signal to the next shift register 141; and the 3240th shift register 141 will generate the enable signal En after receiving the internal pulse signal. Accordingly, all (3240 in total) shift registers 141 , latches 142 and channel drivers 143 can be enabled in a ripple fashion.

Continue to refer to FIG. 3 , and please refer to FIG. 6 at the same time, which is a second circuit block diagram of the source driving circuit and the display panel of the present invention. The source driving circuit 14 of the present invention supports the display panel 11 of the flat panel display 1 to display images at any resolution. For example, the display panel 11 is controlled to display images at a specific resolution (eg, 1480×720 or 1480×828). It can be seen from FIG. 6 that when the horizontal resolution of the display panel 11 is set to K=2484, by setting the content of the selection signal SEL to select the 379th signal transmission unit 140, the present invention can achieve a ripple method. The 379th to 2862nd (2484) shift registers 141, latches, and channel drivers 143 are enabled.

In addition, FIG. 6 shows the left part represented by the dotted line, the middle part represented by the solid line, and the right part represented by the dotted line, wherein the left part and the right part are both in an inactive state , and the middle part represents the active state. That is, the content of the selection signal SEL is set to select the first signal transfer unit 140 of the middle part, and the number of channels of the middle part is equal to 2484. Accordingly, the source driving circuit 14 can support the resolution of the display panel 11 . In addition, both the left part and the right part may be electrically connected to the display panel 11 or not electrically connected to the display panel 11 . When the right part and the display panel 11 are electrically connected, the source driving circuit 14 can make the internal pulse signal only transmit to the last channel of the middle part through a count value; when the right part and the display panel When 11 is not electrically connected, the source driving circuit 14 can transmit the internal pulse signal to the last channel of the source driving circuit 14 without affecting the display of the picture.

In one embodiment, the signal transfer unit 140 includes a decoder, and the timing controller 13, the Y channel drivers 143, the Y latches 142, the Y shift registers 141, and The Y signal transfer units 140 may be integrated into a source driving chip. As shown in FIG. 6 , the source driver chip including the source driver circuit 1 of the present invention is used to control the display panel 11 to display an image with a horizontal resolution of 2484. At this time, the source driver chip only uses its Output channels 379 to 2862 transmit driving signals to the display panel 11 , that is, the source driver chip uses only 2484 output channels.

Of course, in other feasible embodiments, the timing controller 13 can also be an independent circuit unit.

As can be seen from the above description, the source driving circuit of the present invention has a plurality of channel driving units to drive a display panel, and is characterized in that each of the channel driving units has a display data latch circuit and a pulse signal transmission circuit ; each of the display data latch circuits is coupled to a display data bus and all act according to an enable signal to latch the data on the display data bus; and a plurality of the pulse signal transmission circuits are selected according to a The control of the signal enables a selected pulse signal transmission circuit to generate the enable signal and a pulse signal according to a start pulse signal, and enables a plurality of the pulse signal transmission circuits after the selected pulse signal transmission circuit to ripple The pulse signal is transmitted therebetween by means of waves, and the enabling signal is generated according to the pulse signal.

In addition, each of the display data latch circuits has a channel driver and a latch, and the channel driver is used for providing a pixel driving signal according to the data latched by the latch; and each of the The pulse signal transmission circuits all have an address decoding transmission circuit and a shift register. The address decoding transmission circuit is used to perform a decoding operation on the selection signal according to the content of the address, and the result of the decoding operation is true. At the same time, the start pulse signal is transmitted to the shift register so that the shift register can generate the enable signal and the pulse signal accordingly.

In addition, in the case where a horizontal resolution of the display panel is set to K, where K is a positive integer greater than 1, after the selected pulse signal transmission circuit, there will be at least K-1 of the pulse signal transmission circuits to ripple The pulse signal is transmitted therebetween by means of waves, and the enabling signal is generated according to the pulse signal.

According to the above description, the present invention further provides an information processing device having the above-mentioned flat-panel display, which can be a smart phone, a tablet computer, a notebook computer, an all-in-one computer, a smart watch or an access control device.

Thus, the above has completely and clearly described a source driver circuit of the present invention; and, through the above, it can be known that the present invention has the following advantages:

1. The source driver circuit of the present invention can be applied to a source driver chip or a flat panel display, the flat panel display including but not limited to a liquid crystal display device, an LED display device and an OLED display device, and the source driver of the present invention The circuit can support the display panel to display images at any resolution.

2. The source driving circuit of the present invention does not need to be specially designed in a customized manner, so it can realize the function of displaying images at any resolution under the premise of low R&D cost.

It must be emphasized that the above-mentioned disclosure in this case is a preferred embodiment, and any partial changes or modifications originating from the technical ideas of this case and easily inferred by those who are familiar with the art are within the scope of the patent of this case. category of rights.

To sum up, regardless of the purpose, means and effect of this case, it shows that it is completely different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. Society is to pray for the best.

1a: LCD display 11a: LCD panel 12a: Gate drive circuit 13a: Timing Controller 14a: Source driver circuit 141a: shift register 142a: Latch 143a: Channel Driver 15a: Gamma voltage generating unit 1: flat panel display 11: Display panel 12: Gate drive circuit 13: Timing Controller 14: Source driver circuit 140: Signal transmission unit 141: shift register 142: Latch 143: Channel Driver 15: Gamma voltage generation unit

1 is a circuit block diagram of a conventional liquid crystal display; 2 is a first circuit block diagram of a liquid crystal display panel and a source driving circuit of a conventional liquid crystal display; 3 is a second circuit block diagram of a conventional liquid crystal display panel and a source driver circuit; 4 is a circuit block diagram of a flat panel display including a source driver circuit of the present invention; FIG. 5 is a first circuit block diagram of the source driver circuit and the display panel of the present invention; and FIG. 6 is a second circuit block diagram of the source driver circuit and the display panel of the present invention.

11: Display panel

14: Source driver circuit

140: Signal transmission unit

141: shift register

142: Latch

143: Channel Driver

Claims (10)

A source drive circuit, which has a plurality of channel drive units to drive a display panel, is characterized in that: Each of the channel driving units has a display data latch circuit and a pulse signal transmission circuit; each of the display data latch circuits is coupled to a display data bus and operates according to an enable signal to latch data on the display data bus; and A plurality of the pulse signal transmission circuits are controlled by a selection signal so that a selected pulse signal transmission circuit generates the enable signal and a pulse signal according to a start pulse signal, and enables the selected pulse signal transmission circuit in the selected pulse signal transmission circuit. The subsequent plurality of the pulse signal transmission circuits transmit the pulse signal therebetween in the form of ripples, and each generates the enable signal according to the pulse signal. The source driver circuit of claim 1, wherein each of the display data latch circuits has a channel driver and a latch, and the channel driver is used for latching according to the latch. The data provides a pixel driving signal; and each of the pulse signal transmission circuits has an address decoding transmission circuit and a shift register, and the address decoding transmission circuit is used for performing a selection signal according to the content of an address. A decoding operation is performed, and when the result of the decoding operation is true, the start pulse signal is transmitted to the shift register so that the shift register can generate the enable signal and the pulse signal accordingly. The source driving circuit according to claim 1, wherein, when a horizontal resolution of the display panel is set to K, where K is a positive integer greater than 1, the selected pulse signal transmission circuit will have at least The K-1 pulse signal transmission circuits transmit the pulse signal therebetween in the form of ripples, and each generates the enable signal according to the pulse signal. The source driving circuit of claim 1, wherein the selection signal and the start pulse signal are transmitted from a timing controller. A flat panel display, which has a display panel and a source drive circuit for driving the display panel, the source drive circuit has a plurality of channel drive units to drive the display panel, and is characterized in that: Each of the channel driving units has a display data latch circuit and a pulse signal transmission circuit; each of the display data latch circuits is coupled to a display data bus and operates according to an enable signal to latch data on the display data bus; and A plurality of the pulse signal transmission circuits are controlled by a selection signal so that a selected pulse signal transmission circuit generates the enable signal and a pulse signal according to a start pulse signal, and enables the selected pulse signal transmission circuit in the selected pulse signal transmission circuit. The subsequent plurality of the pulse signal transmission circuits transmit the pulse signal therebetween in the form of ripples, and each generates the enable signal according to the pulse signal. The flat panel display of claim 5, wherein each of the display data latch circuits has a channel driver and a latch, and the channel driver is used to provide the data latched by the latch a pixel driving signal; and each of the pulse signal transmission circuits has an address decoding transmission circuit and a shift register, and the address decoding transmission circuit is used to perform a decoding operation on the selection signal according to the content of the address , and when the result of the decoding operation is true, the start pulse signal is sent to the shift register so that the shift register can generate the enable signal and the pulse signal accordingly. The flat panel display according to claim 5, wherein, when a horizontal resolution of the display panel is set to K, where K is a positive integer greater than 1, the selected pulse signal transmission circuit will have at least K- One of the pulse signal transmission circuits transmits the pulse signal therebetween in the form of ripples, and each generates the enable signal according to the pulse signal. The flat panel display of claim 5, wherein the selection signal and the start pulse signal are transmitted from a timing controller. An information processing device having the flat panel display according to any one of claim 5 to claim 8. The information processing device according to claim 9, which is an electronic device selected from the group consisting of a smart phone, a tablet computer, a notebook computer, an all-in-one computer, a smart watch and an access control device.

Images