JPS63300496A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent occurrence of ringing, by previously lowering the level of an output node so that the charge extracting quantity can be made smaller when the level of the next output node is changed. CONSTITUTION:An output level adjusting signal phix generating circuit section inputs the gate controlling signal phi0 of an output transistor (Tr) Q1 and outputs an output level adjusting signal phix. An output level adjusting circuit section is connected between an output node Dout and earth, and is constituted of a Tr Q3 as an FET, of which the signal phix is inputted to the gate. The signal phix is an one-shot pulse signal which becomes a high level only during a fixed time utilizing the moment when the output node Dout changes from a high level to a high-impedance state, namely, the fall at which the signal phi0 changes from a high level to a low level. By turning on the Tr Q3 for a fixed time immediately after the node Dout changes from the high level to the high- impedance state by utilizing the signal phix, the level of the node Dout is lowered. Therefore, occurrence of ringing can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output section in a semiconductor integrated circuit constituted by MO3 field effect transistors, and particularly to stabilization of output waveforms.

[Prior Art] In a dynamic memory using transistors (MOS), there is a static column mode in which the column address side is statically operated, and cells in the same row can be accessed at high speed by switching addresses. With the realization of page mode or nibble mode, which allows high-speed operation by limiting one-time access to 4 bits, the role of output circuits with respect to external loads has become more important.

FIG. 5 shows a circuit diagram of an output circuit used in a conventional example. This circuit diagram shows a field effect transistor Q1 which is provided between a power supply and an output node Dout, and whose gate is supplied with a signal φ0, and which is connected between the output node Dout and ground (GN
D) and a field effect transistor Q2 whose gate is connected to a signal φO (over par), and generally assumes resistors R1, R2 and a capacitor MC as external loads, and a lead as a stray inductance Ll. The entire system is made up of the wire and the lead bin component.

In this output circuit, the gate signal φ0 of the transistor Q1 on the power supply side is at a high level (when this transistor Q1 is a P-channel transistor, it is at a low level. However, hereinafter, this output transistor will be explained as an N-channel transistor). When the transistor Q1 is turned on, charge is supplied to the output node Dout from the power supply through the transistor Q1, and the output becomes a high level. On the other hand, the ground side transistor Q2
When the gate signal φ0 (over par) becomes a high level, this transistor Q2 is turned on, extracts the charge from the output node Dout, and sets this output node to a low level. Also, some modes during write or refresh, or the column address strobe signal CA
When S (over par) is at a high level, that is, when it is inactive, the two input signals φ0 and φ0 (over par) of this output circuit both maintain a low level, and both transistors Q1 and Q2 are turned off. As a result, the output is kept in a high-impedance state.

Unlike ordinary complementary CMOS inverters, the above output circuit requires tri-state state control including an output high-impedance state, and this output high-impedance state varies depending on the external circuit configuration, and can be either high level or low level. Possible levels include a level floating state and an intermediate potential between the power supply and ground. Figure 5 shows the external load conditions when specifying normal dynamic RAM access, including a capacitor MI 0OPF and two resistors (2T
When the output is high impedance, a certain potential between the power supply and ground determined by these two resistors becomes the output node Dout level.

The output circuit is thus a connection part with an external circuit, and must be tri-state controlled so that its level differs depending on the external circuit. Normally, data out signals φD, φD (over par) and CAS (over par) indicating the relative cell data level data transmitted from the data amplifier to the data out buffer through the human output bus are In the case of bit-based memory, the logic output signal with the signal output enable φE that involves the judgment of OE (Overhaul synchronization), early write, and refresh is set to φ.
0, φO (over par) is common.

Next, differences in the waveform of the output node Dout due to differences in external circuits will be explained using the waveform diagram of FIG. At time 11, the outputs φD and φD (over par) of the data amplifier are settled, and φD is at a high level and φD (over par).
Let's discuss the case where the level is low. When φD and φD (over par) are determined at time tl and the output enable signal φE for the data output bin is activated at time t2, the data output output node Dout becomes high level at time t3. At this time, in the case of the normal output load circuit shown in FIG. 5, the output level changes from an intermediate level between the power supply and ground determined by the resistance value ratio of the external resistors R1 and R2 to a high level of the power supply level. On the other hand, as shown in Fig. 6, when there is no resistance in the external circuit and only a load capacitance, the level of the output contact Dout when the output is high impedance before time t2 is the same as the level of the previous output and is high. It is fixed at either level or low level, and the amplitude when it fluctuates is a full swing between the power supply and ground, such as during address access in static column mode or nibble mode access in high-speed operation. .

Next, at time t4, when performing an operation such as a static column mode in which the output control signal φE remains at a high level and information on the output data Do and DO (over par) of the data amplifier is inverted, the output Similarly, the node Dout performs a static operation, and the gate signals φ0 and φ0 (over par) of the data output transistors are inverted, and the output node DOut also changes with a large amplitude from a high level to a low level. Next, at time 6, when the output control signal φE goes low, the signals φO1φO (over par) both go low, and the output node becomes a high impedance state. In the case of the external resistive circuit shown in FIG. 5, when it enters a high impedance state, the level of the output node DOut tries to return to the intermediate level determined by the resistance ratio, but only the external circuit load capacitance shown in FIG. In this case, the previous output, that is, the low level in this case, is held as long as the output high impedance state continues.

As mentioned above, in the static column mode where the column side is made static, the nibble mode where the deactivation time of CAS (over par) that controls the output is short, and high-speed operation is possible, If the external circuit has only a capacitor as a load, the output node Dout level will be a full swing between high and low levels in any access, and will change with large amplitude and at high speed. I will do it.

[Problems to be Solved by the Invention] When the above-described conventional output circuit adopts the recent static column mode or high-speed nibble mode, the output node Dout must be changed at high speed and with a large amplitude. However, the output transistor is connected to the signal φO
In order to switch quickly at 1φ0 (over par), there is a problem in that ringing occurs in the output level due to external capacitance and parasitic inductance, and substantial access is delayed. In particular, oscillations are likely to occur when changing from a high level to a low level, where the speed at which the charge is extracted by the transistor increases.When the external capacitance is large and the power supply level is high, the range of change in the output node becomes large, and the output transistor Since the amount of charge that Q2 must extract is large, the output voltage is low.
Vibration may occur if the level is exceeded. In other words, there is a problem that actual access becomes slow.

[Means and operations for solving the problems] The first invention of the present application includes a first field effect transistor provided between a first reference voltage source and an output node and to which a first control signal is supplied; an output circuit including a second field effect transistor provided between the second reference voltage source and supplied with a second control signal complementary to the first control signal; and a third field effect transistor, which is provided between the output node and the second reference voltage source and whose gate is supplied with the one-shot pulse signal. It is characterized by having the following.

A second invention of the present application linked to the first invention is a first field effect transistor provided between a first reference voltage source and an output node and to which a first control signal is supplied;
a second control signal provided between the reference voltage source and complementary to the first control signal;
a second field effect transistor to which a control signal is supplied; an output level adjustment signal generation circuit that generates a one-shot pulse signal based on the first control signal; and an output node and a first intermediate node. a first capacitor provided between the first intermediate node and the second intermediate node;
a fourth field effect transistor provided between a reference voltage source and having a gate supplied with the one-shot pulse signal;
and an output level adjustment circuit including a fifth field effect transistor provided between the first reference voltage source and the first intermediate node and having a gate supplied with the first control signal. .

Furthermore, a third invention of the present application linked to the first invention is a first field effect transistor provided between a first reference voltage source and an output node and to which a first control signal is supplied; A one-shot pulse signal is generated based on the first control signal in an output circuit including a second field effect transistor provided between the voltage source and supplied with a second control signal complementary to the first control signal. an output level adjustment signal generating circuit, a first capacitor provided between the output node and the second intermediate node, and a gate provided between the output node and the second intermediate node that receives the one-shot pulse signal; a seventh field effect transistor provided between the second intermediate node and the second reference voltage source and having a gate supplied with the first control signal; The output circuit of each invention of the present application, which is characterized by having an output level adjustment circuit including a second capacitor provided between a node and the second reference voltage source, has the above-mentioned high-speed access, In response to access delays due to ringing during large amplitudes, the first control signal change that precedes data output is used to control the level of the output node, preventing large amplitude changes during accesses and preventing ringing. This is an attempt to substantially speed up access.

Furthermore, in the output circuit according to the second invention and the third invention of the present application,
The level of the output node is determined by the capacitance division between the capacitance of the first capacitor and the second capacitor and the external load capacitance.

Therefore, in contrast to the conventional output circuit described above, the present invention has the following features:
For example, input/output data path, data amplifier output, or
It is characterized by using cell data signals such as output transistor control signals φ0 and φ0 (over par) to reduce the amount of change when the level of the output node changes, which causes ringing. It has the original content of lowering the level of the output node in advance by using the change in the output transistor control signal when the output node changes from low level to low level.

[Example] Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the first invention of the present application.

This circuit diagram includes an output buffer section that determines whether to output cell data, an output transistor section, an output level adjustment signal φX generation circuit section, and an output level adjustment circuit section. A two-man powered NAND game that operates based on complementary signals φD and φD (over par) that transmit data, and an output control signal φE that has information on whether it is a write cycle or a read cycle and refresh information)
It is composed of AI, NA2, inverter 11, and I2.

The output transistor section includes transistors Q1 and Q2 as first and second field effect transistors. In this embodiment, the first reference voltage source is used as the power supply, and the second reference voltage source is used as the ground. The output level adjustment signal φX generation circuit section includes an inverter I3 which receives the gate control field φ0 of the output transistor Q1 as an input signal, and three inverters I
an odd-numbered stage inverter delay section consisting of 4 to I6 (the number of inverter stages in the delay section may be an odd number, and the one-shot width can be determined by this number of stages);
It consists of a two-man powered NAND game (NA3) to which the output N1 of the inverter I3 and the output N2 of the delay section are supplied, and an inverter I7 whose input signal is the output contact N3 of this NAND gate. becomes the output node of the output level adjustment signal φX.

The output level adjustment circuit section includes a transistor Q as a third field effect transistor connected between the output node Dout and the ground, and having the output level adjustment signal φX input to the gate.
Consisting of 3. The output level adjustment signal φX is set at the time when the output node changes from a high level to a bipedance state, that is, the gate signal φ of the output transistor Q1.
This is a one-shot pulse signal that uses the falling edge of 0 to change from high level to low level and remains high level only for a certain period of time. Using this one-shot pulse signal,
Output node Dout in a high float state immediately after the output node changes from high level to high impedance
By turning on the transistor Q3 to which the output level adjustment signal φX is inputted to the gate for a certain period of time, the level of the transistor Q3 is turned on for a certain period of time to reduce the swing width at the next low level output, thereby preventing ringing and substantially speeding up the access. ing.

Next, the operation of this embodiment will be explained using the timing diagram shown in FIG. Before time t1, the old data of the cell is read out, and the complementary data signal φ is output through the data amplifier.
It is assumed that cell data is transmitted to D and φD (over par). At time t1, a read determination for this cycle is made, the output control φE becomes high level, and the output buffer is activated. At time t2, the gate signal φ0 of the output transistor Q1 goes high in response to the high level of the data signal φD and the high level of the output control signal φE. At time t3, in response to the signal φ0 becoming high level, the output transistor Q1 is turned on, and the output node DOut becomes V.

It becomes a high level when it exceeds the h level. When the output control signal φE becomes low level at time t4, φ0 changes to low level. At this time, the output node Dout
The output N1 of the level adjustment signal φX generation circuit is a negative phase signal with a delay of one stage of the inverter with respect to the gate signal φO, and the output N2 of the delay part of the inverters I4, I5, and 6 is a signal with a negative phase with respect to the gate signal φO. , the output N1 becomes a reverse phase signal with a delay of three inverter stages, so the output N3 of the two-man NAND to which these two outputs are supplied becomes a one-shot pulse signal that remains at a low level only for a certain period of time, and the signal φX becomes a one-shot pulse signal that is at a high level only for a certain period of time in the opposite phase. On the other hand, at time t6, the signals φD and φD (over par) are reversed, and the signal φD is at a low level and the signal φD (over par) is at a high level. At time t7, the signal φE is at a high level and the output buffer is activated. At time t8, the gate signal of the output transistor Q2, φ0(
over par) signal becomes high level, and the output node Do
The charge stored in ut begins to be drawn down, but the one-shot pulse signal φX caused by the fall of the signal φ0 at time t5 turns on the transistor Q3 for a certain period of time, so the high float level of the output node Dout is discharged. It can be lowered to some extent. The level of the output node Dout here is the one-shot pulse signal φ0
can be set freely by the high level width. In this manner, at time t8, the amount of charge can be reduced before the charge is rapidly extracted by the output transistor Q2, so ringing can be prevented, and access delays due to ringing as shown in the conventional example can be prevented. can.

FIG. 3 is a circuit diagram of an embodiment of the second invention of the present application, showing a second output level adjustment circuit of the output circuit.

This circuit includes a capacitor C2 connected between the output node Dout and the contact N4, and a transistor serving as a fifth field effect transistor connected between the power supply and the contact N4 and whose gate is supplied with the output transistor control signal φ0. Q6 and
The fourth field effect transistor Q4 is connected between the contact N4 and the ground and has an output level adjustment signal φX input to its gate. Similar to the embodiment of the first invention, the output level adjustment signal φX is a one-shot signal that remains at a high level only for a certain period of time. When the output node Dout is at a high level, the transistor Q5 whose gate receives the signal φ0 is on, so the contact N4 is charged to a high level. On the other hand, at this time, the transistor Q4 is not turned on because the signal φX is at a low level. At time t5, the transistor Q4 is turned on by the one-shot pulse signal φX triggered by the fall of the signal φ0 from the high level of the output node Dout to high impedance. As a result, the level of the contact N4 is lowered, and the level of the output node Dout is lowered through the capacitor C2. At this time, since the signal φ0 is at a low level, the transistor Q5 is not turned on and no through current flows. Further, the withdrawal level of the output node is determined by the capacitance ratio between the external load capacitance C1 and the capacitor C2. As a result, the amount of charge extracted from the output node at time 18 when the φ0 (over par) signal becomes high level is reduced, ringing can be prevented, and access delay can be prevented.

FIG. 4 is a circuit diagram of an embodiment of the third invention of the present application, and similarly to the embodiment of the second invention, only the third output level adjustment circuit of the output circuit is shown. This circuit diagram shows the output node Dout
and a transistor Q6 as a sixth field effect transistor connected between the contact N5 and the gate and inputting the output level adjustment signal φX to the gate, and a sixth field effect transistor connected between the contact N5 and the ground and inputting the output control signal φ0 to the gate. 7 Consists of a transistor Q7 as a field effect transistor and a capacitor C3 connected between a contact N5 and the ground, and when the output level is high, the transistor Q7 is in an on state.
Since transistor Q6 is in an off state, contact N5 is kept at a low level.

When the signal φ0 becomes low level and a one-shot high level of φX occurs, the transistor Q7 is turned off.
Transistor Q6 remains on for a certain period of time. Therefore, the level of the output node Dout is lowered by capacitance division between the external load capacitor 11c1 and the capacitor C3, and as in the embodiment of the second invention, ringing is prevented and access delay can be prevented.

[Effects of the Invention] As described above, the present invention has the advantage that, when the first control signal, such as the gate signal of the output transistor, falls, that is, the output node changes from the first reference voltage level to high impedance (high float). By generating a one-shot pulse signal that is triggered by the point at which the output level changes to The amount of charge extracted by the second field effect transistor when the level of the node changes can be reduced.

As a result, ringing can be prevented and substantial access delays can be prevented. Moreover, the level of the output node is only lowered when the output high level changes to the high float level, and the level object is also
This can be done by adjusting the one-shot pulse width of the output level adjustment signal, that is, the delay width of the output adjustment signal generation circuit as in the invention, or by adjusting the value of the capacitor with respect to the external capacitor JICI as in the second and third inventions. .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the first invention, FIG. 2 is a graph showing waveforms of main signals of the output section, FIG. 3 is a circuit diagram showing an embodiment of the second invention, and FIG. 4 is a circuit diagram showing an embodiment of the third invention, FIGS. 5 and 6 are circuit diagrams showing the configuration of a conventional output circuit including an external load circuit, and FIG. 7 is a waveform diagram of the conventional example. . Ql, Q2. Q3. Q4. Q5.
Q6. Q7...Electric field transistor, NA1, NA2, NA3...
Nant gate, ■1 to I7...inverter, CI, C2...capacitor. Patent applicant: NEC Corporation Representative Patent attorney Kiyoshi Kuwai - Figure 1 Figure 3 Figure 4 Figure 2 Figure 5 Figure 6

Claims (3)

[Claims] (1) a first field effect transistor provided between a first reference voltage source and an output node and supplied with a first control signal;
a first reference voltage source provided between the output node and the second reference voltage source;
An output circuit comprising: a second field effect transistor to which a second control signal complementary to the control signal is supplied; an output level adjustment signal generation circuit for generating a one-shot pulse signal based on the first control signal; An output level adjustment circuit comprising a third field effect transistor provided between a node and a second reference voltage source and having a gate supplied with the one-shot pulse signal. (2) a first field effect transistor provided between the first reference voltage source and the output node and supplied with the first control signal;
a first reference voltage source provided between the output node and the second reference voltage source;
An output circuit comprising: a second field effect transistor to which a second control signal complementary to the control signal is supplied; an output level adjustment signal generation circuit for generating a one-shot pulse signal based on the first control signal; a first capacitor provided between the node and the first intermediate node;
a fourth field effect transistor provided between the first intermediate node and the second reference voltage source and having a gate supplied with the one-shot pulse signal; an output level adjustment circuit comprising: a fifth field effect transistor provided between the transistors and having a gate supplied with the first control signal; (3) a first field effect transistor provided between the first reference voltage source and the output node and supplied with the first control signal;
a first reference voltage source provided between the output node and the second reference voltage source;
An output circuit comprising: a second field effect transistor to which a second control signal complementary to the control signal is supplied; an output level adjustment signal generation circuit for generating a one-shot pulse signal based on the first control signal; a sixth field effect transistor provided between the node and the second intermediate node and having the gate supplied with the one-shot pulse signal; and a sixth field effect transistor provided between the second intermediate node and the second reference voltage source and having the gate supplied with the one-shot pulse signal. The output level adjustment circuit includes a seventh field effect transistor to which the first control signal is supplied, and a second capacitor provided between the second intermediate node and the second reference voltage source. An output circuit featuring: