JPS6330019A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a circuit device including a delay element without remarkable increase in the power consumption and component number by providing two kinds of level converting circuits converting logic level between a CMOS logic circuit and a high speed logic circuit in order to connect the both. CONSTITUTION:The 1st level conversion circuit 1 converts a logic signal (ECL in) of the ECL(emitter coupling logic) level into a logic signal of the CMOS level. Further, the 2nd level converting circuit 2 converts the logic signal of CMOS level into the logic signal of the ECL level. Moreover, a high speed logic circuit 4 comprising ECL and a low power consumption logic circuit 3 comprising CMOS, and also the 1st and 2nd two/kind of level conversion circuits 1, 2 converting the logic level between the two kinds of logic circuits mutually are provided. Thus, while the high speed logic circuit 4 comprising, e.g., ECL is constituted, the block including a delay element for timing adjustment is constituted with a comparatively few element number and low power consumption by the CMOS logic circuit 3.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention is a technology that is effective when applied to semiconductor integrated circuit technology, and furthermore, to semiconductor integrated circuits in which high-speed logic circuits such as ECL (emitter coupled logic) are formed. It is related to
For example, fast RAM with ECL interface
(Random Access Memory).

[Prior Art] Recently, for example, published by Nikkei McGraw-Hill, "Nikkei Electronics, March 1, 1986 issue (no, 390)
Bipolar-CMO described in J 199-217
High-speed, highly integrated static RAM with an ECL-level input/output interface, such as S RAM.
has been developed.

Here, the present inventor will consider a high-speed static RAM having an ECL interface.The following is a technique that has been considered by the present inventor, although it is not a publicly known technique, and its outline is as follows. That's right.

FIG. 12 shows an outline of a high-speed static RAM studied by the present inventor.

First, the static RAM 200 shown in the figure includes a memory cell array 100, an input buffer 101, an address buffer 102, an X decoder/driver 103, a Y decoder/driver 104, a Y selection switch 105, a write buffer 106, and a sense circuit. 107, sense output buffer 1
08, an input/output buffer 109, a control circuit 110, and the like.

Here, in the memory cell array 100, a large number of memory cells m are arranged in the XY (row and column) directions. Each memory cell m
Although not shown, it is constituted by a flip-flop type holding circuit using an n-channel MO3) transistor. This memory cell m is arbitrarily selected by a word line WL wired in the X direction and a data line (or bit 1ll) DL wired in the Y direction.

The input buffer 101 includes an ECL-CMOS level conversion function, converts an address signal Ain inputted at an ECL logic level into a CMOS level, and supplies the converted signal to an address buffer 102 .

The address buffer 102 is constituted by a so-called B1-CMOS type high-speed logic circuit in which bipolar and CMOS are combined in the logic circuit. This address buffer 102 phase-divides the input address signal Ain to create a logic signal pair of positive logic and negative logic for each bit.

This logical signal pair is used by decoder driver 103 and Y
It is distributed and given to the decoder driver 104.

The X decoder driver 103 and the Y decoder driver 104 are also constructed of B i-CMOS type high-speed logic. The X decoder driver 103 decodes the X selection signal that selects the memory cell m from the X direction. An arbitrary word line W is alternatively selected and driven by this decoded X selection signal. On the other hand, the Y decoder driver 104 converts the memory cell into Y
Decode the X selection signal that selects from the direction. This decoded X selection signal is applied to the Y selection switch 105. The Y selection switch 105 connects any pair of data lines DL designated by the X selection signal to the common data line Dc.

As described above, an arbitrary memory cell m is selected from the X direction and the Y direction based on the address signal Ain, and this selected memory cell m is connected to the common data line Da.

During a memory write operation, the input/output buffer 109
The write data (Da
ta in) is written into the selected memory cell m via the write buffer 106, the common data line Dc, the Y selection switch 105, and the selected data line DL, respectively.

On the other hand, during the memory read operation, the storage information of the selected storage cell m is transferred to the selected data line DL-Y! ! Selection switch 105-
The sense circuits 107 are connected to each other via common data lines Dc.
is read by Although not shown, the sense circuit 107 is configured to read stored information appearing on the common data line Dc using a differential pair of bipolar transistors, and output the read output, that is, the read data at the ECL level. The data Vout read by this sense circuit 107 is sent to the input/output buffer 109 via the intermediate output buffer 108 by ECL.
From there, ECL level read data (Data out
t) is output to the outside.

The input/output buffer 109 is constituted by ECL and is operated as an input buffer during a write operation and as an output buffer during a read operation. Its mode of operation is controlled by a write/read control signal ττ+WE issued from control circuit 110.

The control circuit 110 generates a control signal for controlling the operation of the turnout buffer 109 and other parts based on the externally applied chip selection signal (2) and the write control signal 7τ. This control circuit 110 is also constituted by an ECL, and receives the above three signals and Wτ from the outside at the ECL level to produce a control signal t17+WE etc. at the ECL level.

As described above, only the storage section and its vicinity are converted into MOS
By configuring the RAM 200 with B1-CMOS and configuring its peripheral and control portion with ECL, a high-speed and highly integrated RAM 200 can be obtained.

[Problems to be Solved by the Invention] However, the inventors have found that the above-mentioned technique has the following problems.

That is, like the RAM 200 mentioned above, semiconductor integrated circuit devices using high-speed logic circuits such as ECL have the advantage of high-speed operation, but the high-speed operation makes it difficult to use semiconductor integrated circuit devices. The inventors have found that this poses another problem in that it may make it difficult.

For example, in the RAM 200 described above, the write/read control signal ττ+WE is generated based on the externally applied chip selection signal τ and the write control signal Wτ, and the read data Vout is generated externally using the write/read control signal U+wE. Controls the input/output buffer 109 for outputting to
At this time, since the ECL logic circuit in the control system operates at high speed, as shown in FIG. The time Tc until 1+WE is activated by the read/write control signal is much faster than the time Tm1n to Tmax until the read data from the sense circuit 107 is determined. Of the time during which the read operation mode is switched, the effective read time Tv during which the read data Vout from the sense circuit 107 can be reliably read externally becomes short. In other words, when externally sending 100 with the address signal Ain and chip selection signal to continuously output stored data,
The inventors of the present invention have found that a problem arises in that the timing at which the stored data can be read is very short and becomes difficult. Also, Tc
The inventors have found that during the period -Tm1n, the output is not determined, causing a problem in which an intermediate level occurs in the output.

Therefore, in order to solve the above-mentioned problem, the present inventors considered providing a delay circuit using ECL to adjust the timing of 5+WE using a write/read control signal.

However, as mentioned above, the write/control signal τ5+
WE is a signal transmitted through a high-speed ECL logic circuit. Therefore, its write/control signal (:5+W
If we try to configure a delay circuit that adjusts the timing of E, we will have to connect a large number of ECLs in multiple stages, which creates another problem: a large increase in power consumption and the number of elements. The inventors have found that this is the case.

An object of the present invention is to provide a semiconductor integrated circuit in which high-speed logic circuits such as the above-mentioned R A, M are formed,
An object of the present invention is to provide a technology that enables a circuit device including delay elements for timing adjustment, etc., without significantly increasing power consumption or the number of elements.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, for example, a high-speed logic circuit using ECL and a CM
A low power consumption logic circuit by the OS is formed together, a delay element for timing adjustment etc. is configured by the CMOS logic circuit, and the CMOS logic circuit is connected to the high speed logic circuit. 1. Mutual logic level conversion between two types of logic circuits. A second type of level conversion circuit is provided.

[Operations] According to the above-described means, a high-speed logic circuit can be constructed using ECL, for example, while a portion including delay elements can be constructed with a relatively small number of elements using a CMOS logic circuit. This achieves the purpose of providing a relatively large delay element for timing adjustment in a high-speed logic circuit using ECL or the like without significantly increasing power consumption or the number of elements.

[Examples] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

In each figure, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a main part of a circuit formed in a semiconductor integrated circuit device to which the technology according to the present invention is applied.

The circuit part shown in the figure is an EC
An input buffer circuit INPUT CIRCUIT is partially formed in a high-speed logic circuit formed by L and receives an ECL level input signal as one circuit block among the plurality of circuit blocks, and an input buffer circuit lNPt1T C4RCUIT as a high-speed logic circuit of the circuit block, and an input buffer circuit INPUT CIR,CU as the high-speed logic circuit 4.
a first level conversion circuit 1 that converts an IT logic level to a CMOS (complementary field effect transistor) logic level; a CMOS logic circuit 3 that is operated with low power consumption as an electronic circuit including a delay element; The above CMOS
a second level conversion circuit 2 that converts the logic level of the logic circuit 3 to the logic level of the high-speed logic; and another circuit among the plurality of circuit blocks that receives the output of the second level conversion circuit 2. A high-speed logic circuit 4 based on ECL as a block is shown.

Here, the high-speed logic circuit 4 based on ECL includes bipolar transistors Q41. Q
This differential pair includes 42 differential pairs of bipolar transistors Q41. The respective emitters of Q42 are commonly connected, and this common emitter is connected to the negative side power supply VEH via the constant current circuit Ics. On the other hand, the bipolar transistor Q41. Each collector of Q42 is connected to the positive power supply potential VCC via load resistors R41' and R42, respectively. Then, by inputting a logic signal to one of the bipolar transistors Q41 and applying a predetermined reference potential Va to the base of the other bipolar transistor Q42, both transistors Q41
．． Mutually complementary logic signals are output from the collector side of Q42. Note that the positive power supply VCC is determined based on the ground potential GND.

For example, as shown in the figure, the CMOS logic circuit 3 includes delay circuits 0M31-1 to M31-n and
B2-1~M32-n are inverters 3-1~
3-n shows a p-channel MOS transistor and an n-channel MOS transistor.

The first level conversion circuit 1 converts the ECL level logic signal (
This is an ECL-MOS level conversion circuit that converts ECL in) into a CMOS level logic signal. The front stage side of the first level conversion circuit 1 includes bipolar transistors Qll to Q15, a constant current circuit ■cs, and a resistor R1.
1 and R12 form an ECL type input circuit. Further, on the subsequent stage side, there are a p-channel MOS transistor M13, n-channel MOS transistors M16 to M18, and a bipolar transistor Q16. Q
17, a B1-CMOS type buffer circuit is formed. Between the front stage side and the rear stage side, p-channel MOS transistors Mll and M12 and n-channel MOS transistors M14. A level conversion section using M2S is formed. This level converter converts the level of ECL-CMOS using current mirror operation.

The second level conversion circuit 2 is a CMOS-level converter that converts a CMOS level logic signal into an ECL level logic signal.
This is an ECL level conversion circuit. This second level conversion circuit 2 includes CMOS transistors M21 and M22.
MOS inverter and this CMOS inverter
Power supply potential V CC' at approximately the same level as the logic level of CL
V RE' (V cc > V cc'> V EE
'> VE! ＞.

This voltage control circuit includes a diode D21, a resistor R21,
R22, constant current circuit Ics, and bipolar transistor Q21, and has the same potential as the logic level of ECL (Vcc''' = 0.6V, v, , ' =
-2, iv). In this case, diode D21
is inserted in series to the positive side of the power supply potential ■cc, thereby creating a potential Vcc' (approximately -0.6V) that is a certain potential (approximately 0.6V) more negative than the power supply potential VCC. Also, the bipolar transistor Q21 has a resistor R
Potential ■ arbitrarily determined by 21 and R22. ′ (
-2, IV) on its emitter side. As a result, even if the input of the inverter formed by CMOS transistors M21-M22 is driven by a CMOS level logic signal, the above potentials VCC°-VE,'
(VcC' Misaki-0,6, VER'Ki-2,1'V)
Outputs an ECL level logic signal with an amplitude within the range of .

As described above, the high-speed logic circuit 4 and CM using ECL
Along with the low power consumption logic circuit 3 by the OS, the first . By providing the second two types of level conversion circuits 1 and 2, the high-speed logic circuit 4 can be constructed using ECL, for example, while the portion including delay elements is
The MOS logic circuit 3 allows a configuration with a relatively small number of elements and low power consumption. This results in
E without significantly increasing power consumption or number of elements.
The purpose of providing the high-speed logic circuit 4 using CL with a relatively large delay element for timing adjustment etc. is achieved.

FIG. 2 shows an embodiment of a RAM to which the technology according to the present invention is applied.

The RAM 200 shown in the figure is configured as a high-speed, highly integrated static type RAM having an ECL interface.

First, the static RAM 200 shown in the figure includes a memory cell array 100, an input buffer 101, an address buffer 102, an X decoder/driver 103, an X decoder/driver 104, a Y selection switch 105, a write buffer 106, and a sense circuit. 107, sense output buffer 1
08, an input/output buffer 109, a control circuit 110, and the like.

Here, in the memory cell array 100, a large number of memory cells m are arranged in the XY (row and column) directions. Each memory cell m
Although the details will be described later, it is constituted by a flip-flop type holding circuit using an n-channel MOS transistor. This memory cell m is arbitrarily selected by a word line WL wired in the X direction and a data line (or bit line DL) wired in the Y direction.

The input buffer 101 includes an ECL-CMOS level conversion function, converts an address signal Ain inputted at an ECL logic level to a CMOS logic level, and provides the address signal Ain to the address buffer 102 .

The address buffer 102 is bipolar and cM.

The so-called Bj-CM in which S and S are combined in a logic circuit.
It is composed of an OS-type high-speed logic circuit. This address buffer 102 phase-divides the input address signal Ain to create a logic signal pair of positive logic and negative logic for each bit. This logical signal pair is the decoder driver 10
3 and X decoder driver 104.

The X decoder driver 103 and the X decoder driver 104 are also constructed from B1-CMOS type high-speed logic. The X decoder driver 103 decodes the X selection signal that selects the memory cell m from the X direction. An arbitrary word line WL is alternatively selected and driven by this decoded X selection signal.

On the other hand, the Y; Korg driver 104 decodes the X selection signal that selects the storage cell from the left direction. This decoded X selection signal is applied to the Y selection switch 105. The Y selection switch 105 connects any pair of data lines DL designated by the X selection signal to the common data line Dc.

As described above, an arbitrary memory cell m is selected from the X direction and the Y direction based on the address signal Ain, and this selected memory cell m is connected to the common data line Dc.

During a memory write operation, the input/output buffer 109
The write data (Da
ta in) is written into the selected memory cell m via the write buffer 106, the common data line Da, the Y selection switch 105, and the selected data line DL, respectively.

On the other hand, during the memory read operation, the stored information of the selected memory cell m is sent to the sense circuit 107 via the selected data line DL-Y selection switch 105-common data line Dc, respectively.
is read by Although the details will be described later, the frequency circuit 107 is configured to read the stored information appearing on the common data line Da using a differential pair of bipolar transistors, and output the read output, that is, the read data at the ECL level. The data Vout read by this sense circuit 107 is sent to the input/output cover buffer 109 via the ECL intermediate output buffer 108, and from there the read data (Data
output) to the outside.

The input/output buffer 109 is constituted by ECL and is operated as an input buffer during a write operation and as an output buffer during a read operation. Its mode of operation is controlled by the write 7/read control signal -5-'+wE issued by control circuit 110.

Control circuit 110 generates a control signal for controlling the operation of turnout buffer 109 and other parts based on externally applied chip selection signal 1 and write control signal WE. This control circuit 110 is also constituted by ECL, and receives the above-mentioned signal τ and W from the outside at the ECL level to generate a control signal C5+WE at the ECL level.

FIG. 3 shows a detailed circuit example near the sense circuit 107.

As shown in the figure, the memory cell m is an n-channel MOS
Transistors M101 to M104 and high resistance load RIOI
, R102. The sense circuit 107 also includes bipolar transistors Q71. A differential circuit consisting of Q72 and MoS transistor M71, and a bipolar transistor Q73. Q74 and constant current circuit Ic
It has a common base type amplifier circuit based on s. Intermediate output buffer 108 includes bipolar transistor Q81,
It has an emitter follower input circuit using Q82 and a constant current circuit Ics, an emitter coupling logic using bipolar transistors Q8B and Q84 and a constant current circuit Ics, and an emitter follower output circuit using a bipolar transistor Q85.

In addition, in FIG. 3, n-channel MOS transistors M51. M52 constitutes a part of the Y selection switch 105. Yy indicates a Y selection signal, and p-channel MOS transistor M53 connects a pair of data lines DL-
A so-called data line potential equalizer is configured to equalize the potential between DL when not selected. Further, reference numeral 111 is a potential generation circuit that applies a predetermined bias potential to the common data line Dc.

As described above, first, by configuring only the storage section and its vicinity with Mo3 and B i-CMo3, and configuring its periphery and the control portion with ECL, a high-speed and highly integrated RAM 200 can be realized. It is now possible to obtain it.

Furthermore, the static type RAM 2 of the embodiment shown in FIG.
00, in addition to the above-described configuration, a C M 0S logic circuit 3 is provided that constitutes a delay circuit 5 using a multi-stage inverter array. Along with this, the CMOS logic circuit 3
The output of the control circuit 110 is connected to the input of the control circuit 110 via the first level conversion circuit 1 shown in FIG. Also,
The output of the CMOS logic circuit 3 is the second
It is connected to the operation mode control input of the input/output buffer 109 via the level conversion circuit 2 of the input/output buffer 109 .

As a result, the ECL level write/read control signal output from the control circuit 110 converts the level of τ+WE from the ECL level to the CMOS level, and then converts the level of the ECL level to the CMOS level.
A predetermined delay operation is performed by the delay circuit 5 of the S logic circuit 3. The delayed CMOS level write/read control signal 5+WE is then level-converted to the ECL level again and is then applied to the input/output buffer 109 as an operation mode control signal.

Then, as shown in FIG. 4, after the externally applied chip selection signal becomes active (changes to H mustard),
The time Tc' until @+WE is activated by the write/read control signal applied to the input/output buffer circuit 109 is extended by the delay time td caused by the delay circuit 5. As a result, the time Tm1n to Tm1n until the read data ■out from the sense circuit 107 is determined.
The timing difference between max and the time (Tc') at which the input/output buffer 109 is switched to continuous output mode becomes smaller.

As a result, the effective reading time Tv that allows successive data to be reliably read from the outside via the input/output buffer 109 becomes substantially longer. In other words, the address signal Ain and the chip selection signal from the outside? When reading stored data by sending 7r, there is a margin in the timing at which the stored data can be read. moreover,
The time required to generate an output intermediate level between TC and Tm1n can be reduced. This reduces its RAM to 200
It becomes very easy to design systems that use . Moreover, the delay circuit 5 for timing adjustment described above is made of a CMOS logic circuit with low power consumption and relatively low speed.
The structure can be configured without significantly increasing power consumption or the number of elements.

FIG. 5 shows an embodiment in which the technique according to the present invention is applied to high-speed logic circuits other than RAM.

As shown in the figure, input/output buffer 6 and E
Also in the general logic semiconductor integrated circuit device 201 having a high-speed logic circuit 4 based on CL, the high-speed logic circuit 4 has a first . By connecting the CMOS logic circuit 3 through the second two types of level conversion circuits 1 and 2, the delay elements required in the high-speed logic circuit 4 can be reduced in power consumption by the delay circuit 5 in the CMOS logic circuit 3. FIG. 6 shows a modification of the second level conversion circuit 2 that performs 0MO3-ECL level conversion.

As shown in the figure, the second level conversion circuit 2 includes a plurality of sets of transistors Mll-1°M21-1. Ml
1-2. By using M21-2, any logical function can be provided. The level conversion circuit 2 shown in the figure is a NAND logic circuit that takes an indefinite logical product A''3 of two logic inputs A and B.

FIG. 7 shows an example of an application circuit of the delay circuit 5 formed in the CMOS logic circuit 3 described above.

In the application example shown in the figure, a pulse width reduction circuit is configured by CMOS inverters 3-1 to 3-2n in even columns (2n columns) and a NAND gate G1.In this case, as described above, level conversion NAND gate G1 in circuit 2
can contain logical functions.

FIG. 8 shows an example of the operation of each part of the circuit shown in FIG. 7 using a waveform chart.

FIG. 9 shows another application circuit example of the delay circuit 5 formed in the CMOS logic circuit 3 described above.

In the application example shown in the figure, an odd number column (2n-1 column) CMO
S inverter 3-1 to 3- (2n -1) and NAND
An edge trigger circuit is configured by the gate G1. Also in this case, as described above, the level conversion circuit 2 can include the logic function of the NAND gate G1.

FIG. 10 shows an example of the operation of each part of the circuit shown in FIG. 9 using a waveform chart.

FIG. 11 shows an embodiment in which a high-speed logic circuit 4 based on ECL is partially formed in a semiconductor integrated circuit device mainly formed with a CMOS logic circuit 3. In this case, EC
High-speed logic 4 based on L is the second, first level conversion circuit 2.
1 to a CMOS logic circuit 3 and a CMOS level input/output buffer 6. This allows CMOS
A high-speed logic function can be provided in the logic circuit 3 by a high-speed logic circuit 4 based on ECL.

Above, the invention made by the present inventor has been specifically explained based on the examples, but it should be noted that the present invention is not limited to the above examples and can be modified in various ways without departing from the gist thereof. Not even. For example, the logic circuit format constituting the high-speed logic circuit 4 may be, for example, TTL.

In the above description, the invention made by the present inventor was mainly applied to a logic semiconductor integrated circuit device, which is the field of application in which the invention was made, and in particular to a static type RAM, but the invention is not limited thereto. For example, it can be applied to analog/digital mixed type semiconductor integrated circuit devices.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, in a semiconductor integrated circuit in which a high-speed logic circuit such as a RAM with an ECL interface is formed,
The advantageous effect is that a circuit device including delay elements for timing adjustment etc. can be realized without significantly increasing power consumption and the number of elements.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of a circuit in a main part of a high-speed logic semiconductor integrated circuit device to which the technology according to the present invention is applied, and FIG. 2 is a block diagram showing the configuration of a RAM to which the technology according to the present invention is applied. , FIG. 3 is a diagram showing a detailed circuit example of a part of FIG. 2, FIG. 4 is a timing chart showing an example of the read operation of the RAM shown in FIG. 2, and FIG. 5 is a high-speed circuit diagram to which the present invention is applied. A block diagram showing another embodiment of a logic semiconductor integrated circuit device, FIG. 6 shows an ECL formed in a semiconductor integrated circuit device to which the present invention is applied.
-A diagram showing a modified example of a CMOS level conversion circuit; FIG. 7 is a diagram showing an example of a circuit formed in a semiconductor integrated circuit device to which the present invention is applied; FIG. 8 is a circuit shown in FIG. 7; 9 is a diagram showing another example of a circuit formed in a semiconductor integrated circuit device to which the present invention is applied, and FIG. 10 is an example of the operation of the circuit shown in FIG. 9. 11 is a block diagram showing yet another embodiment of a semiconductor integrated circuit device to which the present invention is applied; FIG. 12 is a block diagram showing the configuration of a RAM studied prior to the present invention; FIG. 13 is a timing chart showing an example of the read operation of the RAM shown in FIG. 12. 1...First level conversion circuit (ECL-CMOS
level conversion circuit), 2...second level conversion circuit (E
CL-CMOS level conversion circuit), 3... CMOS logic circuit, 4... Bipolar high-speed logic circuit such as ECL, 5... Delay circuit, 6... Input/output buffer,
M21. M22...CMOS transistor for configuring the second level conversion circuit 2, VQC, VEE・
...Power supply potential, vcc', v, ε'...Power supply potential for operating the second level conversion circuit. Figure 4 Figure 5 Figure 10 Figure 11

Claims (1)

[Claims] 1. (1) a plurality of circuit blocks; (2) a first level conversion circuit that converts the signal amplitude of an output signal sent from one circuit block among the plurality of circuit blocks; (3) an electronic circuit including a delay element that receives the output of the first level conversion circuit; and (4) receives the output of the electronic circuit and transmits an output signal responsive to the input signal into the plurality of circuit blocks. The other 1
1. A semiconductor integrated circuit comprising: a second level conversion circuit that sends data to one circuit block; 2. The electronic circuit is composed of a CMOS (complementary field effect transistor), and the first and second level conversion circuits are composed of a bipolar transistor and a CMOS,
The one circuit block that applies an input signal to the first level conversion circuit and the other circuit block that receives the output signal of the second level conversion circuit are comprised of bipolar transistors. A semiconductor integrated circuit according to claim 1. 3. The first level conversion circuit has an ECL logic signal of C
2. The semiconductor integrated circuit according to claim 1, wherein the level of the CMOS logic signal is converted into an ECL logic signal, and the second level conversion circuit converts the level of the CMOS logic signal into an ECL logic signal. 4. A patent characterized in that the operating power supply of the second level conversion circuit is varied in accordance with the logic amplitude of the other one circuit block that receives the output of the second level conversion circuit. A semiconductor integrated circuit according to claim 1. 5. The semiconductor integrated circuit according to claim 1, wherein the electronic circuit including the delay element is a logic block. 6. The plurality of circuit blocks include a high-speed logic circuit block and a low power consumption circuit block, and the circuit elements constituting the electronic circuit including the delay element and the low power consumption circuit block are made of CMOS, and Claim 1, wherein the high-speed logic circuit block and the other circuit block receiving the output signal of the second level conversion circuit are made of bipolar transistors and are formed on the same substrate. Semiconductor integrated circuit described in Section 1. 7. The low power consumption circuit block is composed of a plurality of memory cells made of CMOS, and the high-speed logic circuit block is an address circuit for selecting an arbitrary memory cell from the plurality of memory cells, The other circuit block that receives the output of the second level conversion circuit includes a sense circuit that amplifies the information read to the data line pair of the memory cell, and a data circuit that sends the output signal of the sense circuit to the outside. Claim 6, characterized in that it includes an input/output buffer circuit, and delays and transmits a chip select signal and/or write enable signal at an ECL logic level inputted from the outside to the data input/output buffer. Semiconductor integrated circuit.