JPS63298569A - Conductor pattern designing apparatus and method for printed circuit board - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an apparatus and method for designing conductor patterns for printed circuit boards.

BACKGROUND OF THE INVENTION In the computer-aided design of printed circuit boards, the pattern of point-to-point conductors or interconnects routed through one or more layers is typically automated or "maze-based".
This is achieved using an algorithm. In this method,
An expanding database, i.e., a conductor pattern extending from a point within a connected set of points, until the map of available locations expands to include another point (or points) in the same set. Create a map of available locations. Various algorithmic methods are commercially available to accomplish this function. To ensure that several printed circuit board standards are met, automatic routing methods are used to ensure that several printed circuit board standards are met, such as minimum conductor size, minimum conductor spacing, number of allowable paths or interlayer connections, and overall conductor length.
It operates according to an interconnection protocol that defines some constraints on the conductor patterns between points. These protocols can be generic, applying to the entire printed circuit board, or they can vary in terms of each set of interconnects, which is especially common in complex multilayer circuit board designs. After processing the entire list of point pairs that should be interconnected using automatic routing, some pairs cannot be interconnected using the automatic routing method based on the protocol given for that printed circuit board. things are discovered.

(Problem to be Solved by the Invention) Automatic routing requires that once a list of point pairs that cannot be automatically interconnected is established, an operator must manually interconnect the list of points. It should be noted that manually interconnecting sets of points left by the scheme by an operator is a very time consuming and frustrating process.

SUMMARY OF THE INVENTION In accordance with the teachings of the present invention, the task of manually completing the interconnection of each set of points left undone by an automatic routing scheme for a printed circuit board is replaced by an interconnection protocol. Based on
By providing an operator with an indication representing the area on the printed circuit board to which a conductor can extend from each point in the set of points to which a connection is not successful through an automatic routing scheme, the system of the present invention achieved. To simplify the operator's task of determining how the interconnection is done, logical operations are performed on the regions, which provides minimal disruption to the interconnection protocol. In general use,
Such logical operations include displaying one or the other region with respect to a point within a set of unconnected points, displaying the conjunction between regions, displaying possible jumper wire positions between regions, and logic of regions. An indication of the summation number or point of closest approach between locations in the region for each point in the unconnected set is included. Such information provided to the operator may lead to one or more violations of the protocol, such as increasing the number of paths or using jumper wires between points, to make room for additional conductors connecting both specified points. Use or
or by relaxing the protocols applicable to already completed interconnections, thereby simplifying the task of operators in devising the final interconnection strategy.

Based on logical operations on the area for each point, it can be automatically applied to unconnected or previously connected points, allowing automatic completion of wiring with an acceptable compromise to circuit board performance. Additionally, a database containing prioritized relaxations of protocols is provided.

To improve efficiency and minimize the performance penalty due to forced completion of interconnects between points, the list of each pair of unconnected points is prioritized for order for interconnect completion. be done. For example, this prioritization typically identifies points that are likely to be the most distant or most difficult, with no or minimal overlap between regions, to complete the connection first.

Because the system completes interconnects with minimal sacrifice to the circuit board, operators of auto-routing schemes provide front-side minimization of performance sacrifices to complete unconnected points and/or unconnected closed points through automatic routing. Automatic routing can be used to process the entire interconnection list of a circuit, or a significant portion thereof, regardless of whether automatic routing provides completion for some of the points or not.

These and other features of the invention will be explained in more detail below by way of example only and in the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides an overview of the area within a set of points to be interconnected on a printed circuit board by providing an operator with an indication of the area into which conductors from each point to be interconnected on the printed circuit board are to be applied. The system is intended to facilitate the completion of interconnections between points.

Referring to FIG. 1, a portion of a printed circuit board, generally designated 12, is shown having a plurality of terminals or contacts 14 disposed thereon. These terminals are typically connected to integrated circuits or other i! A wire connection represents an electrical connection to which a wire connection is connected. Each set of displayed terminals 14 corresponds to conductor pattern 1.
electrically interconnected by 6. printed circuit board 1
2 is generally a multilayer board: According to normal convention, the conductors on one layer run in one direction, east-west, or horizontally in Figure 1, while the conductors on the next layer run in the north-south direction, or vertically in Figure 1. It extends to Interconnections between each layer of a circuit board generally require a passageway, which is usually essential on a complex circuit board due to the required crossing of conductors to enable interconnections from one location to another on the board. given through.

FIG. 2 shows a printed circuit board 20 on a smaller scale than in FIG. 1, with two terminal points 22 and 24 to be interconnected. Processing according to the present invention provides a multilayer circuit board 2 to which conductor patterns from corresponding points 22 and 24 can extend when other known interconnections are present on the circuit board.
First and second regions 26 and 28 are formed representing positions above the . If the printed circuit board 20 is a multilayer board, a set of regions corresponding to, but differently located from, regions 26, 28 can be formed from various locations on each layer, and terminal points 2
Locations on different layers other than those including 2 and 24 are formed via passageways located between each layer and provided with connections to regions 26 and 28. Thus, the operator, given information corresponding to that shown in FIG.
An interconnect pattern between 4 and 4 can be formed.

For example, if regions 26 and 28 overlap in region 30, one passage between both layers in region 30 can be used to interconnect points 22 and 24. In other cases, the region 32 of possible conductor on another layer is the region 26
．． 28 respectively to complete the connection.

In still other cases, upon permissible violation of the protocol used by the operator to establish the conductor pattern, for example to break the connection existing between the points of approach 3 and 40 of areas 26 and 28, Adjust the conductor pattern.

The information generally displayed is a portion of what is represented by FIG. 2, such as one region in a layer at a time, or a representation of the conjunction of regions 26 and 28 represented by overlapping region 30. Other logical operations include the disjunction of regions @26 and 28, the indication of the point of closest approach between regions 26 and 28, and/or the
Instructions are included based on an interconnection protocol that allows jumper wiring between both the and 28 locations to be accomplished with minimal sacrifice of circuit board performance. Any number of pools can be used for data representing areas. The operator is then provided with the results of the calculation information, greatly reducing the operator effort required to complete the interconnection of both points. Other examples of region mapping are shown in Figures 5.6 and 7, where the same numbers in each of these figures indicate the same features.

FIG. 3 shows a computer-aided design terminal in accordance with the present invention, which generally has an operator key code 46 and a display screen 48, and includes internal graphics, a graphics processor, attached memory and software. For use with a computer-aided design terminal 44 such as that shown in FIG. The process of FIG. 3 includes the presence and location of terminals on the printed circuit board and dimensional data regarding these terminals, the connection requirements between each terminal that generally constitutes a list of points to be interconnected, and the connection requirements between points or terminals. A set of databases 5 configured according to the known rules of the printed circuit board to each identify a set of interconnection rules or protocols, including how the
0.52.54 is used. The protocol generally describes the size of the conductors on the circuit board, including their width or cross-sectional area, the required spacing between the conductors, the number of glabellar passages or interconnections on the circuit board allowed by the protocol, and the points or terminals allowed between them. Check the total length of the conductor. The protocol is comprehensive;
It may be applicable to all pairs of points, or each ′i! of points to be connected! may vary from i to i, and the protocols are generally established by the design engineer to accommodate the current density requirements and to minimize interference, capacitive, inductive, or radiated effects, all of which are well known in the art. Ru.

From the database described above, a bitmap 56 is first constructed having circuit board dimensions and terminal locations given by a setup routine 5, as is well known in the art. Commercially available "maze" or routing software, such as that available from Redac Corporation and used in the Visula terminal, then maps the interconnection requirements and protocols in databases 52 and 54 to a dot-by-dot map 56. The bit interconnection pattern determined is operated in step 60. The automatic connection routine of step 60 generally takes each set of points to be interconnected in some sequential order;
For one or the other of both points, form a trajectory of points to which the conductor is routed according to the protocol of the database 54 until this trajectory extends to include another point in the set to be connected. . The expanding trajectory is maintained as a temporary bitmap 62 in the memory of the terminal 44. Once the trajectory in the bitmap 62 has expanded to include two points in the set, a "maze method" step 60 establishes a specific conductor route through the trajectory in the temporary bitmap 62 based on the protocol. There is.

The process now determines whether automatic routing was able to complete the interconnection between the points in the set according to the steps described above, or whether it was unable to complete the connection after a predetermined number of attempts or after a predetermined length of time. Pass/fail passes through step 62 of determining. Generally, decision 62 is performed as soon as the trajectory expands to include a pixel or a predetermined time interval has elapsed. If the automatic route determination determines a trajectory large enough to include both points, the process proceeds to step 64.
, where the just completed conductor pattern from temporary bitmap (TBM) 62 is transferred to bitmap 56.
Add to. In the next step 68, the temporary bitmap 6
After clearing 2, proceed to step 68 to select the next set of points to interconnect and return to the "maze method" step 60 for operation on that set.

If the automatic routing scheme in step 60 fails to complete the connection, control passes from decision step 62 to step 70, which places the dotted line in a list or record of unconnected point pairs. 70 returns control to step 66 to clear the temporary bitmap 62 and continue processing as described above.

Alternatively, the data in temporary bitmap 62 may be placed in central storage file 72 at step 70 to speed up processing after unconnected threads.

Once all sets of interconnection requests in database 52 have been processed, the system generally moves from step 70 through various paths to operate on records for each set of established disconnect points. Preferably, the system processes the list through a prioritization step 74, which determines the order in which each set of disconnected points is processed. This priority scheme selects for initial processing the pairs that are likely to be the most difficult to interconnect, as determined by the least amount of overlap, the farthest point of closest approach, or other criteria. Once the priorities have been determined in step 74, a subsequent step 76 selects the first or next set in the priority list, and step 78 establishes a temporary bitmap formed from each point to be connected. In step 78, regions are determined, such as those shown as regions 26 and 28 in FIG. 2 for the two points 22 and 24, for example. A routing step 60 is operated for each point to be connected by step 78, determining a separate bitmap for each point. A next step 80 corresponds to the temporary bitmap determined in step 78. Provides the operator with a display of the indicators to be used.

Generally, the display of the temporary bitmap is operator-selectable and is accomplished through keyboard input by the operator in a selection step 82 and one or more logical combinations of the data in the temporary bitmap determined in step 78. Select a processing operation.

This logical processing includes processing the data in the temporary bitmap based on an arbitrary number of pools and displaying the results. Temporary bitmaps for regions relating to passageways to other layers in a multilayer circuit board, such as passageways 34 or 36 in FIG. 2, can be ordered by an operator.

The logic function can be selected to display overlapping regions such as region 30, the closest position between regions for each point in the temporal bitmap, or the disjunction (including exclusive disjunction) of the temporal bitmaps. .

From this information, conductors can be routed to the desired interconnect through certain allowed violations of the interconnection protocol with respect to the specific interconnect or other previously established interconnects that can achieve blocking to the desired interconnect. , the operator is provided with concise data indicating where potentially possible interconnections can be achieved between regions of the temporary bitmap. In step 84, the operator uses known commands to identify changes to the conductor pattern that acceptably sacrifice a portion of the interconnection requirements to provide interconnections between points in the unconnected set. Input is provided to computer aided design terminal 44. At step 86, the design implements the changes either directly or using a maze method or other available routing procedure. Eight days of subsequent testing will determine whether the changes complete the interconnect.

If interconnection is achieved, processing returns to step 64 to update the bitmap with the newly determined interconnection. If not, processing returns from step 88 to step 70 where the set of points is maintained in a list of unconnected points. Ultimately, the set of disconnected points must be processed entirely by manual intervention, but can be iterated through a series of steps starting at step 76 as many times as the operator sees fit. After each set of unconnected points is thus processed, the next connect step 68 branches to step 76 to select the next unconnected point in the list.

Alternatively or additionally, the set of specified protocol modification rules in database 90 may be automatically executed at step 86 to minimize operator interference.

A set of permissible changes is made to the set of points that could not be automatically connected by the "maze method" and an attempt is made to automatically connect the otherwise unconnectable set of points. Modifiers in the database 90 are formed interactively depending on the nature of the previously obtained interconnects and may be pre-built into the system or activated by the operator once the list of disconnected points has been established. You may.

As mentioned above, interoperating operator intervention is efficient and economically accomplished. It will be appreciated that the above description is intended to be exemplary only, and that other embodiments of process details may be used within the scope of the invention, which is limited only by the following claims.

[Brief explanation of drawings]

Figure 1 shows representative points on a printed circuit board and interconnection conductor patterns on multiple circuit board layers; FIG. 3 is a block diagram of a computer-aided design process using operator intervention to complete a connection in accordance with the present invention; and FIG. 1 is a schematic sketch diagram of a representative computer-aided design workstation on which the present invention operates; FIG. 12; 20-Printed circuit board, 14; 22. 24 piece,
16-conductor pattern, 18; 34.36 interlayer passage, 3
0-Logical operation area map, 44.82.84-Means for interacting with the operator (44; terminal), 50.52Means for checking each set of one point, 54-Protocol checking means, 56-Map maintenance means, 62- Temporary matsubu, 70 point-to-point conductor,
74-
Prioritization means, 78-Area confirmation means, 80-Means for providing indicators, 90-Protocol modification means. FIG.1

Claims (1)

[Claims] 1. In an apparatus for designing a conductor pattern of a printed circuit board: means for identifying a set of points on said circuit board between which a conductor extends; means for ascertaining a protocol for placing conductors; means for automatically routing conductors between a set of points; a set of points between which said routing means can provide conductors based on a protocol; means for maintaining a map of automatically verified conductor routing between the sets of points; means for identifying a set of points for which said automatic routing means was unsuccessful in providing a conductor between said sets of points; means for ascertaining the area in which a conductor can be provided from each point within the set of points for which the determining means was unsuccessful in providing a conductor between points; means for providing an operator-visible indicator representative of said area; means for providing interaction with an operator to confirm the conductor route between points within the set of points where the automatic routing means has not been successful in completing the conductor between the set of points; the point-to-point route confirmed by the operator; means for adding to said map. 2. The apparatus of claim 1, wherein said means for identifying a set of points to be interconnected includes means for identifying points on one or more layers of a printed circuit board. 3. The means for verifying a protocol includes means for verifying a protocol selected from the group consisting of conductor size, conductor spacing, conductor path, and point-to-point conductor length.
The device described. 4. The routing means includes means for ascertaining a region of conductor placement for a point in a set of points to be interconnected, and for performing said ascertainment until said region includes other points in said set;
2. The apparatus of claim 1, wherein: and said means for ascertaining a region for each point is operative to cause said routing means to form a region for each point within a set of points. 5. The apparatus of claim 4, wherein said region is provided as a temporary map of possible semiconductor devices. 6. The means for providing an indicator visible to the operator,
2. The apparatus of claim 1, further comprising means operative to provide logical operations on the determined area for each point in the set in response to said area. 7. The apparatus of claim 6, wherein said means for providing a logical operation includes means for displaying a temporal map of the area for a selected point within said set of points. 8. Claim 6, wherein said means for providing a logical operation includes means for providing a logical product of regions regarding a plurality of points within said set of points.
The device described. 9. The apparatus of claim 6, wherein said means for providing logical operations includes means for providing an indication of jumper wire locations between regions. 10. The apparatus of claim 6, wherein said means for providing a logical operation includes means for providing a logical OR operation for regions. 11. The apparatus of claim 1, wherein said means for providing operator interaction includes means for providing protocol changes. 12. The apparatus of claim 11, wherein said means for providing a protocol change includes means automatically operative to confirm the protocol change according to a predetermined scheme and to achieve interconnection between a set of points. 13. means for prioritizing sets of confirmed unsuccessful routing; and said means for identifying areas being operative to identify areas in a sequential order based on the priority of said confirmed sets; 2. The apparatus of claim 1, further comprising; 14. The apparatus of claim 6, wherein said means for providing a logical operation includes means for determining a point of closest approach for a region for each point in a set of points. 15. In an apparatus for designing interconnections for a printed circuit board: means for identifying a region of locations where a point-to-point conductor within a set of points can become a conductor of a printed circuit between the two points; logic regarding said identified region; means for providing an operation; based on an interconnection protocol and depending on the logical operation;
means for routing conductors between identified areas; 16. The logical operation is one or more selected from the group consisting of displaying only a positional area, displaying a logical product of areas, displaying a logical sum of areas, and displaying an index representing the point of closest approach between areas. 16. The apparatus of claim 15, comprising the operation of . 17. The apparatus of claim 15, wherein said protocol includes means for minimizing cost factors in interconnecting points. 18. The apparatus of claim 17, wherein the cost factors include costs associated with conductor size, spacing, passages, and length. 19. In a method of designing a conductor pattern for a printed circuit board: identifying a set of points on said circuit board between which a conductor extends; for placing a conductor between a set of points; a step of verifying a protocol; a step of automatically routing a conductor between a set of points; a step of automatically verifying between a set of points, said routing step being able to provide a conductor between the points based on a protocol; maintaining a map of routed conductors; identifying sets of points for which the automatic routing step was unsuccessful in providing a conductor between the points; identifying areas that can be provided with conductor from each point in the set of points that were unsuccessfully provided with conductor; providing an operator-visible indicator representing said area; providing an interaction with an operator identifying conductor routes between points in the set of points that have not been successful in completing a conductor between the points in the set; adding to the map the route between points identified by the operator; ; A method comprising; 20. The method of claim 19, wherein said step of identifying a set of points to be interconnected includes identifying points on one or more layers of a printed circuit board. 21. The step of confirming the protocol includes the conductor size,
20. The method of claim 19, including the step of verifying a protocol selected from the group consisting of conductor spacing, conductor path, and point-to-point conductor length. 22. said routing step comprises identifying a region of conductor placement for a point in a set of points to be interconnected, and performing said verification until said region includes other points in said set; and 20. The method of claim 19, wherein the step of identifying a region for a point is operative to cause the routing step to form a region for each point within a set of points. 23. The method of claim 22, wherein the region is provided as a temporary map of possible conductor arrangements. 24. The method of claim 19, wherein the step of providing an operator-visible indicator includes the step of being operative to provide a logical operation on the identified area for each point in the set in response to the area. 25. The method of claim 24, wherein the logical operation step includes the step of displaying a temporal map of the area for a selected point within the set of points. 26. The method of claim 24, wherein the logical operation step includes providing a logical product of regions for multiple points within the set of points. 27. The method of claim 24, wherein the logical operation step includes providing an indication of jumper wire locations between regions. 28. The method of claim 24, wherein the logical operation step includes providing a logical OR operation on regions. 29. The method of claim 19, wherein the step of providing operator interaction includes providing protocol changes. 30. said protocol modification step automatically operates to confirm the protocol modification according to a predetermined scheme;
Claim 29 comprising the step of achieving an interconnection between a set of points.
Method described. 31. prioritizing the sets of verified unsuccessful routing successes; and said step of verifying regions being operative to verify regions in a sequential order based on the priorities of said verified sets. 20. The method of claim 19, further comprising; 32. Claim 2, wherein the logical operation step includes the step of determining the point of closest approach for a region for each point in the set of points.
The method described in 4. 33. In a method of designing an interconnect for a printed circuit board: identifying a region of locations where a point-to-point conductor within a set of points can become a printed circuit conductor between the two points; logic regarding the identified region; providing an operation; based on the interconnection protocol and in response to the logical operation;
A method comprising: routing conductors between identified areas. 34. The logical operation is one or more selected from the group consisting of displaying only a positional area, displaying a logical product of areas, displaying a logical sum of areas, and displaying an index representing the point of closest approach between areas. 34. The method of claim 33, comprising the operation of . 35. The method of claim 33, wherein the protocol includes minimizing cost factors in interconnecting points. 36. The method of claim 35, wherein the cost factors include costs associated with conductor size, spacing, paths, and length. 37. The apparatus of claim 6, wherein the logical operation is a pool operation. 38. The apparatus of claim 15, wherein the logical operation is a pool operation. 39. The method of claim 24, wherein the logical operation is a pool operation. 40. The method of claim 33, wherein the logical operation is a pool operation.