JPS6329452B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information word error correction method suitable for application to a transmission system with many burst errors.

Conventionally, as an error correction method using an error correction code, as disclosed in Japanese Patent Application Laid-Open No. 1472925/1989, multiple bit errors are encoded into error correction codes in the row direction and column direction and arranged in a matrix. There is a known method that corrects bit errors in the row direction and then corrects the bit errors in the column direction.
However, in this case, since the number of bits for error correction in the row direction and the bits for error correction in the column direction are not the same, the error correction arithmetic circuits have completely different configurations. Furthermore, since correction coding is performed in the row and column directions, each error correction process cannot be performed until all the information bits in a matrix form are complete. Further, since correction in the row direction and correction in the column direction are performed independently, it is not possible to use each other's error detection results.

The present invention provides a novel error correction method that solves the above-mentioned problems. In particular, among the methods for decoding various correction codes used for error correction when receiving an information word encoded with error correction codes, The present invention provides a correction method that is extremely efficient and can perform corrections with high correction ability.

An embodiment of the present invention will be described below. FIG. 1 shows an encoder provided on the transmitting side. An input terminal 1 is supplied with an information bit sequence in which an analog signal such as an audio signal is sampled, and each sampling output corresponds to one word. The parallelization circuit 2 separates the odd-numbered words of the input information bit sequence from its even-numbered words. As shown in FIG. 2A, a first information bit sequence H1 consisting of odd-numbered words and a second information bit sequence _H2 consisting of even-numbered words are obtained at the output of the parallelization circuit ₂ . These bit series _H1 and _H2 are supplied to the adder circuit 3,
Parity bit from adder circuit 3 (even parity)
A first error correction bit sequence H ₃ (see FIG. 2B) is obtained. The adder circuit 3 and the adder circuits described below perform operations according to the all (mod. 2) addition method, and are specifically constructed of exclusive OR gates. A parity bit sequence _H3 is formed from two words shown at the same timing in FIG. 2A of each of the two bit sequences _H1 and _H2 transmitted in parallel. For example (P ₁ = A ₁ A ₂ )
It is. Also, bit series _H2 and _H3 are delay circuits.
Delayed by D ₁ and D ₂ by 2 and 4 words, respectively. A shift register or the like is used as the delay circuits _D1 and _D2 . Therefore delay circuits D ₁ and D ₂
The bit sequences shown in Figure 2 C and D, respectively, are outputted by
H ₄ and H ₅ appear. These bit series H ₁ ,
A second error correction bit sequence H6 consisting of parity bits (even parity) shown in FIG. 2E from three words _{of H4} and _H5 shown at the same timing.
is formed by the adder circuit 4. For example (Q ₁
= A ₁ A _-2 P _-7 ). 4 bit series
H ₁ , H ₄ , H ₅ , H ₆ are added to the serialization circuit 5.
These bit sequences form a matrix code structure of four rows and a plurality of columns, and each column of this code structure is sequentially serialized and taken out to the output terminal 6.
For example, A ₁ , A _-2 , P _-7 , Q ₁ , A ₃ ,
Serial data in the order A ₀ , P _-5 , Q ₃ ... is generated.
This serial data is modulated and amplified as necessary and transmitted.

FIG. 3 shows a decoder provided on the receiving side. The received serial data demodulated and amplified as necessary is added to the input terminal indicated by 7 in FIG. ₃ , and the received serial data is transmitted in parallel by the parallelization circuit 8. _H4 ,
Converted to H ₅ and H ₆ . Bit sequences H ₁ and H ₄ are processed by delay circuits D ₃ and D ₄ respectively into 4 words and 2 words.
word delayed. Let the bit sequences appearing at the outputs of delay circuits D ₃ and D ₄ be H ₁ ' and H ₂ ', respectively. That is, in the decoder, four bit sequences H ₁ having the same time relationship as in the encoder,
We get H ₄ , H ₅ , H ₆ and then three bit sequences, also in the same time relationship as in the encoder.
We obtained H ₁ ′, H ₂ ′, and H ₅ . In order to restore the original time relationship, a data synchronization signal is added to, for example, every four words of the serial data that is transmitted.

Each word of the bit series H ₁ , H ₄ , H ₅ , H ₆ is supplied to the adder circuit 9, and the bit series H ₁ ′, H ₂ ′,
Each word of H ₅ is supplied to adder circuit 10 .
Addition circuits 9 and 10 are for forming a syndrome. Since the present invention uses convolutional codes, the outputs of adder circuits 9 and 10 are provided with four 1-word delay circuits _D5 to _D8 and _D15 to
D ₁₈ is provided in series so that the previous syndrome is also supplied to the correction logic circuit 11. Furthermore, the bit sequences H ₁ ′ and H ₂ ′ are sent to correcting adder circuits a 1 and 1 through 1-word delay circuits D ₉ and D ₁₀ , _respectively .
a ₂ and the outputs of adder circuits a ₁ and a ₂ are supplied to 2- _word delay circuits D ₁₁ and D ₁₂ ,
The output of is added to the correction adder circuit _a3 . The outputs of delay circuit D ₁₁ and adder circuit a ₃ are connected to serialization circuit 12.
Error-corrected serial data is obtained at its output terminal 13. Note that the delay circuit D ₉ ,
D ₁₀ is to secure the time necessary for the logic operation of the correction logic circuit 11, and the delay circuits D ₁₁ and D ₁₂ are
This is to correct an error two words earlier and to maintain data synchronization. Although not shown, an analog signal can be obtained by PCM demodulating this serial data.

The error correction operation of the decoder will be explained. If the error word included in one received word is indicated as e, and a suffix of the word number is attached to e to indicate the correspondence with each word of the information bit series and the parity bit series, then the adder circuit 9
A part of the syndrome formed by is shown by the following formula.

y ₁ = e ₁ e _-2 e _p-7 e _q1 y ₃ = e ₃ e ₀ e _p-5 e _q3 y ₅ = e ₅ e ₂ e _p-3 e _q5 y ₇ = e ₇ e ₄ e _{p- 1} e _q7 y ₉ =e ₉ e ₆ e _p1 e _q9 A part of the syndrome formed by the adder circuit 10 is expressed by the following formula.

x _-7 = e _-7 e _-6 e _p-7 x _-5 = e _-5 e _-4 e _p-5 x _-3 = e _-3 e _-2 e _p-3 x _-1 = e _-1 e ₀ e _p-1 x ₁ = e ₁ e ₂ e _p1 In these syndromes, all bits will be "0" if there is no error. (e _i +e _j = 0) (however,
The probability _of occurrence of the ^case where _e The probability that _i , e _j ) will be the same by chance becomes negligibly small. Further, the timing at which the syndrome occurs from the adder circuits 9 and 10 is as shown in FIG. 2F and G in relation to the information bit series.

The correction logic operation of correction logic circuit 11 is shown in the flowchart of FIG. In Fig. 4, the circle side of the judgment block means affirmation, the side without circle means negation, and Zc is
This means a clearing operation that sets all bits of the syndrome held in the corresponding delay circuit to "0". Furthermore, the interrelationship of the syndromes is shown in FIG. Each error word in the horizontal direction in FIG. 5 forms a syndrome from adder circuit 9, and each error word in the vertical direction in FIG. 5 forms a syndrome from adder circuit 10.

Syndrome (y ₁ , y ₅ , y ₉ ) as mentioned above
At the timing when (x _-7 , x _-3 , x ₁ ) is given to the correction logic circuit 11, the information bit series A ₁ , A ₂ ,
It is possible to correct the error words e ₁ , e ₂ , and e _-2 contained in A _-2 , and these errors can be corrected by adding a predetermined syndrome to the adder circuits a ₁ , a ₂ , and a ₃ . will be done.

For simplicity, a part of the flowchart (FIG. 4) will be explained with reference to FIG. 5. First (x ₁ =
0), it means that there are no errors regarding A ₁ , A ₂ , and P ₁ , so proceed to the next step. (x ₁
≠ 0) and (y ₁ = 0), at least one of e ₂ and e _p1 exists, and to determine this, it is necessary to determine whether (x ₁ = y ₅ ) holds or not. It can be investigated.
If (x ₁ = y ₅ ), it means that an error word e ₂ regarding A ₂ exists, and the received data is (A ₂ +
e ₂ ). Therefore, since (x ₁ = e ₂ ), in adder circuit a ₂ (A ₂ + e ₂ + x ₁ )
The correct word A ₂ can be obtained by the operation . Then, when the delay circuits D ₁₅ and D ₇ are cleared and the process moves to the next step, (x ₁ = y ₅ = 0)
It shall be done as it is said. This is to prevent wasteful performing the correction operation again even though the error word _e2 has been corrected as described above, and to prevent a correction error from occurring at that time. The need to clear
The same applies to other cases.

If (x ₁ ≠y ₅ ), it is determined whether (x ₁ =y ₉ ). If (x ₁ = y ₉ ), then the error word e _p1 regarding P ₁ exists. _D5
is cleared and proceed to the next step. (x ₁ ≠ y ₉ )
But let's move on to the next step.

Furthermore, when (y ₁ ≠ 0) and (x ₁ = y ₁ ) hold, it means that there is an error word e ₁ related to A ₁ , so in the adder circuit a ₁ , (A ₁ + e ₁ ) +
The error can be corrected by calculating x ₁ , and in the next step the delay circuit D ₁₅ is cleared to set (x ₁ =0).

Also, (x ₁ , y ₁ ≠ 0), (x ₁ ≠ y ₁ ), and (y ₁ = x ₁ +
x _-3 ) holds, then the error words e ₁ and e _-2 regarding A ₁ and A _-2 exist. Therefore, syndrome x ₁ for adder circuits a ₁ and a ₃ respectively
and x _-3 are supplied to correct the error. In this case, delay circuits D ₁₅ and D ₁₇ are cleared so that (x ₁ , x _-3 =0) in the next step. Hereinafter, the correction logic circuit 11 performs a correction logic operation according to the flowchart.

FIG. 6 shows an embodiment in which the above-described invention is applied to a PCM signal recording and reproducing apparatus using a VTR. Reference numeral 14 indicates a helical scan type VTR, and a PCM signal H having a signal format similar to that of a television signal is supplied to the video input terminal 15i of the VTR.
The video data is recorded on a magnetic tape through a recording system 14, and the reproduction output of this magnetic tape appears at a video output terminal 15o through the reproduction system.

16L and 16R indicate terminals to which a left channel signal and a right channel signal of the stereo audio signal are supplied, respectively, and 17L and 17R are low-pass filters. The left and right channel signals are sampled by sampling and holding circuits 18L and 18R, encoded by AD converters 19L and 19R, and their outputs are supplied to encoder 20, which will be described later. The encoder 20 performs processing such as adding parity bits and compressing the time axis, and outputs it as a serial code to the synchronous mixing circuit 21.
added to. 22 indicates a basic clock oscillator, from which sampling pulses,
A clock pulse for AD conversion, a composite synchronization signal, a control signal for the encoder 20, etc. are generated by the pulse generation circuit 23, and the output of the synchronization mixing circuit 21 is supplied to the video input terminal 15i of the VTR 14.

The PCM signal reproduced by the VTR 14 and taken out to the video output terminal 15o is supplied to the synchronization separation circuit 24. The composite synchronization signal separated by the synchronization separation circuit 24 is supplied to the pulse generation circuit 25, and the PCM
The signal is supplied to a decoder 26, which will be described later. The decoder 26 performs processing such as time axis expansion, error detection, and error correction, and the DA converters 27L and 27
R, and its analog output is guided to output terminals 29L and 29R via low-pass filters 28L and 28R. A control signal for the decoder 26, clock pulses for the DA converters 27L and 27R, timing pulses for synchronization separation, etc. are generated by the pulse generating circuit 25. The time base in this case is the reproduced composite synchronization signal.

The encoder 20 has a configuration shown in FIG. From AD converter 19L, 19R to terminal 30
PCM signal S _L regarding the left channel to L, 30R
and a PCM signal S _R for the right channel are supplied and applied to one word delay circuits D _19L and D _19R , respectively. The output of this 1-word delay circuit is further transmitted to the switch circuit 31 via 1-word delay circuits D _20L and D _20R .
It is added to the input terminals of L and 31R. The switch circuits 31L and 31R are synchronized with each other, and their input terminals and output terminals are sequentially connected every word time. Further, a total of six words, including one word of the PCM signals S _L and S _R , one word one word before each husband, and one word two words before each of them, are added to the adder circuit 23.

Further, the bit series H ₁₁ appearing at the output terminal of one switch circuit 31L is supplied to the serialization circuit 33, and the bit series H ₁₃ appearing at the other output terminal,
H ₁₅ is connected to the serialization circuit 33 via delay circuits D ₂₂ and D ₂₄
supplied to The bit series H ₁₂ , H ₁₄ , H ₁₆ appearing at each output terminal of the other switch circuit 31R is supplied to the serialization circuit 33 via delay circuits D ₂₁ , D ₂₃ , D ₂₅ . Furthermore, the bit series _H17 formed by the adder circuit 32 is sent to the serialization circuit 3 via the delay circuit _D26 .
3. If the delay amount of delay circuit D ₂₁ is d word, delay circuits D ₂₂ , D ₂₃ , D ₂₄ , D ₂₅ , D ₂₆
The delay amounts are selected to be 2d, 3d, 4d, 5d, and 6d (words), respectively, and in this example, (d=16 words). In other words, the delay amount of each delay circuit is
16, 32, 48, 64, 80, 96 (words). At the same time, the seven bit sequences _H11 and _H18 to _H23 are supplied to the adder circuit 34 to form a bit sequence _H24 consisting of the parity bit sequence Q.
_H24 is also supplied to the serialization circuit 33. One word is extracted from each of a total of eight bit sequences supplied to the serialization circuit 33, and serial data is obtained at the output terminal 35. This serial data is applied to a time-base compression circuit (not shown) in the encoder 20, and the time-base compression circuit forms data missing periods corresponding to the horizontal blanking period and the vertical blanking period.

The operation of the encoder 20 described above will be explained with reference to FIGS. 8 and 9. In the adder circuit 32, a bit series _H17 is made up of parasitic bits from six words of the PCM signals S _L and S _R , the word one word before each word, and the word two words before each one.
is formed. For example (L ₁ R ₁ L ₂ R ₂ L ₃
A one-word parity bit sequence _P1 is formed by the operation of _R3 ). Six bit sequences appearing from each output terminal of switch circuits 31L and 31R
H ₁₁ to _{H 16} and the above-mentioned bit series H ₁₇ are shown in FIG. Of the bit series H ₁₁ to _{H 17} , bit series H ₁₂ to H ₁₇ excluding bit series H ₁₁ are delay circuits.
Bit sequences H ₁₈ to _{H 23} are obtained by delaying by D ₂₁ to D ₂₆ , respectively. One word from each of the seven bit sequences formed by the bit sequences _H18 to _H23 and the undelayed bit sequence _H11 is supplied to an adder circuit 34 to form a bit sequence _H24 . For example (L ₁ R _-47 L _-94 R _-142
A one-word parity bit sequence _Q1 is formed by the calculation of L _-189 R _-237 P _-287 .

In the serialization circuit 33, eight words occupying the same position in FIG. 8 are serialized. Figure 9 shows 1H of the signal supplied to the VTR 14 with a synchronization signal added (1H is 1H defined by the horizontal synchronization signal HD).
period (indicating a plateau) is shown. If the word length is 16 bits, (8 x 16 = 128 bits) will be inserted into 1H.

The decoder 26 is also provided with a time axis expansion circuit (not shown), and the serial data from which data missing periods have been removed is supplied to the parallelization circuit 38 from an input terminal 37 shown in FIG. The parallelization circuit 38 separates the eight bit series _H11 and _H18 to _H24 in the time relationship shown in FIG. 8, and one word of each bit series is supplied to the addition circuit 39.
A syndrome is formed by the adder circuit 39. At the same time, the seven bit sequences H ₁₁ having the time relationship _shown in FIG _{. .about.H17} and one word of each bit sequence is supplied to the adder circuit 40 to form a syndrome. Furthermore, the bit series H ₁₁ to _{H 16} consisting of the information bit series are supplied to the correction adder circuit group d ₁₁ via the one-word delay circuit D ₃₃ . below,
16-word delay circuits D ₃₄ , D ₃₅ , D ₃₆ , D ₃₇ , D ₃₈ and correction adder circuit groups a ₁₂ , a ₁₃ , a ₁₄ , a ₁₅ , a ₁₆ are sequentially provided. The corrected information bit series is supplied to the switch circuit 42 and converted into PCM signals of the left and right channels, and the output terminals 43L, 4
They appear in each of the 3Rs.

Six 1-word delay circuits and six 15-word delay circuits are arranged in series at the outputs of the adder circuits 39 and 40, respectively, so as to be arranged alternately. The syndrome is extracted from and added to the correction logic circuit 41.

The other embodiments of the present invention described above are also concept extensions of the one embodiment described above. Although details of the error correction operation of the decoder will be omitted, when the syndromes y ₂₈₉ and x ₁ are generated from the adder circuits 39 and 40, respectively, the syndromes y 241 and y ₂₄₁ are generated as shown in FIG.
y ₁₉₃ , y ₁₄₅ , y ₉₇ , y ₄₉ , y ₁ ) and (x _-47 , x _-95 ,
x _-143 , x _-191 , x _-239 , x _-287 ) appear and are added to the correction logic circuit 41.

According to the present invention described above, it is possible to realize an information word error correction method that is effective for correcting burst errors. In addition to the convolutional code, instead of the bit sequence consisting of the parity bit sequence Q, an error detection code such as a CRC code (Cyclic
A code configuration using a cyclic redundancy check code (Redundancy Check Code) may also be considered. However, the present invention can provide higher correction capability than those using such a code structure. In order to explain the comparison of correction capabilities, FIG. 11 shows a graph in which the vertical axis represents the number of corrections and omissions (per hour) and the horizontal axis represents the bit correlation coefficient. The bit correlation coefficient is (0, 999)
The closer it gets to , the more bursty the error becomes;
900), this becomes more random. The characteristic shown by the solid line in FIG. 11 shows the case where a CRC code is used in place of the parity bit sequence Q. According to the present invention, as shown by the broken line, it is possible to further reduce the number of corrections and missed corrections, and it is also possible to make the system resistant to random errors.

Furthermore, in the present invention, each error correction word is generated by an operation using each information word composed of a plurality of bits as a unit, and during correction decoding, the word combination of each error correction word and each information word is generated. Since error detection and correction is performed on a word-by-word basis using calculations in units of , once the position of a word containing an erroneous bit is known, multiple erroneous bits can be corrected in a word-by-word manner. This has the effect that if it is a bit within the word, it can be corrected without having to invent the position of each error bit, and even if multiple bit errors occur in a burst, they are included in each word of the correctable number of words. If it is a bit, it can be corrected. Therefore,
According to the present invention, errors in all bits included in at least one word can be corrected. Furthermore, in the present invention, a plurality of first information word blocks configured to straddle a plurality of information word series, and blocks different from each other among the plurality of first information word blocks that are configured to straddle a plurality of information word series. Since error correction decoding is performed using the first error correction word and the second error correction word generated from the information word with the block configured as above, error correction words are generated in the row direction and column direction of the matrix, respectively. In error correction decoding using so-called product codes, it is necessary to wait until the data in all rows and columns of the matrix are complete and each correction decoding block is completed before generating a syndrome in the error correction decoding process. There is no waiting time for calculations, and since the first and second syndromes can be generated sequentially using the first and second correction words if the data spanning each information word series of each information word block is complete, there is no waiting time for calculation. It is particularly effective for data processing that requires real-time processing, such as audio signals.

The test result (syndrome) using the first error correction word can be used for the test using the second error correction word (or the test result using the second error correction word can be used for the test using the first error correction word). ), etc., to maximize the efficiency of correction codes. That is, for example, a block containing an error word can be detected by the syndrome obtained by the test using the first error correction word, and as a result, there is a possibility that there is an error in the test using the second error correction word. Since it is possible to identify the word with the second error correction word, compared to the conventional method of correcting with the first error correction word and then making correction with the second error correction word without using the detection result, Inspection using correction words can be performed efficiently. In addition, in the present invention, since the first and second syndromes are obtained by word-by-word calculations of each information word and the first and second error correction words, each of which is composed of the same number of bits, the calculation method and circuit can be changed. This has advantages in simplifying the circuit configuration, such as being able to handle data with the same number of bits, and in some cases, allowing some parts to be shared.

Note that in the above-mentioned embodiment, the parity bit series Q is added to every 3 words, and in the other embodiments, to every 7 words, but it is also possible to add the parity bit series Q to every arbitrary word other than these numerical values. good.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an encoder according to an embodiment of the present invention, FIG. 2 is a schematic diagram used for explanation thereof, FIG. 3 is a block diagram of a decoder according to an embodiment of the present invention, and FIGS. The figure is a flowchart and a schematic diagram used to explain the operation, and Figure 6 is a
A general block diagram of another embodiment in which the present invention is applied to a PCM recording and reproducing apparatus using a VTR, FIG. 7 is a block diagram of its encoder, and FIGS. 8 and 9 are schematic diagrams used to explain the encoder. , FIG. 10 is a block diagram of a decoder in another embodiment of the present invention, and FIG. 11 is a schematic diagram used to explain the present invention. 1 is the input terminal, 3, 4, 9, 10, 32, 3
4, 39, 40, a ₁ to _{a 16} are adder circuits, 11, 4
1 is a correction logic circuit, _D1 to _D12 , _D15 to _D18 , _D19L ,
D _19R , D _20L , D _20R , and D ₂₁ to _{D 38} are delay circuits, respectively.

Claims (1)

[Claims] 1. A digital signal consisting of a plurality of information words each consisting of a first predetermined number of bits is divided into a second predetermined number of information words to form a second predetermined number of information word sequences. a plurality of first information word blocks each including the second predetermined number of plurality of information words spanning the second predetermined number of plurality of information word sequences; Each first error correction word consisting of the first predetermined number of bits is generated from a plurality of words included in one information word block by a word-by-word operation, and each first error correction word is made up of the second predetermined number of bits. The plurality of second information word blocks are configured to include the second predetermined number of information words selected from mutually different blocks of the plurality of first information word blocks across the plurality of information word series. , each second error correction word consisting of the first predetermined number of bits is generated from the plurality of words included in each of the second information word blocks by a word-by-word operation, and the plurality of second error correction words are transmitted. An information word, a plurality of first error correction words, and a plurality of second error correction words are received, and the plurality of second error correction words and the plurality of words included in the plurality of second information word blocks are combined with each other. A first syndrome is obtained by using the plurality of first error correction words and a plurality of words included in the plurality of first information word blocks, and a test using these plurality of syndromes is performed. A method for correcting errors in information words, characterized in that errors in each word are detected and corrected by performing logical operations on the results.