JPS6116628A - Error correcting method of information word - Google Patents

Abstract

PURPOSE:To correct a burst error effectively by correcting words of the 2nd block with the 2nd error correcting word, constituting the 1st block of the words of the 2nd block, and correcting the 1st block with the 1st error correcting word. CONSTITUTION:Syndromes y1, y3, y5, y7, and y9 are generated by the adding circuit 9 of a decoder and syndromes x-7, x-5, x-3, x-1, and x1 are generated by the adding circuit 10. All bits of those syndromes are all ''0'' unless an error occurs. A correcting logical circuit 11 makes errors. For example, if x1not equal to 0 and y1=0, either of e2 and ep1 is present and when x1=y5, an error word e2 relating to A2 is present, thereby showing that received data is A2+e2. Therefore, x1=e2, so an adding circuit a2 calculates A2+e2+x1 to obtain a correct word A2. Then, delay crcuits D15 and D7 are cleared and when an advance to the next step is made, x1=y5=0. When x1not equal to y5 and x1=9, an error word ep1 relating P1 is present.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information word error correction method suitable for application to a transmission system with many burst errors.

An embodiment of the present invention will be explained below. FIG. 1 shows an encoder provided on the transmitting side. An input terminal (1) K is supplied with an information bit sequence in which an analog signal such as an audio signal is sampled, and each sampling output is one word. Parallelization circuit (2
) separates the odd-numbered words of the input information bit sequence from its even-numbered words. Parallelization circuit (2
), a first information bit sequence H1 consisting of odd-numbered words and a second information bit sequence H2 consisting of even-numbered words are obtained as shown in FIG. 2A. These pit sequences H1 and H2 are supplied to an adder (3) K, and a first error correction bit sequence Ha (see Fig. 2B) consisting of tip pits (even parity) is obtained from the adder (3). It will be done. The adder circuit (3) and the adder circuits described below perform calculations according to the all (mod, 2) addition method, and are specifically configured using an exclusive-or-dirt method. Two bit sequences H1 and H2 transmitted in parallel
A parity pit series H3 is formed from two words shown at the same timing in each of FIG. 2A. for example(
P1=A1(9A2). Also, bit series H2
and H3 are delayed by 2 words and 4 words by delay circuits D1 and D2, respectively. Shift registers or the like are used as delay circuits D1 and D2. Therefore, delay circuit D1
Bit sequences H4 and H5 shown in second rgJC and D appear at the outputs of D2 and D2, respectively. These bit sequences H1m
A second error correction bit sequence H6 consisting of 3 words of H4 and H5 shown at the same timing to 9 parity pits (even number) shown in FIG. =A1(E
IA-2ΦP-7). 4 bit sequences H1e
H4e85*H6 is added to the serialization circuit (5). These bit sequences form a matrix code structure of four rows and a plurality of columns, and each column of this code structure is sequentially serialized and output from an output terminal (6) K. For example, the output terminal (
6) A1・A-2p P-7e Ql # A31
Serial data in the order AO*P-5+Q3...- is generated. This serial data is modulated and amplified as necessary and then transmitted.

FIG. 3 shows a decoder provided on the receiving side.

In FIG. 3, demodulated and amplified received serial data is added to the input terminal indicated by (7) as necessary, and the received serial data is transmitted in parallel by a parallelization circuit (8).
bit sequence H1+H4+H5.

Converted to H6. Bit sequences H1 and H4 are delayed by four words and two words by delay circuits D3 and D4, respectively. The bit sequences appearing at the outputs of delay circuits D3 and D4 are H1/ and H!, respectively. shall be. That is, the decoder obtains four bit sequences H1p H4+ H5#H6 in the same time relationship as in the encoder, and then three bit sequences H1a in the same time relationship as in the syndrome. H2e H5 is obtained. In order to restore the original time relationship, a data synchronization signal is added to, for example, every four words of the serial data that is transmitted.

Each word of the bit series H1* H4* H5e H6 is supplied to the adder circuit (9), and the bit series H1',
H2'.

One word of H5 is supplied to adder circuit QIK. Addition circuits (9) and a[ are for forming a syndrome. Since the present invention uses a convolutional code, four 1's are used for the output of the adder circuit (9) and α
Word delay circuits D5-D8 and D15-I) are provided in series to correct the previous syndrome.

The power is supplied to the logic circuit aυ. Further, the bit sequences H1/ and H2' are transmitted through l-word delay circuits D9 and D, respectively.
The outputs of the adder circuits a1 and a2 are added to the correction adder circuits a1 and a2 via the 2-word delay circuit Dl.
1 and D12, and the output of the delay circuit D12 is added to the addition circuit a3 for correction. The outputs of the delay circuit Dll and the adder circuit a3 are supplied to the serialization circuit α2, and error-corrected serial data is obtained at its output terminal α3.

Note that the delay circuit D9 y Dlo is a correction logic circuit aυ
In order to secure the time necessary for the logic operation, the delay circuits D11 + D12 are rounded circuits that correct the error of two words before and maintain data synchronization. Although not shown, an analog signal can be obtained by PCM demodulating this serial data.

The error correction operation of the decoder will be explained. If the error code included in one received word is indicated as e, and a word number suffix is attached to e to indicate the correspondence with each word of the information pit series and parity bit series, then the adder circuit (9 ), some of the syndromes formed are as shown in the following formula.

)'1 ”611■a-2Φep~7 e6q I?
a = ea @eo eep-s■19q3y5
= e5Φ626El ep-a eq5)'7
” '37 ee4Φep-teeQ779 = e9
eefi '(() 6p1 (El eqg) Also, part of the syndrome formed by the addition circuit α is as shown in the following equation.

x-r = f3-7ee-sΦeP-7X-5= 8-
5e e, -4Φep-5X-s =9-aΦe-2■
e p -3x-1=e-1eeoΦep-1 xl = 61 G1362 ``eP''In these syndromes, all bits will be 0'' unless there is an error.(6i +ej=0) (However, ei+o, 8j+
The probability that o) will occur is 2-n when the word length is n (bits), and if the word length n is made long enough, the two error codes (ei + ej) will coincidentally be the same. The probability becomes negligible. Further, the timing at which the syndrome occurs from the adder circuit (9) and <11 is as shown in FIG. 2 F and G in relation to the information bit series.

Correction logic circuit (111 correction, logic operation is 70 in Figure 4)
- Shown on the chart. In FIG. 4, the O part side of the judgment block means affirmation, the side without a circle means negation, and Zc means that all bits of the syndrome held in the corresponding delay circuit are @0 It means the clearing operation to ``.
- The interrelationships between the two systems are shown. Each error code in the horizontal direction in FIG. 5 forms a syndrome from the adder circuit (9), and each error code in the vertical direction in the same figure forms a syndrome from the adder circuit (11).

As mentioned above, the syndrome (71t F5 * 19
) (X-7e X-s #XI) is the correction logic circuit (
11), the information bit sequence A
l * A2 e 01 * e contained in A-2 respectively
21 (3-2 error word) Any correction is possible, but these errors are corrected by adding a predetermined syndrome to the adder circuit "1ea2pa3.

For simplicity, a part of the flowchart (FIG. 4) will be explained with reference to FIG. 5. First, if (X1=O),
Since there is no error regarding A1eA2*Pl, proceed to the next step. (X1'=0) and (yl=0
), then at least one of 62 and apt exists, and to determine this, it is checked whether ("t=y5) holds.◎If ("1=y,) Ba,
This means that the error word e2 regarding A2 exists, and the received data is (A2+6g).

Therefore, since (X1=02), the correct word person 2 can be obtained by calculating (Az+?z+xl) in the adder circuit a2. Then, the delay circuit D15 e
When D7 is cleared and you move on to the next step, (
The trap is set so that X1=75=0). This is to prevent the error word e2 from being redundantly corrected even though it has been corrected as described above, or from causing a correction error at that time. The necessity of clearing is the same in other cases as well.

If (xi'=ys), it is determined whether (x1=)'s). If (X1wY*), then Pl
The error word epx exists.

D5 is cleared and the process advances to the next step. (Xl'=y
s) but proceed to the next step.

Further, when (yx'=0) and (Xx=Yt) hold, it means that there is an error word e1 regarding A1, so in the adder circuit a1, (AI + el) +
The error can be corrected by calculating xl, and in the next step, the delay circuit ois is cleared to set (X1=0).

Also (XI # Y1'<O) (Xx'i)'x)
When (yx=Xx+x-3) holds true, it means that error words θ1 and number 2 regarding A1 and A-2 exist. Therefore, syndromes x1 and x3 are supplied to adder circuits a1 and J13, respectively, and errors are corrected. In this case, the delay circuit D15*I)zy is cleared so that (X1pXs=O) in the next step. Hereinafter, the correction logic circuit aυ performs a correction logic operation according to the flowchart.

FIG. 6 shows an embodiment in which the above-described invention is applied to a PCM signal recording and reproducing apparatus using a VTR.

G4 indicates a vertical scan type VTR, and a PCM signal having a signal format similar to that of a television signal is supplied to its input terminal (15i), and is recorded on a magnetic tape via the recording system of the VTR (141). The reproduction output of this magnetic tape appears at the video output terminal <15o) via the reproduction system.

(16L) and (16R) indicate terminals to which the left channel signal and right channel signal of the stereo audio signal are supplied, respectively, and (17L) and (17R) are low-noise filters. The signals of the left and right channels are sampled by sampling and holding circuits (18L) and (18R), and then sent to AD converters (19L) and (19).
R) is encoded by K, and its output is supplied to an encoder (a) to be described later. Processing such as addition of property pits and time axis compression is performed by the encoder ■ and added to the synchronous mixing circuit (211) as a serial code. clock pulses for conversion,
A composite synchronization signal, a control signal for the encoder C11, etc. are formed in the nocellus generation circuit (c), and the output of the synchronization mixing circuit Qυ is determined by the VTR (14) O video input terminal (154).
).

The video output terminal (150) is played back by the VTR (14).
) The output PCM signal is supplied to the synchronous separation circuit @. The composite synchronization signal separated by the synchronization separation circuit■ is
The PCM signal is supplied to the note coder (a) K, which will be described later. Processing such as time axis expansion, error detection, and error correction is performed by the decoder 2, and the DA
The analog output is supplied to the converters (27L) and (27R), and the analog output is supplied to the Ronos filter (28L) and (28
R) to the output terminals (29L) and (29R). Control signal for decoder (1), DA converter (
27L), (27R) clock pulse for K,
Timing pulses, etc. for synchronous separation are generated by the pulse generation circuit (
formed by c). The time pace in this case is the reproduced composite synchronization signal.

The encoder blade has the configuration shown in FIG. A.D.
Converter (19L), (19R) Color terminal (30L)
), (30R) are supplied with a PCM signal sL for the left channel and a PCM signal sR for the right channel, and are applied to the 1-word delay circuits D19L a D19H, respectively. The output of this 1-word delay circuit is further applied to the input terminals of switch circuits (31L) and (31R) via 1-word delay circuits D20L #D20B. The switch circuits (31L) and (31R) are configured to be synchronized with each other so that the input terminal and the output terminal thereof are sequentially connected every one power time. Further, a total of six words, including one word of the PCM signals sL and sR, one word one word before each husband, and one word two words before each of them, are added to the adder circuit 6a.

Further, the bit series H1l appearing at the output terminal of one switch circuit (31L) is supplied to the serialization circuit (to) K, and the bit series H13e HI3 appearing at the other output terminal is sent to the serialization circuit via the delay circuit D22 * D24. (to) will be supplied. The bit series H12e HI3 g ) (ia) appearing at each output terminal of the other switch circuit (31R) is supplied to the serialization circuit (to) via the delay circuit D21 e D23 #I gs. Further, the bit sequence H17 formed by the adder circuit G3 is supplied to the serialization circuit (to) via the delay circuit D26. If the delay amount of delay circuit D21 is d word, delay circuit D22 wins D28 # D
24 U D25 e D26 delay amount is 2d, 3d, respectively.
4d, 5d, 6d (words) K are selected, and in this example, (d=16 words). That is, the delay amount of each delay circuit is 16°32,48,
64, 80, 96 (words). At the same time, the seven bit sequences H1l and H18 to H23 are supplied to the adder circuit (to) K to form a bit sequence H24 consisting of the serialization circuit (to), and this bit sequence H24 is also supplied to the serialization circuit (to). be done. One word is extracted from each of a total of eight bit sequences supplied to the serialization circuit (to), and serial data is obtained at the output terminal (to). This serial data is applied to a time-base compression circuit (not shown) in the encoder (2), and the time-base compression circuit forms data missing periods corresponding to the horizontal blanking period and the vertical blanking period.

The operation of the encoder (2) described above will be explained with reference to FIGS. 8 and 9. PCM signal S in adder circuit 6
A bit sequence H17 consisting of parity pits is formed from six words: the L and SR words, the word one word before each, and the word two words before each. For example (Lte
1 by the operation of RxeL2eR2eL3 (EIRa)
A parity pit series P1 of words is formed. Six bit sequences H1l to H16 appearing from each output terminal of the switch circuits (31L) and (31R) and the above-mentioned bit sequence H
17 is shown in FIG. and bit sequence H
H12~ excluding bit sequence H11 from 1l~H17
By delaying H17 by delay circuits D21 to D26, bit sequences (is to H23) are obtained. From the seven bit sequences formed by these bit sequences H18 to H23 and the undelayed bit sequence H1l. One word at a time is supplied to the adder circuit diagram to form a bit sequence H24. For example, (LlΦR-4reL-e< eR
-t<gΦL-189R-2a7eP-2s7), a one-word sledge tipit series Q1 is formed.

In the serialization circuit (to), eight words occupying the same position in FIG. 8 are serialized. In FIG. 9, a synchronizing signal is added and the IH (of the signal supplied to the VTR (44)
IH indicates one horizontal period defined by the horizontal synchronization signal HD). If the word length is 16 bits, then (8× 16 =128 bits) will be inserted into the IH.

In addition, the decoder (to) is provided with a time axis expansion circuit (not shown), and the serial data from which data missing periods have been removed is supplied to the parallelization circuit (to) from the input terminal Gη shown in FIG. Ru. The parallelization circuit (to) converts the 8 bit sequences in the time relationship shown in FIG. 8) lit and H18 to H
One word of this bit sequence is supplied to an adder circuit K, and a syndrome is formed by the adder circuit OIK. At the same time, it is converted into seven bit sequences H1l to H17 having the time relationship shown in FIG. 8 through delay circuits D27 to D31 whose delay amounts cancel out the difference in delay amount between pit sequences in the encoder. , a syndrome is formed by the fact that each word of this bit sequence is supplied to the adder circuit (2).

Furthermore, it consists of a series of information bits? Cut series H1l~H1
6 is supplied to the correction adder circuit group all K via the 1-word delay circuit D3B. Below, 16 word delay circuit D34 e D35 + D36 * 037・I) a
a and addition circuit group for correction "12 * a13 e a1
4 + a15 g "16" are sequentially shaken. The corrected information bit series is sent to the switch circuit (421fC
is supplied and converted into PCM signals of the left and right channels,
They appear at the output terminals (43L) and (43R), respectively.

Six 1-word delay circuits and six 15-word delay circuits are arranged in series so as to be alternately located at the output of the adder circuit (to) and θG, respectively. Syndromes are extracted from the final stage and between the predetermined stage and added to the correction logic circuit (4υ).

The other embodiments of the present invention described above are also concept extensions of the one embodiment described above. Although the details of the error correction operation of the decoder are omitted, the addition circuits C31 and (40 to
When 89 and
141S * ysy l Y2Os yl ) and (X
-47e x-91i + x-143ex-191#
X-2:l*x-287) appears and a correction logic circuit (41)K is added.

According to the present invention described above, it is possible to realize an information word error correction method that is effective for correcting burst errors. In addition to the convolutional code, an error detection code such as CR
A code configuration using C code is also possible. However, according to the present invention, it is possible to improve the correction ability by using such a code structure. In order to explain the comparison of correction capabilities, FIG. 11 shows a graph in which the vertical axis represents the number of corrections and missed corrections (number per hour) and the pit correlation coefficient represents the horizontal axis. The closer the pit correlation coefficient is to (0,999), the more bursty the errors are, and conversely, the closer the pit correlation coefficient is to (0,900), the more random the errors are. The characteristic shown by the solid line in FIG. 11 shows the case where a CRC code is used in place of the parity pit series Q. According to the present invention, as shown by the broken line, it is possible to reduce the number of errors in correcting or missing corrections, and to make it resistant to random errors.

Note that in the above embodiment, a parity pit series Q t- is added to every 3 words, and in the other embodiments, a parity pit series Q t- is added to every 7 words, but a parity pit series Q is added to every arbitrary word other than these values. You may also do so.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an encoder in an embodiment of the present invention, FIG. 2 is a route map used for explanation, FIG. 3 is a block diagram of a decoder in an embodiment of the present invention, and FIGS. 4 and 5 6 is an overall block diagram of another embodiment in which the present invention is applied to a PCM recording and reproducing apparatus using a VTR, and FIG. 7 is a block diagram of its encoder. Figures 8 and 9'' are route maps used to explain the encoder, Figure 1θ is a block diagram of a decoder according to another embodiment of the present invention, and Figure 11 is a route map used to explain the present invention. (1) is the input terminal, (3), (4), (9)
, Part 02. (to), (to). K (ha1 to a16 are addition circuits, an, (41) are correction logic circuits, Dl "" Dl2 s D15 to D1
8 * D19L s D19R# D20L #D2
0Rs D21 to I)as are delay circuits, respectively. G K-e fc-v Z-51c,z Z-z
Zr Zs Xi 2t zs ZnFigure 3Figure 5Figure 6Figure 9nu
nνFigure 7

Claims (1)

[Claims] a plurality of first blocks such that a digital signal in which one word is composed of a plurality of bits is divided into a first predetermined number of plural information words, each of which includes the first predetermined number of plural information words divided; A plurality of first error correction words are generated from the plurality of words included in each of the plurality of first blocks, and each of the plurality of first error correction words is generated from the plurality of information words included in the plurality of first blocks. The plurality of second blocks are configured to include a second predetermined number of plural information words selected from mutually different blocks, and each of the plurality of second blocks is configured to include a second predetermined number of plural information words selected from mutually different blocks. error correction words are generated, the plurality of information words, the plurality of first error correction words and the plurality of second error correction words are received, and the plurality of error correction words are used to generate the plurality of error correction words. corrects a plurality of information words included in second blocks of the plurality of blocks, and configures the plurality of first blocks from the plurality of information words included in the plurality of second blocks, and corrects the plurality of first error correction words. A method for correcting errors in information words, characterized in that the plurality of first blocks are corrected using the method.