JPS63294133A - Digital modulating/demodulating method and its circuit - Google Patents

Abstract

PURPOSE:To reduce the deterioration of performance, by dividing data to be converted into 6-bit units and converting each 6-bit unit into 8-bit codes, and then, alternately converting codes which are 5:3 to codes which are 3:5 in the case other than codes which is 1:1 CONSTITUTION:Data to be converted are divided into 6-bit units and respective data d0-d5 are respectively converted into 8-bit codes C0-Cn. At the time of this conversion, the section between codes is constituted of a pattern in which the number of '0' between '1' and '1' is two or less and the 8-bit codes C0-C7 of codes having DC components '0' in which the ratio of the number of '1' to the number of '0' of NRZI-converted signals is 1:1, codes having DC components '+2' in which the ratio is 5:3, and codes having DC components '-2' in which the ratio is 3:5. When the data are converted into codes having DC components '+ or -2' at the time of modulation, codes having DC components '+2' and '-2' are selected so that the DC components can be offset each other successively. Therefore, the deterioration of the charactsristic can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital modulation/demodulation method and circuit for use in an apparatus for recording and reproducing digital signals.

[Conventional technology]

An example of a conventional digital modulation method is JP-A-59-2.
As described in Publication No. 31956, 4-bit data is converted into 6-bit data.
There is so-called 4-6 modulation for converting into a bit code, and 8-10 modulation for converting 8-bit data into a 10-bit code as described in Japanese Patent Laid-Open No. 60-93857. Table 1 shows the characteristics of both modulation methods.

・ ４ ・ Both of these methods remove the DC component in the frequency spectrum of the recording waveform, and the data bi-stop cell interval is set to T.
Then, in the 4-6 modulation method, Tmax (hereinafter, the maximum inversion interval of the modulation signal is abbreviated as Tmax and the minimum inversion interval is abbreviated as Tm1n) is as small as 2T, and overwriting (automatic overwriting) is performed to keep the TmaJmin ratio as small as 3. This is a method that exhibits superiority in terms of (1-light) characteristics and crosstalk characteristics. In addition, the 8-10 modulation method is Tm1n-0
．． A method that exhibits superiority in error characteristics in high-density recording by making it as large as 8T [Problem to be solved by the invention] The above conventional technology has a DC component and Trmx (z)G
Although Tm1n is considered, all so
G) There was no consideration given to satisfying all parameters at the same time. Therefore, for example, in the 4-6 modulation method (G), Tm1n is 9.67T and the recording density ratio is as small as 0.67, and the problem is that the higher the density recording, the worse the error characteristics are compared to the 8-10 modulation method. There is. In addition, Oharite's short wavelength (Tm1n) is converted into a long wavelength (Tm1n).
The unerased component becomes the largest when overwriting is performed using the 8-10 modulation method, where Tm and ax are 3.2T, and Tmax When the /Tm1n ratio is as large as 4, a problem arises in that override characteristics and crosstalk characteristics deteriorate with respect to 4-6 modulation.

The purpose of the present invention is to eliminate the DC component, increase Tm1n and the recording density ratio, and increase the Tm1n and recording density ratio to solve the above problems.
By reducing the ax and Tmax/'I'm In ratios, the error characteristics during high-density recording can be improved to 8-1.
It is an object of the present invention to provide a digital modulation/demodulation method and circuit which can achieve performance comparable to 0 modulation and at the same time have override characteristics and crosstalk characteristics comparable to 4-6 modulation.

[Means for solving problems]

The purpose of the above is to divide the data to be modulated into 6-bit units and convert each piece of data into a predetermined 8-bit code. Consisting of a pattern in which the number of 0" between "1" and 1" is 2 or less,
The number of l” and 0 of the signal obtained by converting the 8-bit code to NRZI
Code with 0 DC component, where the ratio of the number of `` is 1 to 1, 5 to 3
DC component +2 code, DC component - 3:5
This DC component +2 code and -2 code must correspond to one piece of data as a pair. When converting to a code where the DC component is +2 during modulation, this DC component must be sequentially converted into a code with a +2 DC component. +2 to offset. This is achieved by controlling the selection of -2 codes.

[Effect]

By converting the 6-bit data into an 8-bit code, the recording density ratio is set to 0.75, and the 4-6 modulation is 0.67.
’1” and 1 of the 8-bit code
Tm
a x=2.25 T and Tm a x/Tmin
The ratio is 3, which is smaller than 4 in 8-10 modulation, and 4-6
It is equivalent to modulation, and even if it is converted to a code with a DC component of ±2, it is controlled to cancel it out with a code that has components of opposite polarity, so the DC component can be removed on average. It has an effect.

, 7.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure is an explanatory diagram showing an example of a conversion table constituting 6-8 modulation according to the present invention. The pattern adopted as an 8-bit modulation code is the pitch 1 (J) that falls between bits "'1" and "1" even at the boundary where the modulation codes connect
satisfies the condition that the maximum number of items is 2. Further, among the patterns satisfying the above conditions, 46 code patterns are adopted in which the number of bits "'1" and "0" in the recording signal pattern obtained by NRZI conversion are equal, that is, the number is DC balanced. However, in 6-8 modulation for converting 6-bit data into 8-bit codes, 64 8-bit codes satisfying both of the above conditions are required, so codes with a DC component of +2 are assigned to the remaining 18 patterns. Here, a code with a DC component of +2 is assigned to table "0", and a code with a DC component of -2 is assigned as a pair to table "'1". The code pattern in which the DC component is O is the same for both tables "0" and WIN, and the DC component is canceled during modulation.8.

For this purpose, a control flag is added as shown in FIG. This flag indicates the table that the next modulated data will use for conversion. By switching the conversion table according to this flag and sequentially modulating the data, the DC components of both can be canceled when the code is converted to a code with a DC component and then converted to a code with a DC component. Can be done.

This operation will be explained in more detail with reference to FIG.

Figure 2 (3) shows - For example, the data is 15'', 11M,
This shows the case where the code continues as ``'28'', and the code pattern obtained by modulating this using the conversion table shown in Figure 1 is shown in the figure (
B). This is data ``'15'' of table ``0''
Since the flag is O, table 0 is used when converting the next data "1", and since the flag at this time is 1, the conversion of the next data "28" represents the operation according to table 1. . Furthermore, since the modulation code of ω) is NRZI-converted before being recorded and transmitted, its signal pattern becomes a waveform inverted at the bits of the modulation code, as shown in (C).Here, the Tmax pattern is This is a case where two 0's exist between bits "1" and "1" of the modulation code, and the Tm1n pattern is a case where '1's are continuous.

Furthermore, when evaluating the DC component, one bit in the "H" state of the recorded waveform is charged 1, and one bit in the "L" state is charged -1.
D 8 V (Digita
18um Varlatlon) value. The data "'15" and π" are codes having a DC component, and the data "1" is a code that maintains DC balance within the 8-bit code.

Therefore, the transition of DSV shown in (D) of the same figure is DSV at point Q1.
8 V = +2, and the next data is a DC-balanced code in units of 8 bits, so it is point Q.

Therefore, D SV =+2 remains. However, at point Q, which is converted into a code with a DC component for the second time, DSv converges to 0, canceling out the previous DS V = +2, and DC balance is maintained at this point. represents. This is the result of controlling the conversion table used by the flag so that if the data "'15" is a code having a DC component +2, the DC component of the next data "28" having a DC component becomes -2. In other words, in the NRZI-converted recording waveform, as shown by point P1, a code in which the number of bits in the "H" state starts from the 'L' state and becomes 5 is defined as a DC component +2.3, as a DC component -2. , and are unified into tables ``0'' and ``1'', respectively. Furthermore, according to the above definition, when NRZ I conversion is performed using a code with a DC component of ±2, the same value as the table in which the code exists is added as a flag value to the code where the starting state and ending state are reversed, and the code that is not reversed is The conflicting table values are used as flag values. This is because when NRZI conversion is performed from the code 5-HN state where the DC component is ±2 according to the above definition, the polarity is reversed and the DC component is also reversed to:i:2. Also, it is necessary to manage the final state after NRZ I conversion for codes that do not have a DC component, so for codes whose state is reversed, contradictory table values are used as flags, and for codes whose state does not change, that code is By setting the table value where exists as a flag, it is possible to cancel and remove the DC component.

The conversion table for 6-8 modulation constructed in this way is shown in FIG. 1. In this embodiment, the circuit scale reduction and simplification for realizing the 11° 6-8 modulation, which is the present invention, are taken into consideration. When selecting a code pattern that has a DC component, the codes in both tables are assigned patterns in which only the most significant bits are inverted, but there are other code patterns that have the effect of the present invention, as far as the one shown in Figure 1 is concerned. isn't it. Although the correspondence between data and code patterns is arbitrary, PLA (Programmable Logic
It goes without saying that it is effective to use a correspondence that can simplify decoding such as Array). FIG. 1 is an example of correspondence between data and codes in consideration of reducing the scale of the modulation/demodulation circuit.

Next, a synchronization signal pattern suitable for the 6-8 modulation of the present invention will be explained. The synchronization signal originally satisfies the modulation rules,
Also, a pattern that does not exist in the serial bit sequence after modulation is valid. Table 2 shows an example of an 8-bit pattern that satisfies the 6-8 modulation conversion rule of the present invention and is not adopted in FIG.

, 12° Table 26-8 Unused Codes in Modulation Rules The codes shown in Table 2 are synchronization signal pattern candidates.
These are all patterns that may occur in the serial bit sequence after modulation; that is, if these are adopted as a synchronization signal, erroneous detection may occur even if there is no code error. To solve this problem, digital signal recording and reproducing devices usually have a synchronization signal detection protection circuit on the reproduction side to absorb code errors, jitter, etc., and open the gate only for a few bits near the timing that can be detected in a normal cycle. Since the synchronization signal is detected by using the synchronization signal, not all synchronization signal patterns that occur by chance at an arbitrary position will be detected incorrectly.

A particular problem here is when a pseudo-synchronization signal pattern occurs immediately after an originally strong synchronization signal. The bit correlation, which is the probability of this occurrence, and the suspicious pattern occurrence distance with respect to the correct synchronization signal position were determined and are listed in Table 2.

Here, among the patterns in Table 2, the pattern with the minimum bit correlation has a low probability of false detection and is optimal as a synchronization signal pattern. However, among the codes shown in Table 2, there is no code where DC=O, and also for the DC=±2 code, Tmax
Due to the conditions, the first bit reversal rule described above cannot be used.

Therefore, a different synchronization signal pattern from table "0" 8119 is adopted.

Adoption of the synchronization signal pattern described above can realize word synchronization during modulation and demodulation without impairing the initial characteristics of the 6-8 modulation according to the present invention, but erroneous detection may occur during demodulation even if no code error occurs. Considering a high-density recording system in which many code errors occur, the probability of erroneously detecting a synchronization signal increases, which may become a problem.

Therefore, as an example of a synchronization signal candidate pattern that never occurs in a modulated bit sequence without a code error, we will introduce a pattern outside the 6-8 modulation rule, that is, Tmax
= 3 T is shown in Table 3, and the bit correlation was determined in the same manner as described above.

・15 ・ Table 36-8 Modulation rule outside synchronization signal candidate pattern However, e
is the pit error rate. Here, e means the pit error rate, that is, the probability of a 1-bit error due to a code error. In a digital audio recording and playback system, e is usually 1O-f.
The probability of generating an erroneous synchronization signal pattern is extremely low at about 10-8, and the reliability is improved by 16 degrees. Furthermore, the patterns No. 8 to 1@10 are DC=±2 codes, and if the rule of reversing the leading bits is performed, Tmax=3T will be exceeded, so they cannot be used in pairs with different leading bits.

FIG. 3 shows an embodiment of a digital signal recording and reproducing system using 6-8 modulation according to the present invention. FIG. 3 is a block diagram when the system is used, for example, in a system for recording and reproducing 2-channel PCM audio with a sampling frequency of 48 KHz, f/child conversion of 16 bits, and a VTR.

Here, in order to keep the recording wavelength to a level that can be realized, it is possible to reduce the amount of information by compressing the 16-bit quantized value into 12 bits. Based on this, this embodiment The internal processing is a 12-bit system. In the figure, 4゜5 is an input amplifier, 6 and 7 are low-pass filters, 89 is a sample and hold circuit, 10 is a beam, an R channel signal switching circuit, 11 is an A/D converter, and 12 is compression that compresses 16 bits into 12 bits. 13 is an internal data bus, 14 is a memory (for example, RAM), 15 is a code emission and error detection and correction circuit, 1
6 is a 6-8 modulation circuit based on the present invention described above; 17 is a synchronization signal generation circuit suitable for the 6-8 modulation described above; 18
19 is a data and synchronization signal switching circuit, 19 is a recording amplifier, 20 is a cylinder, 21 is a rotary head, 22 is a magnetic tape, 23 is a reproduction amplifier, 24 is a waveform equalizer, 25 is a data strobe circuit, and 26 is a synchronization signal detection protection circuit, 28
27 is an address detection protection circuit, 27 is a 6-8 demodulation circuit of the present invention, 29 is a memory address generation circuit, 30 is a memory address selection circuit, 31 is an interpolation circuit, 32 is a circuit that expands a 12-bit signal to 16 bits, 33ha D/A
converter, 34 and 35 are sample and hold circuits;
36 and 37 are low-pass filters, and 38 and 39 are output amplifiers.

First, the R channel audio signal is input from the input terminal 2.3 via the input amplifiers 4 and 5, and is cut in the high frequency range by the low pass filter 6°7 according to the sampling frequency.
, R2 channels are sampled and held and subjected to human/D conversion. The 16-bit digital signal obtained here or the 16-bit digital signal inputted from the input terminal 1 is compressed into 12 bits by the compression circuit 12 and stored in the memory in units of upper and lower 6 bits. From the data stored in the memory, a predetermined error correction code (Nigalois type (2')' in 6-bit units) is generated, a block address, an ID code, etc. are added to form a signal in block units, and 6- 8 modulation circuit 16, the first
Convert to the 8-bit code shown in the figure and generate the synchronization signal w
At step 517, the synchronization signal pattern shown in Table 2 or Table 3 is added and recorded on the tape. During playback, signals on the tape are read out by the magnetic head 21 and input to the waveform equalizer 24 via the playback amplifier blades. Furthermore, the data strobe circuit 25 performs waveform shaping, signal identification, and reproduction clock extraction, the synchronization signal detection protection circuit 26 detects only the correct synchronization signal, and the address detection protection circuit correctly detects the block address added during recording. do. At the same time, based on the synchronization signal from the data string reproduced by the 6-8 demodulation circuit 27,
After demodulating a predetermined correct 8-bit code into 6-bit data and storing it in the memory 14, a correction circuit 15 detects and corrects code errors that occur during the reproduction process, and data that cannot be corrected is processed by an interpolation circuit 31. After interpolation, the 12 bits of the predetermined upper 6 bits and lower 6 bits are sent to the expansion circuit 3.
2 to 16 bits, performs D/person conversion, and sends the original audio signal to output terminals 40 and 41, respectively, I, R2.
Separate and output into channels. The 6-8 modulation of the present invention also has the advantage of good consistency when used in the 12-bit system.

Next, an embodiment of a modulation circuit realizing 6-8 modulation of the present invention will be described with reference to FIGS. 4 and 5.

In Fig. 4, 161 is a 6-bit latch circuit, 167 is a 1-bit latch circuit, and 162 is a circuit for converting into the predetermined code shown in Fig. 1, for example: FLOMl or PL (programmable logic array), etc. is an 8-bit shift register, and 52 is an NRZ I modulation circuit.

Further, signals are input and output to and from terminals A to E at timings such as those shown in FIG. 5, for example. Here, when arbitrary 6-bit data is input from input terminal A, it is latched,
For example, in the code conversion circuit 162, 6 as shown in FIG.
-Convert 6-bit data into 8-bit code according to the 8-modulation table. In this code conversion, the flag shown in FIG. 1 is input separately from the 6-bit data, and the flag shown in FIG. 1 is decoded and output separately from the output of the 8-bit code. Since this flag represents the table to be used in the next conversion, it is stored in the latch circuit j12i 167 and is input to the code conversion circuit 162 as an identification signal of the table to be used in each conversion. Furthermore, the correspondence for converting 6 bits of data into an 8 bit code is not limited to the one shown in Figure 1, but any one-to-one correspondence is possible, and the circuit scale of the code conversion circuit 162 is usually the smallest. It is effective to make the correspondence so that After being converted into an 8-bit code, parallel/serial conversion is performed by the shift register 163, and NRZ
NRZI inverted by bit “1” by I modulation circuit 52
Output from terminal E as a waveform.

FIG. 6 shows another embodiment of a modulation circuit realizing 6-8 modulation of the present invention. This embodiment includes a synchronization signal generation circuit,
A circuit is provided to independently control the first bit and flag of the conversion code, and the code conversion circuit decodes only the 8-bit code of a single table, thereby reducing the circuit scale. In the figure, the same reference numerals as in FIGS. 1 to 5 indicate the same circuits and signals having the same functions. Here, 60 is a code converting circuit such as a PLA that decodes only the conversion table shown in FIG. Then, D C shown in Figure 1
A code with =+2 or -2 is detected from an 8-bit code or 6-bit data by decoding or the like. 62
63 is an inversion number detection circuit, which determines whether the number of inversions on the NRZI waveform, that is, the number of bits "1" in the 8-bit code, is an odd number or an even number; 63 is a circuit for generating a flag signal (C) and a synchronization signal or A control circuit selects the first bit of the 8-bit code as 0'' or 1'', 64 is an EOR circuit that inverts the first bit, 50 is a synchronization signal generation shown in Table 2 or Table 3, and 8-bit code C0~
This is a synchronization signal generation circuit that performs switching with C1.

Here, for example, the code conversion circuit 60 is
If the circuit decodes only "0", then when conversion is performed using the table "1" based on the flag, only the DC code inverts the first bit, so the DC code detection circuit 61 decodes the 6-bit data. , or detect the DC code by decoding from the 8-bit code, etc., and if the flag at the time of previous conversion is 1', the EOR circuit 6
4 inverts the first bit of the 8-bit code. Also D
The code where C=O has the same turn/turn for tables "O" and "1", but the flags are different, so a flag is generated by the inversion number detection circuit 62.The characteristics of the flag are shown in Figure 1. Accordingly, when the table is "O", the flag becomes 1" when DC=O code and the number of inversions (number of 1"s) of the 8-bit code is an odd number, and when DC=+2 code and the number of inversions is an even number. , the flag=″′1”.

Furthermore, when using table "1", if DC123°10 code and the number of inversions is an even number, then DC=
-2 code and the number of inversions is an odd number, flag = '“1
”.This is summarized in Table 4 as a truth table.

Table 4 Flag generation truth table DC code O...DC=O code...DC-±2 Number of code inversions 0...Even number 1...Odd number Therefore, flag generation logic shared by tables "0" and "1" The formula is as follows.

Flag = DC code ■ Number of reversals ■ Table code...
Logical formula (11) where ■ represents EOR (exclusive OR).

FIG. 7 shows a specific embodiment of the 6-8 modulation circuit shown in FIG. 6 using the above equation. In the figure, the same reference numerals as in FIGS. 1 to 6 indicate the same circuits and signals having the same functions. Here, 70 to 76, 630, and 631.166 are BOR circuits, 175.179 to 182.77 are OR circuits, and 174
．． 176-178 are NOR circuits, 169-172, 1
64 is an inverter circuit, 634 is an AND circuit, 165,
632 is a latch circuit, and the synchronizing signal generation circuit 50 in FIG. 6 is the gate circuit jl! in FIG. 169-1
It consists of 82 pieces. However, the synchronization signal pattern used in this example is 11100010' shown in Table 3 as an example.
/f turn is adopted, and other patterns are also acceptable. Also, the number of reversal detection circuit is the gate circuit 7.
This is realized by performing EOR addition of all bits using 0 to 76, and the DC code detection circuit uses gate circuits j12i73 to 75.
It is shared by Control circuit 63 shown in FIG.
In FIG. 7, gate circuits 77, 630, 63L63
4 and a latch circuit 632, and the NRZI modulation circuit consists of gate circuits 164, 166 and a latch circuit 165.
Consists of. Here, the flag is determined by the above logical formula (1),
This is obtained from the output of the gate 631, and by latching and storing it, the output of the latch circuit 632 indicates the tables "'0" and "1" to be selected at the time of conversion.Therefore, the inversion of the first bit is AND gate 63 because it is a DC code and only when the table "'1" is used during conversion.
4 and 130R circuits 64.

FIG. 8 shows an example of a specific modulation circuit for realizing 6-8 modulation according to the present invention. This embodiment is an example constructed based on the conversion table shown in FIG. 1, and the synchronization signal adopts the "'11100010" pattern as in FIG. 7. In the drawings, the same symbols as in FIGS. 1 to 7 indicate the same circuits or signals having the same functions. Here, 800 to 841 are rNAND, NOR, and EOR depending on each symbol.
, ENOR, and inverter circuits, and 601 is a PLA circuit with a NAND-N-ND configuration. In addition, gate circuits 825 to 833 constitute a synchronization signal generation circuit, and D
The C code detection circuit is composed of BORs 834-836.

Further, in this embodiment, flag generation is performed by gates 837 to 840 and latch circuit 842 according to the following logical formula.

Flag = C, ■C3■C7■C7■Table code ・
...Logical formula (2), where ■ indicates FIOR, addition, and table code. As mentioned above, the flag generated during the previous code conversion is stored (delayed), and the latch circuit 84 in the figure
This can be achieved with 2. The first bit is inverted by the gate 841 depending on the detection of the DC code and the state of the flag, as described above.
, 64. This allows code conversion port ji2!
60 can be realized by simply decoding table "0". Here, this code conversion circuit 60 includes a PLA circuit 601 and gate circuits 800 to 8 to reduce the circuit scale.
This was achieved by using 24 in combination. In other words, in the conversion table shown in Figure 1, the data is divided into those whose codes can be converted according to regular rules and those whose codes cannot be converted, and the regular ones are converted using the PLA circuit, and the other ones are converted using the gate circuit. 82
The configuration is such that correction is performed in the range of 0 to 824. Furthermore, in conversion using a PLA circuit, the upper 3 bits of data G + '4
+G is 100'' and other times, the conversion rule is changed and decoded, so the data bit input (I, ~ J6
), the seventh input J, and the upper three bits of data d, d.

By inputting and switching the gate 8o5 that detects ds ``1000'', T1 to T are used as product terms for calculation.
This was achieved with 12 pieces of IT. Next, an embodiment of a 6-8 modulation demodulation circuit according to the present invention will be described with reference to FIG.

In the figure, 271 is a demodulation circuit that converts the NRZI signal to an NZ signal, 272 is a circuit that converts serial data to 8-bit parallel data, 273 is an 8-bit latch circuit, and 27
4 converts the 8-bit codes C0 to C1 into predetermined 6-bit data d based on the conversion table shown in FIG. 275 is a 6-bit latch circuit, 261 is a 1/8 frequency divider circuit, 262 is a synchronization signal detection circuit, and 263 is a synchronization signal detection circuit. In the protection circuit, 268 is a modulation data input terminal, and 269 is a clock input terminal. A modulation signal and a clock synchronized with it are input from input terminals 268 and 269, and when the next data is shifted to the serial/parallel conversion circuit 272, a synchronization signal as shown in Table 29 and Table 3 above is generated from this data string. The pattern is detected by the synchronization signal detection circuit 262, and further detected by the synchronization signal protection circuit 263.
In addition to determining the correct synchronization signal and replenishing it when it is missing, the
Set the 78 frequency division counter 261 and set the input clock to 1.
A latch circuit 273 latches the code that is frequency-divided by 78 and input to the serial/parallel conversion circuit in predetermined 8-bit units. The latched 8-bit code is converted into 6-bit data d0 to 8-bit code C3-C1 by the code conversion circuit 274 according to the conversion table shown in FIG.
dl and latched by the latch circuit 275. In the above configuration, the demodulation code conversion circuit 274 is 2Kbit.
This can be easily achieved by using a ROM or a full decoding PLA circuit with 256 product terms, but there is a problem in that the circuit scale becomes large. Next, an embodiment of a 6-8 demodulation circuit that reduces the circuit scale will be described with reference to FIG. 10.

In FIG. 10, the same symbols as in FIGS. 1 and 9 indicate the same circuits and signals having the same functions.

Here, 300 is a DC code detection circuit, 301 is a bit conversion circuit that fixes the first bit of the code to, for example, "0," and 302 is the lower 4 bits of the code that are 1001.

303 is an inversion control circuit that inverts the state of the signal; 304 is a circuit that converts a predetermined 8-bit code based on FIG. 1 into 6-bit data; 1 code conversion circuit; 305 is a second code conversion circuit that converts another predetermined 8-bit code based on FIG. 1 into 6-bit data; 3;
For 06, the lower 4 bits of the code are '0010'', ``00''
11'', '0110', and 307 is a switching circuit that selects and outputs the outputs of the code conversion circuits 304 and 305. This embodiment is based on the conversion table shown in FIG. 1 to simplify the demodulation circuit. Therefore, when demodulating a DC code, pairs of codes with different leading bits correspond to the same data, so for example, when the DC code detection circuit 300 detects a DC code, it outputs 0'', By fixing the first bit of the DC code to '0' and making the code and data correspond one to one, decoding is simplified. Of course, it may be fixed to 1" instead of 0. Furthermore, as can be seen from the conversion table in Figure 1, the irregular pattern is such that the lower 4 bits of the code are 0010.
” or “0011” or “0110”, this is detected by the detection circuit 306, and
A first code conversion circuit 304 performs conversion for a regular pattern, a second code conversion circuit 305 performs conversion for an irregular pattern, and a selection circuit 307 outputs the selected code. In addition, the first code conversion circuit converts the regular pattern, but in this case, the lower 4 bits of the code are '100'.
1", 1011".

When it is "1110", by inverting the fifth bit C4 of the code, the circuit becomes more regular and the circuit can be further simplified. Therefore, this is detected by the fixed pattern detection circuit 302, and the inversion control circuit 303 (for example, g
(OR circuit) realizes inversion control.

Also, when converting an irregular pattern, all 8 bits of the code may be used for decoding, but the code bits col
By checking whether the code is c, l CM + c, l c, or DC code, it is possible to establish a one-to-one correspondence between code and data, and it is possible to further reduce the circuit scale. Note that the code conversion circuit 304
, 305 into one, it is also possible to simplify the circuit and wiring. In this case, a 10-manpower 6-output circuit that further receives the output of the irregular pattern detection circuit as the input of the code conversion circuit is used as the input of the code conversion circuit. This can be realized by a circuit, and of course the switching circuit 307 is not necessary.

FIG. 11 shows a more specific embodiment of the 6-8 demodulation circuit based on FIG. 10. Here, the same symbols as in FIG. 10 indicate the same circuits and the same signals having the same functions. In addition, this embodiment is a case in which the code conversion circuit, switching circuit, and various detection circuits are all configured with gate circuits, and 900 to 947
is NAND, NOR, BN according to each symbol
OR represents an inverter circuit. DC shown in Figure 10
The code detection circuit is gates 900 to 902, the bit conversion circuit is gate 905, and the fixed pattern detection circuit is gate 90.
Q, 903°904, inversion control circuit is gate 907
, the first code conversion circuit has gates 910 to 917, the second
The code conversion circuit consists of gates 918 to 927, and the switching circuit consists of gates 930 to 947. The DC code detection circuit is DC=CO■C2■C, -... (31 fixed pattern detection circuit is c, ・C3-(colcri -...L4)) The irregular pattern detection circuit is C5. (co■02)...(51 The first code conversion circuit is d, =C1... (6) d, =C,... (7) d3=C' ,・C,-1-C,・C1... (8)
d, =Co-Ct・=-(9] d, =C,・C3+te.・) ・・・・ (lII
Ido=Co-C, + Co-C, -...-α The second code conversion circuit is d, = C'l・Co... (b) d
, =0... μsd, - gu・co
... 1. L◆dt=C6・C6-c,
+ C6・C't・Cs+ C6-CB・c, -DC"
” ('1d,=to・C1l+to・bow・arrangement
・・Song αedo=C, ・@ −C, +C, ・C7+C
, ·C, -C, -... -aη. Here ■ is EOR logic, C2 is inversion controlled C6,
c′r represents bit-converted C7, and the switching circuit outputs (6) to 0 when the logical formula (5) is 0, and the logical formula (3)
When 1 is 1, (6) to αno are selected and output.

〔Effect of the invention〕

According to the present invention, Thxin ~0.75 T Tmax ~2.25 T TmaVin = 3 Recording density ratio = 0.75 DC component; removed (T is 1 bit interval of data before conversion) This makes it possible to perform high-density recording and to reduce performance deterioration due to the effects of crosstalk and override.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a conversion table which is an example of 6-8 modulation according to the present invention, Fig. 2 is a timing diagram showing the operating principle of DC component removal in the present invention, and Fig. 3 is a 6-8 modulation according to the present invention. A block diagram of a recording and reproducing system using modulation. FIG. 4 is a block diagram of a modulation circuit which is an example of 6-8 modulation according to the present invention. FIG. 5 is a modulation circuit and operation timing of 6-8 modulation according to the present invention. 6-8 according to the present invention.
FIGS. 7 and 8 are modulation circuit block diagrams showing another example of 6-8 modulation according to the present invention, and FIG. 9 is a block diagram of a modulation circuit showing another example of 6-8 modulation according to the present invention. FIG. 10 is a block diagram of a demodulation circuit that is an example of -8 modulation, FIG. 10 is a block diagram of a demodulation circuit that is another example of 6-8 modulation according to the present invention, and FIG. 11 is a block diagram of a demodulation circuit that is an example of 6-8 modulation according to the present invention. FIG. 7 is a demodulation circuit diagram of another embodiment. Code explanation d0-d1... 6-bit data for modulation or demodulation C0-C1... 8-bit code 50 for 6-8 modulation...
- Synchronous signal generation circuit 60...Modulation code conversion circuit 61...DC code detection circuit 62...Inversion number detection circuit 63...Starting bit inversion control circuit 300...
- DC code detection circuit 301...Bit conversion circuit 302...Fixed pattern detection circuit 303...Inversion control circuit 304...First demodulation code conversion circuit 305...
Second demodulation code conversion circuit 306...Irregular pattern detection circuit 307...Switching circuit △ Fig. 5 E NP7I C7Co CCC9C4C5Ct; Fig. 6 and -1\-1-// 8 Fig. 10 )A-7'/do

Claims (1)

[Claims] 1. Data to be modulated is divided into 6-bit units and each is converted into an 8-bit code, and the 8-bit code has a bit “1” and a bit “1” even at the boundary between codes.
A code in which the number of bits “0” in between is 2 or less, and the number of bits “1” and bit “0” after NRZI conversion of the 8-bit code is 1:1, and 5:3 or 3 pairs. 5, and the above 5 to 3 or 3 to 5
The code corresponds to one piece of data as a pair of 8-bit code with the leading bit inverted, and when converting 6-bit data to 8-bit code, in cases other than the above 1:1 code, 5:3 A digital modulation method characterized by alternately converting a code with a ratio of 3 to 5 and a code with a ratio of 3 to 5. 2. A latch circuit for 6-bit data as data to be modulated, a code conversion circuit that takes the 6-bit data of the latch circuit as input and converts it into a predetermined 8-bit code, and generates a predetermined synchronization signal pattern at a predetermined timing. a synchronizing signal generating circuit that outputs the synchronizing signal and the output of the code converting circuit by switching it with the output of the code converting circuit; a parallel/serial converting circuit that outputs the parallel signal of the synchronizing signal and the output of the code converting circuit as a serial signal; and a bit of the serial signal. In a digital modulation circuit consisting of an NRZI modulation circuit that inverts the state at "1", the 8 bits after the NRZI conversion have a ratio of the number of bits "1" to bits "0" of 5:3 or 3:5. A DC code detection circuit that detects a code or 6-bit data corresponding to the 8-bit code, and an inversion that determines whether the number of bits "1" is an even number or an odd number from the output of the code conversion circuit or the output of the synchronization signal generation circuit. A control circuit is provided, which receives the outputs of the DC code detection circuit and the inversion frequency detection circuit and controls the inversion of the first bit of the 5-to-3 code or the 3-to-5 code. A digital modulation circuit characterized by: 3. In the digital modulation circuit according to claim 2, the following 8-bit patterns "11100010", "00100011", "10
010001”, “01000111”, “01110
001”, “10100010”, “01000101
”, “11010001”, or a pattern obtained by inverting the first bit of the above eight patterns as a synchronizing signal. 4. Divide the data to be modulated into 6-bit units, and The 8-bit code is converted into an 8-bit code, and the 8-bit code has a bit “1” and a bit “1” even at the boundary between codes.
” The number of bits “0” between ” is 2 or less, and 8
The bit code is composed of a code in which the number of bits “1” and bit “0” after NRZI conversion is 1:1, and a code in which the number is 5:3 or 3:5, and the above-mentioned 5:3 or 3 The code that becomes pair 5 corresponds to one piece of data as a pair of 8-bit code with the first bit inverted, and when converting 6-bit data to 8-bit code, it is necessary to convert to a code other than the above 1-to-1 code. In this case, the code becomes 5 to 3,
In a method of demodulating data modulated by digital modulation that alternately converts codes with a ratio of 3 to 5, a detection circuit detects a code having a DC component of the ratio of 5 to 3 or 3 to 5 from the 8-bit code to be demodulated. A digital demodulation method characterized in that when demodulating an 8-bit code detected by , the leading bit is fixed to "1" or "0" and then the 8-bit code is demodulated into predetermined 6-bit data. 5. In the digital demodulation method according to claim 4, irregular pattern detection is performed to detect an irregular pattern in which the lower 4 bits of the 8-bit code to be demodulated are "0010", "0011", or "0110". The output of the first conversion circuit converts the irregular pattern 8-bit code into predetermined 6-bit data according to the output of the circuit, and the output of the first conversion circuit converts the 8-bit code other than the irregular pattern into predetermined 6-bit data. A digital demodulation method characterized in that the output is switched between the output of the second conversion circuit and the output of the second conversion circuit.