JPS63293604A - Sequence table type controller - Google Patents

Sequence table type controller

Info

Publication number
JPS63293604A
JPS63293604A JP12796687A JP12796687A JPS63293604A JP S63293604 A JPS63293604 A JP S63293604A JP 12796687 A JP12796687 A JP 12796687A JP 12796687 A JP12796687 A JP 12796687A JP S63293604 A JPS63293604 A JP S63293604A
Authority
JP
Japan
Prior art keywords
signal
interlock
output
sequence table
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12796687A
Other languages
Japanese (ja)
Inventor
Masakazu Ikoma
雅一 生駒
Masato Nakano
正人 中野
Tetsuya Nagai
長井 鉄也
Yoshitomo Takeuchi
良友 竹内
Minoru Yoshino
吉野 稔
Ryosuke Maruyama
丸山 良介
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Fuji Facom Corp
Original Assignee
Fuji Electric Co Ltd
Fuji Facom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Facom Corp filed Critical Fuji Electric Co Ltd
Priority to JP12796687A priority Critical patent/JPS63293604A/en
Publication of JPS63293604A publication Critical patent/JPS63293604A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve the productivity and the quality of a program with a sequence table type controller by having the output of the state of a device designated as an interlock and the AND arithmetic result as the operation output signals. CONSTITUTION:The interlock conditions C are given to an output signal name and a process number B. In this example, the ON signal of an FIC103 and the OFF signal of a DI12 are applied to an output signal TIC101 and PL1 as the interlock signals respectively. Therefore the signal TIC101 is outputted only when the ON signal of the FIC103 exists; while the signal PL1 is outputted only when the OFF signal of the DI12 exists. Thus it is possible to obtain simple a sequence control function without deteriorating the program productivity and quality just by setting an equipment number and its state related to an interlock function.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、所定のプロセスを複数の工程に分割し各工
程毎に操作出力の状態を定義するテーブルと、プロセス
の各工程毎の移行条件とにもとづき一連の制御を行なう
シーケンステーブル式制御装置に関する。
[Detailed Description of the Invention] [Field of Industrial Application] This invention provides a table that divides a predetermined process into a plurality of steps and defines the state of the operation output for each step, and a table that defines the state of the operation output for each step, and the transition conditions for each step of the process. The present invention relates to a sequence table type control device that performs a series of controls based on the following.

〔従来の技術〕[Conventional technology]

従来、か−るシーケンステーブル式制御装置では例えば
第4図の如く、操作対象の出力状態が異なるごとに工程
を割υ付け、各工程毎に操作出力の状態を定義する、い
わゆるシーケンステーブルを用いてプログラムを行なう
のが一般的である。
Conventionally, such a sequence table type control device uses a so-called sequence table, which allocates a process to each different output state of the operation target and defines the operation output state for each process, as shown in Fig. 4, for example. Generally, the program is carried out using

すなわち、同図においてAは操作対象機器と対応する出
力信号名を示し、その各々の出力状態を斜線を施すか(
例えば、オン状態)、否が(例えば、オフ状11!li
りで示している。また、Bは工程を示し、これは実質的
には時間軸と考えることができる。
That is, in the figure, A indicates the output signal name corresponding to the device to be operated, and the output status of each is indicated by diagonal lines (
For example, on state), or not (for example, off state 11!li
It is shown by . Further, B indicates a process, which can essentially be considered as a time axis.

したがって、例えば出力TICi D 1は工程1゜2
.6および5ではオンとなシ、工程4ではオフとなるこ
とがわかり、同様に出力PL1では工程4.5ではオン
で、工程1,2.3ではオフとなることがわかる。
Therefore, for example, the output TICi D 1 is the step 1°2
.. It can be seen that the output is on in steps 6 and 5, and off in step 4, and similarly, it is found that the output PL1 is on in step 4.5 and off in steps 1 and 2.3.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、このようなシーケンステーブルでは、操
作対象となる機器によっては、主たる状態がオン(ON
)であっても、その機器に関連する他の機器の状態と連
動してONまたはOFF (オフ)しなければならない
場合があシ、このことは対象とするプロセスの実際上の
工程は1つであるのに見かけの工程を2つ以上心安とし
、この見かけの工程についてもそれぞれ工程間移行条件
を心安とすることになるので、プログラムの生産性が低
下するだけでなく、対象とするプロセスの工程とシーケ
ンステーブル上の工程とが一致しないため、理解し難い
ことによる品質の低下を招くなどの問題がらる。
However, in such a sequence table, depending on the device to be operated, the main state may be ON (ON).
), it may be necessary to turn the device ON or OFF in conjunction with the status of other devices related to it, which means that the target process is actually only one step. However, if two or more apparent processes are made safe, and the transition conditions between processes are made safe for each of these apparent processes, the productivity of the program will not only decrease, but also the target process Since the process and the process on the sequence table do not match, problems arise such as poor understanding due to poor understanding.

したがって、この発明は対象とするプロセスの工程とシ
ーケンステーブル上の工程とを一致させることができ、
かつプログラムの生産性2品質を向上させることが可能
なシーケンス制御装置を提供することを目的とする。
Therefore, this invention can match the steps of the target process with the steps on the sequence table,
Another object of the present invention is to provide a sequence control device that can improve the productivity and quality of programs.

〔問題点を解決するための手段〕[Means for solving problems]

操作出力一点毎にインターロック条件を付与可能にし、
出力するに当九っては該インターロック条件が付与され
ているか否かを参照して最終的な操作出力を決定する。
Interlock conditions can be assigned to each operation output point,
When outputting, the final operation output is determined by referring to whether or not the interlock condition is given.

〔作用〕[Effect]

シーケンステーブルの操作出力毎にインターロック条件
を付与可能にし、シーケンステーブルの工程に対応する
操作出力がONの場合でも、インターロックに指定した
機器の状態と論理積演算を行なった結果を操作出力信号
として出力することによシ、対象とするプロセスの工程
とシーケンステーブルの工程とを一致させ、かつインタ
ーロックに指定した機器との連動を可能にする。
Interlock conditions can be assigned to each operation output of the sequence table, and even if the operation output corresponding to the process of the sequence table is ON, the operation output signal is the result of performing a logical product operation with the state of the device specified for interlock. By outputting as , it is possible to match the steps in the target process with the steps in the sequence table, and to enable interlocking with the equipment specified for interlock.

〔実施例〕〔Example〕

第1図はこの発明の詳細な説明するための説明図、第2
図はインターロック信号と操作出力との論理的関係を示
すラダー図、第3図は第1図のシーケンステーブルにお
ける工程対応の出力、インターロック信号および出力最
終結果の関係を示すタイムチャートである。
FIG. 1 is an explanatory diagram for explaining the invention in detail, and FIG.
The figure is a ladder diagram showing the logical relationship between interlock signals and operation outputs, and FIG. 3 is a time chart showing the relationship between outputs corresponding to processes in the sequence table of FIG. 1, interlock signals, and final output results.

第1図からも明らかなように、出力信号名人および工程
番号Bに対し、さらにインターロック条件Cを付与した
点が特徴であり、と−では出力信号TIC101とPL
lに対し、FIC103のON信号とD112のOFF
信号とをそれぞれインターロック信号として付与した例
が示されている。したがって、論理的には第2図の如く
、出力信号TIC101はFIC103のON信号があ
るときのみ出力され、出力信号PL1はD112のOF
F信号があるときのみ出力される。その結果、第6図(
イ)、(ホ)の如き出力1,4に対し、それぞれ(ロ)
、(へ)の如きインターロック信号が付与されているた
め、出力最終結果はそれぞれ(ハ)、(ト)の如くなる
。これによシ、1〜5の工程番号も(ニ)の如く、1−
1.1−2 、2−1 、2−2 、3−1 、3−2
 、4−1 。
As is clear from FIG. 1, the feature is that an interlock condition C is further added to the output signal master and process number B, and in -, the output signal TIC101 and PL
For l, ON signal of FIC103 and OFF of D112
An example is shown in which each signal is provided as an interlock signal. Therefore, logically, as shown in FIG. 2, output signal TIC101 is output only when there is an ON signal of FIC103, and output signal PL1 is output from
Output only when F signal is present. As a result, Figure 6 (
For outputs 1 and 4 such as (a) and (e), (b) respectively.
Since interlock signals such as , and (f) are provided, the final output results are as shown in (c) and (g), respectively. In addition to this, the process numbers 1 to 5 are also 1-5, as in (d).
1.1-2, 2-1, 2-2, 3-1, 3-2
, 4-1.

4−2 、4−3 、5−1 、5−2 、5−3の如
く分割され、プロセスの工程とシーケンステーブル上の
工程とを一致させることができる。
The process steps are divided into 4-2, 4-3, 5-1, 5-2, and 5-3, allowing the process steps to match the steps on the sequence table.

このように、インターロック機能に関連する機器番号と
その状態を設定することによp1プログラムの生産性2
品質を損なうことなく簡単にシーケンス制御機能を構築
することが可能となる。なお、以上ではONまたはOF
F状態を制(財)する場合について説明したが、例えば
電動弁などの速度形の機器を制御する場合も、インター
ロック信号として弁位置りばットスイツチを設定し、開
指令。
In this way, the productivity of the p1 program can be increased by setting the device number and its status related to the interlock function.
It becomes possible to easily construct a sequence control function without compromising quality. In addition, in the above, ON or OF
Although we have explained the case of controlling the F state, for example, when controlling a speed-type device such as an electric valve, the valve position switch is set as an interlock signal and an opening command is issued.

閉指令の2組の操作出力を使用することによシ、位置決
め制−機能等を実現することができる。
By using two sets of operation outputs for the close command, positioning control functions, etc. can be realized.

〔発明の効果〕〔Effect of the invention〕

この発明によれば、シーケンステーブル式のプログラム
の作成のし易さおよび理解のし易さと云う利点と、ラダ
一方式のON、OFFの2直を1つの信号で扱えるとい
う利点の双方を、1司単な信号の割シ付けだけで利用す
ることが可能となυ、したがって、シーケンス制御機能
の構築を、高い生産性と品質をもち、対象とするプロセ
スの工程と合致した形で行なうことができる利点かもた
らでれる。
According to this invention, both the advantages of ease of creating and understanding sequence table type programs and the advantage of being able to handle two shifts of ON and OFF of a single ladder type with a single signal are achieved in one system. It can be used by simply assigning signals, therefore, it is possible to build sequence control functions with high productivity and quality, and in a manner that matches the target process steps. What benefits can be brought about?

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の詳細な説明するための説明図、8g
2図はインターロック信号と操作出力との論理的関係を
示すラダー図、第6図は第1図のジ−クンステーブルに
おける工程対応の出力、インターロック信号および出力
最終結果の関係を示すタイムチャート、第4図はシーケ
ンステーブルの従来例を説明するための説明図である。 符号説明 A、TlC101,PLl・・・・・・出力信号、B・
・・・・・工程番号、C,FIC103,DIi2・・
・・・・インターロック信号。 代理人 弁理士 並 木 昭 夫 代理人 弁理士 松 崎    清 第2図
Figure 1 is an explanatory diagram for detailed explanation of this invention, 8g
Figure 2 is a ladder diagram showing the logical relationship between interlock signals and operation outputs, and Figure 6 is a time chart showing the relationship between outputs corresponding to processes, interlock signals, and final output results in the Jiken Stable in Figure 1. , FIG. 4 is an explanatory diagram for explaining a conventional example of a sequence table. Code explanation A, TlC101, PLl... Output signal, B.
...Process number, C, FIC103, DIi2...
...Interlock signal. Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki Figure 2

Claims (1)

【特許請求の範囲】[Claims] 所定のプロセスを複数の工程に分割し各工程毎に操作出
力の状態を定義するテーブルとプロセスの各工程毎の移
行条件とにもとづき一連の制御を行なうシーケンステー
ブル式制御装置において、操作出力一点毎にインターロ
ック条件を付与可能にし、出力するに当たつては該イン
ターロック条件が付与されているか否かを参照して最終
的な操作出力を決定することを特徴とするシーケンステ
ーブル式制御装置。
In a sequence table control device that divides a given process into multiple steps and performs a series of controls based on a table that defines the state of the manipulated output for each step and transition conditions for each step of the process, 1. A sequence table type control device, characterized in that an interlock condition can be given to the control device, and when outputting, the final operation output is determined by referring to whether or not the interlock condition is given.
JP12796687A 1987-05-27 1987-05-27 Sequence table type controller Pending JPS63293604A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12796687A JPS63293604A (en) 1987-05-27 1987-05-27 Sequence table type controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12796687A JPS63293604A (en) 1987-05-27 1987-05-27 Sequence table type controller

Publications (1)

Publication Number Publication Date
JPS63293604A true JPS63293604A (en) 1988-11-30

Family

ID=14973085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12796687A Pending JPS63293604A (en) 1987-05-27 1987-05-27 Sequence table type controller

Country Status (1)

Country Link
JP (1) JPS63293604A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0418605A (en) * 1990-05-11 1992-01-22 Kobe Steel Ltd Method and device for preparing ladder sequence program
JP2005135383A (en) * 2003-09-05 2005-05-26 Fisher Rosemount Syst Inc State machine functional block equipped with user modifiable output configuration database
JP2007207196A (en) * 2006-02-06 2007-08-16 Seiko Instruments Inc Programmable logic controller, information processor, control program, and table preparation program
US8600524B2 (en) 2003-09-05 2013-12-03 Fisher-Rosemount Systems, Inc. State machine function block with a user modifiable state transition configuration database

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0418605A (en) * 1990-05-11 1992-01-22 Kobe Steel Ltd Method and device for preparing ladder sequence program
JP2005135383A (en) * 2003-09-05 2005-05-26 Fisher Rosemount Syst Inc State machine functional block equipped with user modifiable output configuration database
US8600524B2 (en) 2003-09-05 2013-12-03 Fisher-Rosemount Systems, Inc. State machine function block with a user modifiable state transition configuration database
JP2007207196A (en) * 2006-02-06 2007-08-16 Seiko Instruments Inc Programmable logic controller, information processor, control program, and table preparation program

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