JPS63292488A - Decoder circuit for semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent shortage of the pre-charge potential of each node, and to secure a normal operation of a circuit by pre-charging a node of a drain side of a cascaded FET group, and a prescribed node of other FET group. CONSTITUTION:When each address signal, and a control signal phi1 are 'L', a node N12, and N10 and N20 are pre-charged to 'H' through an FET Q7, and through Q112 and Q212, respectively. Accordingly, an output node N11 and N21 of inverters I1, I2 become 'L'. Subsequently, when an external signal becomes 'L', a DRAM becomes an active state. Thereafter, when the signal phi1 becomes 'H', the pre-charge of N12, and N10, N20 is suspended, and when an address signal becomes 'H', Q2-Q6 become ON and N12 and N10 become 'L', N11 becomes 'H', and N20 and N21 become 'H' and 'L', respectively. Next, when a word line driving signal becomes 'H', a pre-decoded word line driving signal becomes 'H', a word line also becomes 'H', and also, when an external signal becomes 'H', the DRUM becomes inactive.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a decoder circuit for a t-conductor memory constituted by MOS transistors, and particularly to a decoder circuit in which address lines are multiplexed.

[Conventional technology]

Semiconductor memories such as MO3DRAMs that are constructed using CMO3FETs (complementary metal oxide semiconductor field effect transistors) require a decoder circuit, and an example of this type of decoder circuit is as shown in Fig. 5. something is proposed. This was first invented by inventor Jun Honda and others, and the figure shows the configuration of a DRAM row decoder circuit. In this FIG. 5, the address signal A2
(A2)E and A3 (A3) ~A? (A
64 (2
6=64)), a decoder circuit for selecting one memory cell is not shown. FETQa to Q6 are FETs to which the address signal is input to the gate, and similarly, FETQ+a
and Q2a are FETs whose gates are input with address signals A2 and At. 0Usually, address signals AI and A
One of the signal lines of I (AI is an inverted signal of AI) is connected to the gate of the FET, but in the figure, the signal lines of addresses No. 43 As, A4, As, As, and At are connected to the FETs Qz and Qa, respectively. , Q4 , Qs , Qa
is connected to the gate of address signal A2. A case is shown in which lines 4a of A are connected to FETs Q+a and Q2a, respectively. Q is a P-channel FET to which the 11 control signal φ1 is inputted to the gate. FET Q2 and Q7
Both drains are connected to node N12.

Further, the sources of FETQ+a and Q28 are both connected to node NI2, and the drains of FETQ+a and Qza are connected to the output nodes N1° and N1° of the eide decoder circuit.
Connected to 2°. Inverter 1. It is composed of an ldP channel FET Q+e and an N channel FET Q++o, and its input terminal f is the output node N of the decoder circuit. The output terminal is connected to the node N. Inverter! 2 is P channel FETQ21
1 and N channel FETQ 210, whose input terminal is connected to the output node N2 of the decoder circuit.
The output terminal is connected to the node N21. And an inverter! 1 and ■2 output terminal 'fN
+ + and N21 are connected to word line driver circuit WD and WO2. In addition, each inverter I+ and ■2 is connected to a P-channel FET Q11+ and Q2 . It is equipped with l.

FIG. 2 is a diagram showing the configuration of word line driver circuits WD, WD2. The predecoded word line drive signals x0 to X shown in the figure are converted into address signals A by the predecoder of FIG. , eighty.

AI, AI pre-decoded signal and word line drive 1
It is A N D g1 of No. 3 φ8. The output side of the inverter II, 12 in FIG.
Through s3 FET Q J 146~Q j14
Connected to gate 3. Further, the signal lines of the predecoded word line drive signals x0 to x3 are connected to the FETs mentioned above.
Word lines WLJO to W via QJ14° to QJI43
Connected to LJ3.

Next, the operations of the decoder circuit of FIG. 5 and the word line driver circuit of FIG. 2 will be explained with reference to the waveform diagram of FIG. 6 before time t0.

External RAS number 3 (Ext, RAS) is at a high level, and the DRAM is in an inactive state.

At this time, each address signal A. * A O+ −'−−
+A, ,A, are at low level and control signal φ1 is also at low level, so node N1 is connected through FETQ7.
2 is precharged to a high level. Further, at this time, it is assumed that nodes NIO and N2° are also precharged to a high level (that is, precharging is performed normally).

Therefore, the output node N of the inverter 11 and the node N12 are at a low level. 4A Ex at time 〇
t, when RAS reaches the (g level), the DRAM becomes active.Next, at time Jill t+, the control signal φ1 becomes high level, and the precharge of the node N12 becomes 11-
be done. At time t2, among address No. 13, this decoder is selected at Ao.

At, A2. A3. A4. As As, As, and At become high level, FET Q2 to Q6 are turned on, and node N12 is discharged and becomes low level. At this time, since the address signal A2 is at high level, the node NI
O is also at a low level. Therefore, node N becomes high level. Further, nodes N2° and N21 are kept at high level and low level, respectively. Word line drive 18 at time t3
When the signal φ goes high, the predecoded word line drive signal KO goes high, and FETQJ
The word line WL+u becomes high level through □4°.

Next, when No. 44 Ext and RAS become high level at time ts, the DRAM enters the inactive state. Then time tll
word line drive signal φ8 and word line WL1. becomes low level, and at time tδ, address signal i Ao, At
, At , At becomes low level D to A3. At the same time, 1
111 (No. 3 φ2 becomes low level.

When the DRAM becomes inactive, the control fi signal φ1 goes low in order to precharge the decoder l path. Here, first, as shown by the solid line, the control signal φ凰 is at time t9.
Let's consider the case at the example level. At this time to
E T Q a to Qa and Qta+ Qza have already been turned off. Then, when control No. 12 φ1 becomes low level, FETQt is turned on and node NIJ is precharged to high level. At this time, FETQ
Since +n is off, node NIO remains low and therefore node N11 remains high. Therefore, in the next cycle, the external signal E
xt, when the DRAM becomes active even if RAS goes low, the predecoded word line drive No. 14 x0
Since one of the ~×3 signal lines becomes high level, the word line WLI is activated even if this decoder is not selected in the next cycle. ~One of the WL13 becomes high level and the DRAM malfunctions.

Next, the control signal φ1 is output at time t as shown by the broken line in FIG.
Consider the case where the level becomes low at 7. When the control signal φ1 becomes low level at time t7, FE'TQ is turned on and precharging of the node N1□ starts. However, at time t, the address signal is still at high level, so F E
T Q 2 to Q6 are on, and F E T Q
The size of 2 to Q is made smaller than that of FETQ7.
If the threshold of the inverter formed by E T Q t and Q2 to Q6 is not set high, the potential of node NI2 hardly increases. Then, at time t8, address signals Ao, At, A2 . A3-A7
When becomes low level, node FJ+
y is precharged to a high level. At this time, node N,. begins to be precharged toward a high level, but since FETQ+a is turned off, the precharging becomes insufficient, and the potential of the node Nil also becomes uncertain (it is unclear whether it is a high level or a low level). Therefore, as in the case described above, DRAM 6 (malfunctions).

Further, although the explanation will be omitted, when the control signal φ1 becomes low level at time ta, the same operation as when the control signal φ1 becomes low level at time t7 occurs, and the DRAM malfunctions.

FIG. 7 shows the structure of another r-conductor memory decoder circuit disclosed in Japanese Patent Application Laid-Open No. 61-120393. The configuration of this decoder circuit is almost the same as that of the decoder circuit shown in FIG. 5, but the difference is that in the circuit shown in FIG.
In the circuit of FIG. 7, a means for precharging the node N12 is not provided, whereas in the circuit of FIG. 7, a means for precharging the nodes NIO and N2° is provided. rFETQzx and Q21 are provided.

Next, the operation of the decoder circuit shown in FIG. 7 will be explained with reference to the waveform diagram shown in FIG. The operation from time clock 〇 to t4 is the 6th
The operation is similar to that shown in the figure. At time t5, the signals Ext, R
When AS goes high, DFLAM becomes inactive. Subsequently, at time t6, word line drive signals φ, l and word lines WL, are applied. becomes low level. Next, the address signals Ao, A+, At, and A3 to A7 become low level at the time clock 0, and FETs Q+a and Q2 to Q6 are turned off.

At the same time, control number 13 φ2 becomes low level.

When the DRAM becomes inactive, the control signal φ, which precharges the decoder circuit, becomes low level. here,
First, let us consider the case where the control signal φ1 becomes low level at the time clock 〇, as shown by the solid line.

Since FETQla and Q2-QB are already off at time t9, when control signal φ1 becomes low level at this time, node NIO is precharged to high level through FETQ+tt. Therefore, node N
i1 becomes a low level. At this time, FET Q +
, is off, the node N1. remains at a low level. Further, nodes N12 and N10 are each floating chambers with respect to the ground potential! t e l 2 and CIG, but since the node NIO is precharged to a high level, the capacity ML CIo is charged, and the node N12
remains at a low level, so the capacitor C1□ is not charged. Therefore, in the next cycle, the external signals Ext and RA are
When S becomes low level, this decoder is not selected, that is, when at least one of the signal lines of address signals A3 to A7 is low level and address signal A2 becomes high level. The charge stored in the floating capacitor Cto is distributed to the floating capacitors CIO and CI2.

Node N12 has FETQ2 and FETQ+a
It is a node connecting Q26 and Q26, and therefore the wiring length on the layout becomes long, so that the floating chamber itc+z becomes approximately the same as the floating capacitance Clo. Therefore, during charge distribution, the potential of the node NIO decreases, and the potential of the Nth node increases, even though one decoder is not selected, the word line WLI. The potential of one of ~WL, , I increases and the DRAM malfunctions.

Next, when the control signal φ becomes low level at time t7,
Precharging of nodes Nlo and N1□ is started through FETQ112, but FETQ+a and Q2~
Since Q6 is on, the potentials of nodes NIO and N17 hardly rise as in the previous example. Therefore, after FETQ+a and Q2 to Q6 are turned off at time t6,
Although node PJto is precharged to a high level through FET Q++a, the potential of node N12 does not rise, and therefore, the DRAM malfunctions as in the above case.

(Problems to be Solved by the Invention) Since the conventional T-conductor memory decoder circuit is configured as described above, nodes in the circuit that should be precharged may not be sufficiently precharged. However, there was a problem in that the potential of the word line rose even though the decoder was not selected, causing the DRAM to malfunction.

The present invention has been made to solve these problems, and aims to provide a decoder circuit for a semiconductor memory in which the nodes to be precharged in one circuit are reliably precharged and the operation is reliable. It has been the target.

(Means for Solving the Problems) A decoder circuit for a semiconductor memory according to the present invention includes a first node connected in cascade to a first node and into which an address signal or a signal obtained by predecoding address No. 13 is input to each gate. A group of FETs having either a source or a drain commonly connected in parallel to the first node and each gate receiving an address (f or predecoded 13) different from the address signal or the predecoded signal. a second FET group to which a signal is input, and a first precharging means for precharging the node of 0" and precharging each node to which the other of the 3FETs of the second FET group is connected. A second precharge means for charging is provided.

(Operation) In the semiconductor memory decoder circuit of the present invention, there is provided a means for precharging the first node on the drain side of the first group of cascade-connected FETs, and a means for precharging the first node on the drain side of the first group of cascade-connected FETs; Since the device is provided with means for precharging the other node of each FET of the second FET group, insufficient precharge potential of each node is prevented, and normal operation of the circuit is guaranteed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a diagram showing the configuration of a decoder circuit of a semiconductor memory according to the present invention. Here, a decoder circuit is shown that selects one out of 64 (2'=64) using 6-bit address signals A2 (A2) and A3 (A3) to A7CAt). In the figure, Q2 to Q6 are FETs whose gates are input with the above address signal or a predecoded signal of the address signal, which are cascade-connected between the first node NI2 and the ground terminal, and constitute the first FETnF. are doing. Similarly, FETs Q+a and Q28 are FETs whose gates receive an address signal A2 or A2 different from the address signal or the predecoded signal, and have one source in common connected to the first node N1.
2 in parallel to constitute a second FET F2.

Usually address No. 4R AJ and AJ (AJ is Aj
One of the signal lines of the inverted signal of
In the figure, the address signal As,
Aa, As, Aa, Aa signal lines are each FETQ
2, Q3, Q4. The case is shown in which the signal lines of signals A2 and A2 are connected to FETs Q+e and Q2a, respectively.

Ql is a P-channel FET having a gate connected to the signal line of the control signal φ1 and having a conductivity type different from the above-mentioned FETs, and is provided as a first precharging means for precharging the first node N12.

The drains of FETQ2 and Ql are commonly connected to node N12, and the sources of FETQIδ and Qta are both connected to node N12. The other drains of FET Ql and Qza are connected to output nodes N1° and N2°, and these nodes N,. The second precharge means for precharging +N1IO is FETQl of the same conductivity type as the first precharge means FETQt.
l□ and Q212 are provided. In addition, P-channel type FETQ19 and N-channel type FETQ
Inverter 1. is configured, its input terminal t is connected to the output node NIO, and its output terminal is connected to the node N. Similarly, P channel type FET
Qzs and N-channel Qx+o constitute an inverter 2, whose input terminal t is connected to the output node 2o, and whose output terminal is connected to the node N21. These inverters 11 and [2 output terminals NI In
N2+ are word line driver circuits WD and W, respectively.
It is connected to D. Further, the Nth node and the node N21 are FET Q + + + and Q which pull up the input terminals of inverter I and ■2, respectively.
It is connected to the gate of 211. As in a double series, nodes NIO and N2° are provided with P-channel type FETs Q112 and Q212 for precharging, the gates of which are connected to the signal line of control signal φ1.

The word line driver circuits WD, WD2 have a configuration as shown in 21X as in the conventional case. That is, the predecoded word line drive signals x0 to x3 in the figure are as follows:
By the predecoder shown in FIG. 3, the address signal Ao
, Ao, A+, a predecoded signal of A+ and a word line drive signal φ.

The output side of the inverter flu■2 in Fig. 1 is the AND signal of the inverter flu■2 in Fig. 1. connected to the gate. Further, the predecoded word line drive signals x0 to x3 are sent to the word line WL via the FETs Qj+4o to Qj+43. ~ Connected to WLj3.

Next, the operation of the decoder circuit having the above configuration will be explained with reference to the waveform diagram in FIG. .

At this time, each address signal AO, A. , -m-.

A? , A are at low level and control signal φ1 is also at low level, so node N12 is precharged to high level through FET Q7. Further, nodes NIO and N2° are also precharged to a high level through FET1$F and Q 2t a. Therefore,
Output nodes Nll and N21 of inverter 11.12
is at a low level. External signal Ext at time 〇,
When RAS goes low, the DRAM becomes active. Next, time 1. When the control signal φ becomes high level,
Node N12 and Node N. The precharge of rN20 is interrupted. At time t2, among the address signals, signals A, , A, , A are used to select the present decoder.
2 and A, ~A7 become high levels, F
E T Q 2 to Q6 are turned on and node N12 is discharged to a low level. At this time, since address signal A2 is at high level, node N,. is also discharged to a low level. Therefore, node N is at a high level. Further, nodes N2° and N2I are kept at a high level and a low level, respectively. When the word line drive signal φ8 becomes high level at time t3, the predecoded word line drive (2'; fr x
, goes high and the word WL, through FET Q1140. becomes high level. Next, at time 1S, the signal Ex
When t, RAS goes high, the DRAM enters the inactive state. Subsequently, at time t6, the word line drive No. 18 φ8 and the word lines WL, o become low level. And time t
Address signal Aa to Q.

A, , A, , A3 to A7 become low level. At the same time, control signal φ2 becomes low level.

When the DRAM becomes inactive, the control signal φ1 becomes low level in order to precharge the decoder circuit. Here, first, the control Q4 signal φ is set at the time 9 as shown by the solid line.
Consider the case where the level becomes low. At time t9, F E
T Q 2 to Q8 and Q, 8°Q2a are already turned off. Then, when the control signal φ1 becomes low level, F
E T Q t is turned on, and node NI2 is precharged to a high level. At this time, FETQ+a is off, but node N,. is precharged to a high level through FETQI12, and node NIl is precharged to the inverter! ,
Since the decoder is discharged to a low level through the decoder, the DRAM becomes active in the next cycle, and the DRAM operates normally even if this decoder is not selected.

Also, as shown by the broken line in FIG. 4, the control signal φ.

Even if becomes a low level at time t7, FE at time t♂
After TQ+a and Q2~Q6 turn off, node NIO
and N12 are both precharged high through FETQ+12 and Q7 so that DRA
M operates normally.

In addition, in the embodiment described above, the first FET1$F connected in cascade
, is an N-channel FET, and the second
The case has been described in which the FET group F2 is composed of N-channel FETs and the precharge FET is composed of P-channel FETs, but by appropriately selecting the applied potential (Vcc), other conductivity types can be used. It may also be configured with FETs.

Furthermore, although the above embodiment has been described with reference to the case where the decoder circuit is used as a row decoder, the same effect can be obtained when the decoder circuit is used as a column decoder. Furthermore, similar effects can be achieved not only when used in a DRAM of a decoder circuit, but also when used in other semiconductor memories.

〔Effect of the invention〕

As explained above, according to the present invention, the node on the drain side of the first cascade-connected FET group in the decoder circuit, the second FET group connected in parallel to this node, and the node Since the precharging means is provided at both the node and the node on the opposite side, the node is reliably precharged, and the decoder circuit can operate reliably.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing a decoder circuit of a semiconductor memory according to an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a word line driver circuit, and FIG. 3 is a generation of predecoded word line drive signals. 4 is a waveform diagram showing the operation of one embodiment; FIG. 5 is a configuration diagram showing a conventional semiconductor memory decoder circuit; FIG. 6 is a waveform diagram showing the operation;
FIG. 7 is a block diagram showing another conventional example, and FIG. 8 is a waveform diagram showing its operation. F,...First FET F2-...Second FET Q7...-FET (first precharge f stage) Q1
□21Q2+2・--FET (second precharge means) N12''...First node N+o, N.--Node 1,,l2--Inverter Note that the same reference numerals in the figure indicate the same or equivalent part.

Claims (7)

[Claims] (1) A first group of FETs that are cascade-connected to a first node and each gate receives an address signal or a predecoded signal of the address signal; a second group of FETs connected in parallel to the node and each gate receiving an address signal or a predecoded signal different from the address signal or the predecoded signal;
A semiconductor device comprising: a first precharge means for precharging a node; and a second precharge means for precharging each node to which the other of each FET of the second FET group is connected. Memory decoder circuit. (2) The first precharge means is connected to the first FE.
2. The decoder circuit for a semiconductor memory according to claim 1, wherein the decoder circuit is comprised of FETs of a conductivity type different from each of the FETs constituting the T group. (3) The semiconductor memory decoder according to claim 2, wherein the second precharge means is constituted by an EFT of the same conductivity type as the FET constituting the first precharge means. circuit. (4) Each FET constituting the first precharge means
4. The semiconductor memory decoder circuit according to claim 2, wherein the same signal is input to the gates of the FETs constituting the second precharge means. (5) A decoder circuit for a semiconductor memory according to any one of claims 1 to 4, wherein the first FET group has the other side grounded. (6) The address signal and the signal obtained by predecoding the address signal are at a potential that turns off each FET constituting the second FET group during a non-operating period of the semiconductor memory. A decoder circuit for a semiconductor memory according to any one of items 1 to 5. (7) The other of the source or drain of each FET constituting the second FET group is connected to an input terminal of an inverter, according to any one of claims 1 to 6. decoder circuit for semiconductor memory.