JPS6329124U - - Google Patents

Info

Publication number
JPS6329124U
JPS6329124U JP12282086U JP12282086U JPS6329124U JP S6329124 U JPS6329124 U JP S6329124U JP 12282086 U JP12282086 U JP 12282086U JP 12282086 U JP12282086 U JP 12282086U JP S6329124 U JPS6329124 U JP S6329124U
Authority
JP
Japan
Prior art keywords
voltage
ecd
coloring
circuit
terminal voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12282086U
Other languages
Japanese (ja)
Other versions
JPH0633450Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986122820U priority Critical patent/JPH0633450Y2/en
Publication of JPS6329124U publication Critical patent/JPS6329124U/ja
Application granted granted Critical
Publication of JPH0633450Y2 publication Critical patent/JPH0633450Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案ECD防眩ミラーの駆動回路図
、第2図はECDの構造の一例を示す断面図、第
3図はオルタネイトスイツチを選択したときの本
実施例防眩ミラーの駆動回路の動作を示すタイミ
ングチヤート、第4図は所定時間毎の着色端子電
圧と反射率との関係を示す図である。 1……ECD、10,20……サンプルホール
ド回路、10a,20a……オペアンプ、11〜
16……トランジスタ、17,27……比較器、
18,28……インバータ、19,29……NO
R回路、25……ECD駆動電圧源、24……ク
ロツク回路、31,32……オルタネイトスイツ
チ、C,C……コンデンサ、VR,VR
……ボリユーム。
Fig. 1 is a drive circuit diagram of the ECD anti-glare mirror of the present invention, Fig. 2 is a sectional view showing an example of the ECD structure, and Fig. 3 is a drive circuit diagram of the anti-glare mirror of the present invention when the alternate switch is selected. FIG. 4 is a timing chart showing the operation, and is a diagram showing the relationship between colored terminal voltage and reflectance at each predetermined time. 1... ECD, 10, 20... Sample hold circuit, 10a, 20a... Operational amplifier, 11...
16...Transistor, 17,27...Comparator,
18, 28... Inverter, 19, 29... NO
R circuit, 25...ECD drive voltage source, 24...Clock circuit, 31, 32...Alternate switch, C1 , C2 ...Capacitor, VR1 , VR2
...Volume.

Claims (1)

【実用新案登録請求の範囲】 1 エレクトロクロミツク素子(ECD)パネル
を用いた防眩ミラーの駆動回路であつて、該駆動
回路はECDの着色側端子電圧を検出する回路と
、ECDの端子電圧が基準電圧を超えると電圧印
加を止めて所定の着消色濃度に制御する回路とよ
りなることを特徴とするECD防眩ミラーの駆動
回路。 2 制御回路はクロツク回路で発生する周期でE
CD着消色側端子電圧のサンプリングとECD駆
動電圧とを交互に繰返し、着色側サンプルホール
ドの出力が設定された電圧を超えると駆動用の通
電を停止し、また着色側端子電圧を消色側サンプ
ルホールドし、その出力電圧が消色側の設定され
た電圧より低下したとき、通電を停止させる構成
となつている実用新案登録請求の範囲第1項記載
のECD防眩ミラーの駆動回路。
[Claims for Utility Model Registration] 1. A drive circuit for an anti-glare mirror using an electrochromic device (ECD) panel, which drive circuit includes a circuit that detects the colored side terminal voltage of the ECD, and a circuit that detects the terminal voltage of the ECD. 1. A drive circuit for an ECD anti-glare mirror, comprising a circuit that stops voltage application when the voltage exceeds a reference voltage and controls the coloring density to a predetermined coloring/decoloring density. 2 The control circuit is E with the period generated by the clock circuit.
Sampling of the CD coloring side terminal voltage and ECD driving voltage are repeated alternately, and when the output of the coloring side sample hold exceeds the set voltage, the driving current is stopped, and the coloring side terminal voltage is changed to the coloring side terminal voltage. A drive circuit for an ECD anti-glare mirror according to claim 1, which is configured to sample and hold and stop energization when the output voltage drops below a set voltage on the erasing side.
JP1986122820U 1986-08-11 1986-08-11 Driving circuit for ECD anti-glare mirror Expired - Lifetime JPH0633450Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986122820U JPH0633450Y2 (en) 1986-08-11 1986-08-11 Driving circuit for ECD anti-glare mirror

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986122820U JPH0633450Y2 (en) 1986-08-11 1986-08-11 Driving circuit for ECD anti-glare mirror

Publications (2)

Publication Number Publication Date
JPS6329124U true JPS6329124U (en) 1988-02-25
JPH0633450Y2 JPH0633450Y2 (en) 1994-08-31

Family

ID=31013369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986122820U Expired - Lifetime JPH0633450Y2 (en) 1986-08-11 1986-08-11 Driving circuit for ECD anti-glare mirror

Country Status (1)

Country Link
JP (1) JPH0633450Y2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6156638U (en) * 1984-09-17 1986-04-16

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6156638U (en) * 1984-09-17 1986-04-16

Also Published As

Publication number Publication date
JPH0633450Y2 (en) 1994-08-31

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