JPH032323U - - Google Patents
Info
- Publication number
- JPH032323U JPH032323U JP6040789U JP6040789U JPH032323U JP H032323 U JPH032323 U JP H032323U JP 6040789 U JP6040789 U JP 6040789U JP 6040789 U JP6040789 U JP 6040789U JP H032323 U JPH032323 U JP H032323U
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- frequency
- circuit
- clock
- crystal module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Liquid Crystal Display Device Control (AREA)
Description
第１図は本考案の原理ブロツク図、第２図は本
考案の一実施例の構成図、第３図は液晶表示装置
の構成図、第４図は液晶駆動用電源回路の構成図
、第５図は従来の構成図、第６図は閾値電圧の周
波数特性を示す図である。
１……ドライバ、２……コントローラ、３……
分周回路。
Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of a liquid crystal display device, Fig. 4 is a block diagram of a liquid crystal driving power supply circuit, and Fig. 4 is a block diagram of a liquid crystal display device. FIG. 5 is a conventional configuration diagram, and FIG. 6 is a diagram showing frequency characteristics of threshold voltage. 1...driver, 2...controller, 3...
Frequency divider circuit.
Claims (1)
を分周して、液晶モジユールを駆動するドライバ
回路１に加える交流化信号Ｍを生成する分周回路
３を設け、 該分周回路３の分周比はドライバ回路１が駆動
する液晶モジユールの閾値の変化が少ないクロツ
ク周波数の範囲に設定してなることを特徴とする
液晶表示装置用駆動回路。[Claims for Utility Model Registration] Clock signal CL2 generated by controller 2
A frequency divider circuit 3 is provided to generate an alternating current signal M to be applied to the driver circuit 1 that drives the liquid crystal module, and the frequency division ratio of the frequency divider circuit 3 is equal to the threshold value of the liquid crystal module driven by the driver circuit 1. 1. A drive circuit for a liquid crystal display device, characterized in that the clock frequency is set within a range in which there is little change in clock frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6040789U JPH032323U (en) | 1989-05-26 | 1989-05-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6040789U JPH032323U (en) | 1989-05-26 | 1989-05-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH032323U true JPH032323U (en) | 1991-01-10 |
Family
ID=31587743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6040789U Pending JPH032323U (en) | 1989-05-26 | 1989-05-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH032323U (en) |
-
1989
- 1989-05-26 JP JP6040789U patent/JPH032323U/ja active Pending