JPS63290166A - Dc-dc converter - Google Patents

Abstract

PURPOSE:To lower application voltage of a switching element, by connecting a series circuit of a capacitor and a diode in parallel with a first switching element, then connecting a second switching element in parallel with the diode. CONSTITUTION:A second switching element, i.e. a N.MOS.FET 3 is connected through the primary winding N1 of a transformer 2 with a DC power source 1. A series circuit of a capacitor 12 and a diode 13 is connected in parallel with the element 3, while a second switching element, i.e. a P.MOS.FET14, is connected in parallel with the diode 13. Furthermore, PWM control circuit 10 provides signals for opening/closing both FETs 3, 14 alternately, and a starting circuit 11 provides signals for opening/closing both FETs 3, 14 alternately only when the power source is thrown in. Consequently, the transformer 2 can be reset by means of the capacitor 12 and the second FET14 and application voltage can be lowered for a small duty factor.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a DC-D device applied to switching stabilized power supplies, etc.
The present invention relates to a C2 inverter, and particularly relates to a circuit that reduces the voltage applied to the switching element during the open period of the switching element when the duty period of the switching element is set to be large.

[Conventional technology]

Figure 4 is a circuit diagram showing a conventional example, which is described in Susumu Hakusho's book ``Switching Regulator Design Method and How to Use Power Devices, Published by Seibundo Shinkosha''. Widely used for power supplies, etc. In FIG. 4, 1 is a DC power source obtained by rectifying a commercial AC power source, etc.; 2 is a DC power source 1 whose positive terminal is connected to the connection point of its primary winding N1 and reset winding NR; The other end is a switching N-channel power field effect transistor (hereinafter N, MO
S , called FET) 3 is connected to the drain of the winding N
The other end of R is a transformer connected to the cathode of diode 4 (the polarity of the a-line of the transformer is indicated by the mark), N,
The sources of the MOS and FET 3 and the anode of the diode 4 are connected to the negative electrode of the DC power supply 1. Both ends of the secondary winding N2 of the transformer 2 are connected to the anodes of diodes 5 and 6 with the polarities shown.

A choke coil 7 has one end connected to the connection point of the cathodes of the diodes 5 and 6, and the other end is connected to one end of the capacitor 8. Further, the other end of the capacitor 8 is connected to the anode of the diode 6.

9 is a load connected to both ends of the capacitor 8, and the voltage across the load 9 is controlled by a pulse width feedback control circuit (hereinafter referred to as PWM control circuit) to keep this voltage constant.
It is input to 10 input terminals. PWM control circuit 1 electrically isolated from the input side using a photocoupler, isolation transformer, etc.
The output terminal of 0 is connected to the gate and source of N, MOS, and FET3.

Reference numeral 11 denotes a starting circuit that drives the gates of N2, MOS2, and FET3 with a pulse voltage only when the power is turned on.

In FIG. 4, when the DC power source 1 is turned on, a voltage pulse is sent from the startup circuit 11 to drive the gates of N, MOS, and FET 3, and N, MOS.

FET3 is closed and the voltage of DC power supply l is applied to winding N1 of transformer 2. The winding N2 of the transformer 2 is fully connected to a voltage corresponding to the turns ratio with the winding Nl, is slipped by P° through the choke coil 7 and the capacitor 8, and is supplied to the load 9. The voltage across the load 9 is compared with a reference voltage in a PWM control circuit 10, and when the voltages match, N, MOS, and FET 3 are opened.

When N, MOS, and FET3 are opened, the excitation current of the transformer 2 flows through the path of the non-marked terminal of the winding NR, the DC power supply 1, the diode 4, and the -marked terminal of the winding NR, and the transformer 2 is reset. At this time, a voltage is generated in the secondary winding N2 with a negative polarity, but it is blocked by the diode 5, so 7
E style is not good. In this way, when the N, MOS, and FET are opened and the voltage across the load 9 becomes lower than 1 (quasi-voltage), the PWMF is activated and the N, MOS, and FE are connected again by the control circuit IO.
The T is closed and the operation of sailing speed is repeated.

FIG. 5(a) shows N and MOS at this time.

The voltage between the drain and source of the FET, and (b) is 1
The voltage waveform of the next winding N1 is shown.

Transformer 2 when N, MOS, and FET are closed and opened
Since the changes in the magnetic flux of the magnetic cores are equal, the following equation (1) holds true.

However, here, E: Voltage of DC power supply 1 T = toN+ tnFF (see Figure 5) (1, - Number of turns of Q wire N1 rz+: 8 loss at a wire N1 Transforming equation (1), we get the following ( 2) Equation 41) is given.

Also, N, MOS, and FET3 are drains when open.

The following equation (3) holds true for the source-to-source voltage.

(1) Here, V ns is the voltage between the drain and source of N, MOS, and FET.

Historically, the following equation (4) holds true for the voltage across the load 9.

However, here, vo: Voltage of load 9 n2 Number of turns of winding N2 of Nidorance 2 From equation (4), output voltage V. In order to keep constant the DC power supply lO, when the main voltage is small, N, MOS.

Increase the closing period of FET3, and conversely, when E is large, D
It turns out that it is better to make it smaller. By the way, according to formula (2), in order to increase D, it is necessary to decrease nR.
In this case, N from equation (3).

The voltage applied between the drain and source of the MOS and FET 3 increases, and an element with high breakdown voltage is required.

That is, according to the conventional example, in order to cope with a wide variation range of the voltage E of the DC power source I, the NMOS is used.

By increasing the ratio (n, /nR) of the number of turns 01 and n□, which can increase the duty ratio of FET3, as is clear from equation (3), the duty ratio will increase even when operating at a value smaller than the duty ratio. Regardless of the comparison, N, MOS,
A large voltage is applied between the train and source of the FET 3, which not only necessitates a high-voltage element but also has the disadvantage of increased switching loss.

Furthermore, it is cumbersome that it is necessary to assume the maximum value of the duty ratio expected in "Use 2" and to determine the turns ratio of the primary winding N of transformer 2 and the reset winding NR each time. was there.

[The problem that the invention attempts to solve]

The present invention was made in view of such drawbacks, and
To provide a circuit that operates stably over a wide duty ratio range even without a reset winding, and in addition, the voltage applied to the switching element is small when used at a low duty ratio, and increases only when the duty ratio is large. It is.

For this reason, in the present invention, instead of resetting the transformer using a series circuit of a reset winding and a diode as in the conventional example, the first switching element is N, MOS, FET.
In parallel, a new series circuit of a capacitor and a diode is connected, and a second switching element f, P, MOS, FET, is connected in parallel with this diode for resetting.

[Effect]

With this configuration of the present invention, the transformer can be reset by the circuit including the capacitor and the second switching element, and the voltage applied to the switching element can be reduced when the duty ratio is small.

〔Example〕

FIG. 11 shows a circuit LS1 showing one embodiment of the present invention,
Components that are the same as or corresponding to those in FIG. 4 are given the same reference numerals.

In FIG. 1, 3 is the first switching element N
, MOS, and FET, and are connected in series with the primary winding Nl of the transformer 2 and connected to the DC power supply l. A series circuit of a capacitor 12 and a diode 13 is connected in parallel with the first switching element 3, and a second switching element P, MOS, PT14 is connected in parallel with the diode 13.

It should be noted that the capacitor 12 has a relatively large capacity so that the terminal voltage does not fluctuate too much.

P W M i'111J control circuit 10 small circuit 10MOS
.

The signals that alternately open and close FET3, P, MOS, and FET14 are the gates of each MOS and FET.

Supplied between sources.

The starting circuit 11 is N and MOS only when the power is turned on.

Outputs a signal that alternately opens and closes FET3, P, MOS, and FET14.

FIG. 2 shows voltage waveforms at various parts in the embodiment shown in FIG. 1, and (a) shows N, MOS.

The voltage between the gate and source of FET3, (b) is P, MO
S shows the gate and source 1m voltage of FET14.

(c) is the voltage between the drain and source of N, MOS, FET 3, (d) is the voltage across the capacitor 12, and
(e) shows the voltage between the drain and source of P, MOS, FET14 (7).

In Figures 1 and 2, N1MO5°FET3 and P
, MOS, and FET 14 are alternately opened and closed, changes in the magnetic flux of the magnetic core of the transformer 2 will be explained.

First, N, MOS, FET3 is closed, P, MOS.

The amount of change ΔΦ1 in magnetic flux when FET 14 is open is expressed by the following formula (5
)become.

Δ Φ l = E 11 D ・ T/ n 1
(5) Conversely, N, MOS,
FET3 is open, P, MOS.

The amount of change ΔΦ2 in magnetic flux when FET 14 is closed is expressed by the following formula (6
)become.

ΔΦ2= −(VCl2−E) ・(1−D) ・T/
n+ (6) Here, nl is the number of turns of the primary winding N1, n2 is the number of turns of the secondary a M N 2, and VCl2 is the voltage of the capacitor 12 expressed by the following equation (7).

E VC+2=　　　　　　　　　　　(7)-D Substituting equation (7) into equation (6) yields equation (8).

ΔΦ2 = −E−DT−T/n,
(8) From equations (5) and (8), it can be seen that ΔΦ1 and ΔΦ2 are equal in size or have opposite signs.

That is, according to the actual tJh example shown in FIG. 1, it can be seen that the transformer 2 is always reset and operates stably, regardless of the duty ratio of the switching elements 3 and 14.

Also, when P, MOS, and FET14 are closed, N, MOS
, the 'lπ pressure applied between the drain and source of FET3 is equal to the voltage of capacitor 2, and conversely, the voltage of P, MOS, FET3 is
ET14 open, N, MOS.

The drain-source voltage when FET3 is closed is also equal to the voltage of capacitor C12, and both are expressed by equation (7).

That is, the voltage applied to the switching transistors 3 and 14 is proportional to the voltage E of the DC voltage l and inversely proportional to (1-D). In addition, unlike the conventional example, there is no need to provide a winding NR corresponding to the maximum duty ratio in the transformer 2, and when operating at a small duty ratio, the voltage applied to the switching element is automatically reduced. . As a result, if a design is made so that the duty ratio can be increased as in the conventional example, a high voltage will be applied to the switching element even when it is operated at a small duty ratio, requiring a high withstand voltage element and increasing switching loss. Defects can be improved.

In the embodiment of FIG. 1, switching elements 3 and 14
can be replaced by other switching elements such as bipolar transistors. Further, the diode 13 connected in parallel with the switching element 14 can of course be omitted if, for example, a switching element with a built-in diode is used. Furthermore, it is clear that normal operation will occur even if the connection order of the parallel circuit of the capacitor 12, the switching element 14, and the diode 13 is changed.

FIG. 3 shows a circuit showing another embodiment of the present invention, which differs from the circuit shown in FIG. 1 in that a choke coil is connected in series to the second switching element 14.

The operation of the circuit shown in FIG. 3 is similar to that shown in FIG. 1, but the choke coil 15 is inserted.

MOS, when FET14 is closed, N, MOS.

The voltage applied between the drain and source of FET 3 is equal to the voltage of capacitor 12 minus the voltage applied to choke coil 15, and its maximum value does not exceed the value of equation (7) above.

Conversely, P, MOS, and FET14 are open and N.

MOS, P when FET3 is closed, MOS.

The drain-source voltage of FET l4 is also less than the value of equation (7).

In the embodiment of FIG. 3, switching elements 3 and 14
can be replaced by other switching elements such as bipolar transistors. In addition, capacitor 12 and diode 13
It is clear that the series circuit of the choke coil 15 and the switching element 14 will operate normally even if the connection order of the respective elements is changed.

〔Effect of the invention〕

According to the present invention, as described above, there is no need for a reset winding in the transformer, so there is no need to worry about deciding the turns ratio between the primary winding and the reset winding, and the withstand voltage of the switching element is low, resulting in switching loss. can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram showing one embodiment of the present invention.
A voltage waveform diagram of each part in the circuit shown in the figure, (a) is N, M
OS, FET3 gate. The source-to-source voltage is shown in (b) for P, MOS. FET l 4 (7) The gate-to-source pressure is (C
) is the voltage between the drain and source of N, MOS, and FET,
(d) is the voltage across the capacitor 12, (e) is P,
M □o S, F E T 14 drain. Indicates source voltage. FIG. 3 is a circuit diagram showing another embodiment of the present invention, FIG. 4 is a circuit diagram of a conventional example, and FIG. 5 is a voltage waveform diagram in the circuit of FIG. 4. (a) is an NMOS. (b) shows the voltage between the drain and source of FET3, and the voltage of the primary winding N1. In the figure, l is a DC power supply, 2 is a transformer, Nl is its primary winding, N2 is a secondary winding, 3 is a first switching element, 1
4 is the second switching element, 5, 6, 13 is a diode, 7 is a Chirok coil, 8 is a capacitor, IO is PW
This is an M control circuit. Note that the same reference numerals indicate the same or similar parts.

Claims (1)

[Claims] A series circuit of a primary winding of a transformer and a first switching element connected to a DC power supply, a series circuit of a capacitor and a diode connected in parallel to the first switching element, and a series circuit of a capacitor and a diode connected in parallel to the diode. a second switching element, a rectifier circuit connected to a secondary winding of the transformer, and a control circuit that alternately opens and closes the first switching element and the second switching element. DC-DC converter.