JPS6328535B2 - - Google Patents

Info

Publication number
JPS6328535B2
JPS6328535B2 JP3617183A JP3617183A JPS6328535B2 JP S6328535 B2 JPS6328535 B2 JP S6328535B2 JP 3617183 A JP3617183 A JP 3617183A JP 3617183 A JP3617183 A JP 3617183A JP S6328535 B2 JPS6328535 B2 JP S6328535B2
Authority
JP
Japan
Prior art keywords
logic
transmitting
power supply
transformer
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3617183A
Other languages
Japanese (ja)
Other versions
JPS59161938A (en
Inventor
Shunichi Nagamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58036171A priority Critical patent/JPS59161938A/en
Publication of JPS59161938A publication Critical patent/JPS59161938A/en
Publication of JPS6328535B2 publication Critical patent/JPS6328535B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B3/00Line transmission systems
    • H04B3/54Systems for transmission via power distribution lines
    • H04B3/542Systems for transmission via power distribution lines the information being in digital form
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B2203/00Indexing scheme relating to line transmission systems
    • H04B2203/54Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5404Methods of transmitting or receiving signals via power distribution lines
    • H04B2203/5416Methods of transmitting or receiving signals via power distribution lines by adding signals to the wave form of the power source
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B2203/00Indexing scheme relating to line transmission systems
    • H04B2203/54Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5462Systems for power line communications
    • H04B2203/5483Systems for power line communications using coupling circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は送受信装置に係り、特に情報信号を電
源供給線路に重畳させて伝送するに好適な送受信
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a transmitting/receiving device, and more particularly to a transmitting/receiving device suitable for transmitting an information signal by superimposing it on a power supply line.

従来例の構成とその問題点 本発明に最も近い従来例としては次のものがあ
る。これは送信および受信装置間を2本の回線で
結び、一方から他方への電源を供給するととも
に、その上に信号を重畳して情報を伝達するもの
である。電源と回線は信号漏洩阻止用素子(低減
濾波器)を介して接続されており、又、信号の重
畳、分離は、回線に並列に接続された同調トラン
スを介して行なわれ、周波数選択性を持たせた回
路構成となつている。この同調トランスは送信用
と受信用でそれぞれ別々に設けられている。
Configurations of conventional examples and their problems The following conventional examples are closest to the present invention. This connects the transmitter and receiver with two lines, supplies power from one to the other, and superimposes a signal on the line to transmit information. The power supply and line are connected via a signal leak prevention element (reduction filter), and signal superimposition and separation are performed via a tuning transformer connected in parallel to the line, achieving frequency selectivity. It has a circuit configuration. This tuning transformer is provided separately for transmission and reception.

このような構成における問題点としては次の通
りである。すなわち、送信動作において、論理
“1”の状態は、同調トランスを搬送周波数で駆
動して、回線に搬送波を重畳させ、論理“0”の
状態は同調トランスのドライブを停止することに
よる、いわゆるトーンバースト方式によつて構成
するものであるが、信号が論理“1”から論理
“0”に切換わつた直後には、同調トランスおよ
びそれに並列に接続される同調コンデンサで構成
される並列共振回路に、その前の論理“1”の状
態のときに蓄積された振動エネルギー(1/2CV2
+1/2Li2)が残つており、第4図bに示すよう
に、論理“0”の時間領域になつてもしばらくの
間(時間ta)は共振回路の振動が継続するという
現象を生ずる。
Problems with such a configuration are as follows. That is, in the transmission operation, a logic "1" state drives the tuning transformer at the carrier frequency and superimposes a carrier wave on the line, and a logic "0" state causes the so-called tone by stopping the tuning transformer drive. It is constructed using a burst method, but immediately after the signal switches from logic "1" to logic "0", a parallel resonant circuit consisting of a tuning transformer and a tuning capacitor connected in parallel with it is activated. , the vibrational energy (1/2CV 2
+1/2Li 2 ) remains, and as shown in FIG. 4b, a phenomenon occurs in which the vibration of the resonant circuit continues for a while (time ta) even in the time domain of logic "0".

このことは受信側において、信号を復調したと
き、第4図cに示すように、論理“1”の状態
が、論理“0”の時間領域にまで侵入してくるこ
とになり、時間tbが大きくなると情報信号の受信
が不確実になることを意味するものである。尚、
第4図aが元の情報である。
This means that when the signal is demodulated on the receiving side, the logic "1" state will invade the logic "0" time domain, as shown in Figure 4c, and the time tb will be A larger value means that the reception of the information signal becomes uncertain. still,
Figure 4a is the original information.

発明の目的 本発明は、上記欠点を解消し、簡単な構成で確
実に論理“1”と論理“0”を伝達することがで
きる送受信装置を提供することを目的とするもの
である。
OBJECTS OF THE INVENTION It is an object of the present invention to provide a transmitting/receiving device capable of reliably transmitting logic "1" and logic "0" with a simple configuration and eliminating the above-mentioned drawbacks.

発明の構成 本発明は少なくとも1対の送受信装置の一方か
ら他方へ電源供給するための電源供給線路に同調
トランスの2次巻線を接続し、上記電源供給線路
上に前記同調トランスの1次巻線から供給される
情報信号を重畳させるものであり、特に、前記同
調トランスの1次巻線と同調用コンデンサで形成
された並列共振回路に並列に、前記並列共振回路
を短絡するためのスイツチ手段を設け、情報信号
が論理“1”から論理“0”に変わつた時該スイ
ツチ手段をオンして前記並列共振回路に蓄積され
ている振動エネルギーを瞬時に消費させ、論理
“1”と論理“0”の区切りを正確に伝送するも
のである。
Structure of the Invention The present invention connects a secondary winding of a tuned transformer to a power supply line for supplying power from one of at least one pair of transmitting/receiving devices to the other, and connects the secondary winding of the tuned transformer to the power supply line. a switch means for short-circuiting the parallel resonant circuit formed by the primary winding of the tuning transformer and the tuning capacitor; is provided, and when the information signal changes from logic "1" to logic "0", the switch means is turned on to instantaneously consume the vibration energy stored in the parallel resonant circuit, and the logic "1" and logic "0" are changed. This is to accurately transmit the 0'' delimiter.

実施例の説明 本発明の一実施例を第1図A,Bに示す。第1
図Aは商用電源Ac100Vに接続される等により、
電源供給能力を有し、他の送受信装置へ電源を供
給する側の送受信装置を、又、第1図Bは逆に電
源を受給する側の送受信装置を示すものである。
DESCRIPTION OF THE EMBODIMENTS An embodiment of the present invention is shown in FIGS. 1A and 1B. 1st
Figure A is connected to a commercial power supply AC100V, etc.
FIG. 1B shows a transmitting/receiving device that has power supply capability and supplies power to other transmitting/receiving devices, and conversely, FIG. 1B shows a transmitting/receiving device that receives power.

第1図Aにおいて、1は電源供給側の送受信装
置全体の構成を示し、端子2a,2bを介して、
商用電源Ac100V接続される。3は電源回路Iで
あり、Ac100V入力を電子回路動作に必要な、例
えば+12V、+5Vなどのような直流電圧に変換し
たり、電源受子側の送受信装置へ伝送するための
電源VBに変換するものである。
In FIG. 1A, 1 indicates the entire configuration of the transmitting/receiving device on the power supply side, and through terminals 2a and 2b,
Connected to commercial power supply AC100V. 3 is the power supply circuit I, which converts the AC100V input into the DC voltage necessary for electronic circuit operation, such as +12V, +5V, etc., or converts it into a power supply VB for transmission to the transmitting/receiving device on the power receiver side. It is something to do.

端子4a,4bは回線5a,5bを接続して、
他の送受信装置への電源供給および情報信号を送
受信するためのものであり、直列に挿入されたト
ランス6の2次巻線6aを介して前記電源VB
両端7a,7bに接続される。電源VBの両端7
a,7bに並列に接続されたコンデンサ8は、前
記トランス6とともに、電源VBと情報信号とを
分離するためのものである。
Terminals 4a and 4b connect lines 5a and 5b,
It is used to supply power to other transmitting/receiving devices and to transmit/receive information signals, and is connected to both ends 7a, 7b of the power source VB via a secondary winding 6a of a transformer 6 inserted in series. Both ends of power supply V B 7
A capacitor 8 connected in parallel to a and 7b is used together with the transformer 6 to separate the power supply VB and the information signal.

すなわち、コンデンサ8の容量c、トランス6
の2次巻線側から見た等価インダクタンスLを適
当な値に設定することにより周波数fに対するそ
れぞれのインピーダンスzを、第2図のような特
性にすることができる。今、電源VBの周波数を
f1、情報信号の周波数をf2とすると、周波数f1
おいてZC≫ZL、周波数f2においてはZL≫ZCとな
り、コンデンサ8の両端には、ほとんど電源VB
の成分だけが、又、トランス6の2次巻線6bの
両端には、ほとんど情報信号成分だけが現われる
という良く知れた電気回路の原理によつて電源
VBと情報信号を分離するものである。
That is, the capacitance c of the capacitor 8, the transformer 6
By setting the equivalent inductance L seen from the secondary winding side of the coil to an appropriate value, the respective impedances z with respect to the frequency f can be made to have the characteristics as shown in FIG. Now, the frequency of power supply V B is
f 1 and the frequency of the information signal is f 2 , Z C ≫ Z L at frequency f 1 and Z L ≫ Z C at frequency f 2 .
According to the well-known electric circuit principle, only the information signal component appears at both ends of the secondary winding 6b of the transformer 6.
This separates VB from the information signal.

更に、トランス6の1次巻線6aと並列に同調
用コンデンサ9を接続し、並列共振回路10aを
有する同調用トランス10構成とすることによつ
て送受信を行なう情報信号に周波数選択特性を持
たせることができるので、回線5a,5bを通し
て外部へ放射される電磁波ノイズに対する配慮を
共振周波数だけに対して行なえばよいし、又、逆
に外部から侵入してくる電磁波ノイズに対して
も、同じ理由で共振周波数以外の周波数ノイズに
対する排除性が大変強くなり、情報伝送誤りを少
なくできるなどの長所があるが、前述の従来例の
構成とその問題点の項で説明したように、並列共
振回路10aに蓄積されていた振動エネルギーに
よつて、情報信号の論理“1”から論理“0”へ
の移行の時、データの区切りが不正確になるとい
う問題を有するものである。
Further, by connecting a tuning capacitor 9 in parallel with the primary winding 6a of the transformer 6 to configure a tuning transformer 10 having a parallel resonant circuit 10a, information signals to be transmitted and received have frequency selection characteristics. Therefore, the electromagnetic noise radiated to the outside through the lines 5a and 5b need only be considered at the resonant frequency, and conversely, the same reason can be applied to the electromagnetic noise that enters from the outside. The parallel resonant circuit 10a has the advantage that it has a very strong ability to eliminate noise at frequencies other than the resonant frequency, and can reduce information transmission errors. There is a problem in that the vibrational energy stored in the information signal causes inaccurate data delimitation when the information signal transitions from logic "1" to logic "0".

そこで、本発明では並列共振回路10aに並列
にスイツチ手段11を接続し、情報信号が論理
“1”から論理“0”に変化したとき、該スイツ
チ手段11によつて並列共振回路10aを短絡
し、蓄積されている振動エネルギーを瞬時に消滅
させ、論理“1”と論理“0”の区切りを正確に
して情報信号を伝送しようとするものである。ス
イツチ手段11において、11aは、FETトラ
ンジスタであり、直接並列共振回路10aを短絡
する。11bは、電流制限抵抗で、FETトラン
ジスタ11aと直列に接続する。11cはFET
トランジスタ11aのドライブ回路であり、送受
信論理回路15のOUT端子から出力される
CLAMP信号によつて、FETトランジスタ11
aをオン・オフさせる。
Therefore, in the present invention, a switch means 11 is connected in parallel to the parallel resonant circuit 10a, and when the information signal changes from logic "1" to logic "0", the switch means 11 short-circuits the parallel resonant circuit 10a. , the purpose is to instantly eliminate the accumulated vibrational energy, accurately delimit logic "1" and logic "0", and transmit information signals. In the switch means 11, 11a is a FET transistor, which directly short-circuits the parallel resonant circuit 10a. 11b is a current limiting resistor connected in series with the FET transistor 11a. 11c is FET
This is a drive circuit for the transistor 11a, and is output from the OUT terminal of the transmission/reception logic circuit 15.
By the CLAMP signal, FET transistor 11
Turn a on and off.

又、トランス6の1次巻線6aの両端には変調
回路12および復調回路13を、中間タツプには
+5Vを接続する。
Further, a modulation circuit 12 and a demodulation circuit 13 are connected to both ends of the primary winding 6a of the transformer 6, and +5V is connected to the intermediate tap.

変調回路12には、送受信論理回路14の
OUT1端子から出力される情報信号DATAが入
力され、CMOSのNANDゲート等で構成した搬
送波発振部12aで変調した後、トランジスタ等
で構成した駆動部12bによつて同調トランス1
0をドライブするものである。
The modulation circuit 12 includes a transmission/reception logic circuit 14.
The information signal DATA output from the OUT1 terminal is input, and after being modulated by a carrier wave oscillating section 12a configured with a CMOS NAND gate, etc., it is modulated by a tuning transformer 1 by a driving section 12b configured with a transistor, etc.
It drives 0.

同調トランス10で周波数選択された情報信号
は、トランス6の2次巻線6bを介して回線5
a,5bに送出され、他の送受信装置16に伝送
される。
The information signal frequency-selected by the tuned transformer 10 is passed through the line 5 through the secondary winding 6b of the transformer 6.
a, 5b, and transmitted to other transmitting/receiving devices 16.

逆に、回線5a,5bを経て他の送受信装置か
ら伝送されてきた情報信号は、トランス6の2次
巻線の両端に発生し、並列共振回路10aと共振
する周波数成分を有する情報信号のみが1次巻線
6a側に現われる。この情報信号は、復調回路1
3の入力処理部13aでインピーダンス変換、増
幅などの前処理を行つた後、検波部13bでAM
検波される。次に波形整形部13cでデイジタル
パルスに整形された後、送受信論理回路14の
IN端子から入力される。
Conversely, the information signals transmitted from other transmitting/receiving devices via the lines 5a and 5b are generated at both ends of the secondary winding of the transformer 6, and only the information signals having frequency components that resonate with the parallel resonant circuit 10a are transmitted. It appears on the primary winding 6a side. This information signal is transmitted to the demodulation circuit 1
After performing pre-processing such as impedance conversion and amplification in the input processing section 13a of 3, the detection section 13b performs AM
Detected. Next, after being shaped into a digital pulse by the waveform shaping section 13c, the transmitting/receiving logic circuit 14
Input from the IN terminal.

このように情報信号の重畳・分離および送受信
動作を唯1つのトランス6を用いて行なうシンプ
ルな構成としている。
In this way, the configuration is simple in that only one transformer 6 is used to superimpose/separate information signals and perform transmission/reception operations.

15はLED、キー、スイツチ、リレー、ボリ
ユーム、センサー類などから成る入出力回路であ
り、その入出力情報は送受信論理回路14を介し
て、遠く離れた他の送受信論理回路16との間で
相互に交信されるものである。尚、送受信論理回
路14にマイクロコンピユータを利用すれば好適
である。
Reference numeral 15 denotes an input/output circuit consisting of LEDs, keys, switches, relays, volumes, sensors, etc., and the input/output information is exchanged with other far away transmitting/receiving logic circuits 16 via the transmitting/receiving logic circuit 14. This is what is communicated to. Note that it is preferable to use a microcomputer for the transmission/reception logic circuit 14.

次に第1図Bにおいて、16は電源受給側の送
受信装置全体の構成を示す。端子17a,17b
には、回線5a,5bが接続され、伝送されてき
た電源の入力および情報信号の入出力が行なわれ
る。18はダイオードブリツジであり、伝送され
てきた電源が直流あるいは交流のいずれの場合に
も、端子17a,17bと回線5a,5bの結線
を無極性化し、電源回路19に、極性の定まつ
た直流電圧VCを供給するものである。
Next, in FIG. 1B, reference numeral 16 indicates the overall configuration of the transmitting/receiving device on the power receiving side. Terminals 17a, 17b
Lines 5a and 5b are connected to the terminals, and transmitted power and information signals are input and output. Reference numeral 18 denotes a diode bridge, which makes the connections between terminals 17a and 17b and lines 5a and 5b non-polarized and provides fixed polarity to the power supply circuit 19, regardless of whether the transmitted power is direct current or alternating current. It supplies DC voltage V C.

電源と情報信号の分離の方法は第1図Aで説明
した通りであり、コンデンサ8の両端に現われる
電源VCを電源回路19によつて、例えば+
12V、+5Vなどの安定化された直流電圧に変換
し、電源受給側の送受信装置16全体を動作させ
るものである。
The method of separating the power supply and information signal is as explained in FIG. 1A, and the power supply V C appearing across the capacitor 8 is connected to
It converts it into a stabilized DC voltage such as 12V or +5V, and operates the entire transmitting/receiving device 16 on the power receiving side.

他の回路ブロツクについては、第1図Aにおい
て説明した内容と全く同じであるので省略する。
尚、同一機能ブロツクについては、同一番号を用
いている。
Since the other circuit blocks are exactly the same as those explained in FIG. 1A, their explanation will be omitted.
Note that the same numbers are used for the same functional blocks.

以上のような構成によつて、第3図のような送
受信動作が得られる。すなわち、第3図aは、一
方の送受信装置(1又は16)の送受信論理回路
14から出力された情報信号DATA、同図bは
同じく、スイツチ手段11を動作させるための
CLAMP信号である。このようなDATA信号と
CLAMP信号のタイミングによつて、回線5a,
5b上には、同図cのように、論理“1”と論理
“0”の区切りが正確な情報信号を送出すること
ができる。このような情報信号を他方の送受信装
置(16又は1)で復調したものが同図dであ
り、論理“1”と論理“0”が忠実に伝送されて
いる。尚、実施例の回路では復調回路13の出力
信号は、同図dを反転したものである。
With the above configuration, the transmission and reception operations as shown in FIG. 3 can be obtained. That is, FIG. 3a shows the information signal DATA output from the transmitting/receiving logic circuit 14 of one of the transmitting/receiving devices (1 or 16), and FIG.
It is a CLAMP signal. With DATA signal like this
Depending on the timing of the CLAMP signal, lines 5a,
5b, it is possible to send out an information signal with accurate delimitation between logic "1" and logic "0" as shown in FIG. Figure d shows such an information signal demodulated by the other transmitter/receiver (16 or 1), in which logic "1" and logic "0" are faithfully transmitted. In the circuit of the embodiment, the output signal of the demodulation circuit 13 is an inversion of the signal d in the figure.

又、CLAMP信号は、受信動作のときは論理
“1”でFETトランジスタ11aがオフであり、
送信動作のときは、DATA信号が論理“1”の
とき論理“1”でFETトランジスタ11aがオ
フ、DATA信号が論理“0”のとき論理“0”
でFETトランジスタ11aがオンとなるもので
ある。
In addition, during reception operation, the CLAMP signal is logic "1" and the FET transistor 11a is off.
During transmission operation, when the DATA signal is logic "1", the FET transistor 11a is turned off, and when the DATA signal is logic "0", the FET transistor 11a is turned off.
In this case, the FET transistor 11a is turned on.

発明の効果 以上の詳細な説明で明らかなように、本発明は
少なくとも1対の送受信装置の一方から他方へ電
源供給するための電源供給線路に、同調トランス
の2次巻線を接続して、電源供給線路への情報信
号の重畳あるいは、逆に電源供給線路からの情報
信号の分離を選択された周波数帯域で行なうとと
もに、前記同調トランスの1次巻線と同調コンデ
ンサで形成された並列共振回路に並列に、前記並
列共振回路を短絡するためのスイツチ手段を設け
た構成にし、情報信号が論理“0”のとき該スイ
ツチ手段をオンし、論理“1”のときに前記並列
共振回路に蓄積されている振動エネルギーを瞬時
に消費させるので、論理“1”と論理“0”の区
切りの正確な情報信号を伝送することができ、信
頼性の高い送受信装置を実現することができる。
Effects of the Invention As is clear from the above detailed description, the present invention connects the secondary winding of a tuned transformer to a power supply line for supplying power from one of at least one pair of transmitting/receiving devices to the other. A parallel resonant circuit formed by the primary winding of the tuned transformer and the tuned capacitor, which superimposes the information signal on the power supply line or, conversely, separates the information signal from the power supply line in a selected frequency band. A switch means for short-circuiting the parallel resonant circuit is provided in parallel with the information signal, and the switch means is turned on when the information signal is logic "0", and when the information signal is logic "1", the information signal is stored in the parallel resonant circuit. Since the vibration energy generated by the transmission is instantaneously consumed, it is possible to transmit an information signal with an accurate delimitation between logic "1" and logic "0", and a highly reliable transmitting/receiving device can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A,Bは本発明の一実施例の送受信装置
を示す回路構成図、第2図は同信号分離の原理を
示す回路特性図、第3図a,b,c,dは同回路
動作を表わす一部信号波形のタイミング図、第4
図a,b,cは従来例における回路動作を表わす
一部信号波形のタイミング図である。 1……送受信装置(電源供給側)、5a,5b
……回線、6……トランス、6a……トランス一
次巻線、6b……トランス2次巻線、8……コン
デンサ(信号分離用)、9……同調用コンデンサ、
10……同調トランス、10a……並列共振回
路、16……送受信装置(電源受給側)。
Figures 1A and B are circuit configuration diagrams showing a transmitting and receiving device according to an embodiment of the present invention, Figure 2 is a circuit characteristic diagram showing the principle of signal separation, and Figures 3a, b, c, and d are the same circuits. Timing diagram of some signal waveforms representing operation, Part 4
Figures a, b, and c are timing diagrams of some signal waveforms representing circuit operations in a conventional example. 1... Transmitting/receiving device (power supply side), 5a, 5b
...Line, 6...Transformer, 6a...Transformer primary winding, 6b...Transformer secondary winding, 8...Capacitor (for signal separation), 9...Tuning capacitor,
10... Tuning transformer, 10a... Parallel resonant circuit, 16... Transmitting/receiving device (power receiving side).

Claims (1)

【特許請求の範囲】 1 一次巻線と同調用コンデンサを並列に接続し
て並列共振回路を構成するとともに、2次巻線を
電源供給線路に接続した同調トランスを用いて電
源供給線路上に情報信号を重畳し、情報伝送と電
源供給を同一の回線で行い、前記並列共振回路と
並列にこれを短絡するためのスイツチ手段を設け
た送受信装置。 2 スイツチ手段は、送信時に情報信号が論理
“1”すなわち前記同調トランスが駆動されてい
るときにオフし、逆に論理“0”すなわち駆動さ
れていないときにオンする特許請求の範囲第1項
記載の送受信装置。
[Claims] 1. A parallel resonant circuit is constructed by connecting a primary winding and a tuning capacitor in parallel, and a tuning transformer in which a secondary winding is connected to a power supply line is used to transmit information on the power supply line. A transmitting/receiving device that superimposes signals, performs information transmission and power supply on the same line, and is provided with a switch means for short-circuiting the parallel resonant circuit in parallel. 2. The switch means is turned off when the information signal is at logic "1" during transmission, that is, when the tuning transformer is being driven, and is turned on when the information signal is at logic "0", that is, when it is not driven. Transmitting/receiving device as described.
JP58036171A 1983-03-04 1983-03-04 Transmitting/receiving device Granted JPS59161938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58036171A JPS59161938A (en) 1983-03-04 1983-03-04 Transmitting/receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58036171A JPS59161938A (en) 1983-03-04 1983-03-04 Transmitting/receiving device

Publications (2)

Publication Number Publication Date
JPS59161938A JPS59161938A (en) 1984-09-12
JPS6328535B2 true JPS6328535B2 (en) 1988-06-08

Family

ID=12462300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58036171A Granted JPS59161938A (en) 1983-03-04 1983-03-04 Transmitting/receiving device

Country Status (1)

Country Link
JP (1) JPS59161938A (en)

Also Published As

Publication number Publication date
JPS59161938A (en) 1984-09-12

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