JPS63282567A - Parallel arithmetic circuit for sum of products - Google Patents

Abstract

PURPOSE:To speed up convolutional arithmetic operation by providing N (N>=2) multipliers and setting the number of inputs of an adder to N=1 which is one larger than the number N of the multipliers. CONSTITUTION:An address bus 1 specifies NX2 addresses of a data memory 2 at a time, all operands of the N (N>=2) multipliers 3-6 are supplied at the same time, and the N multiplication results of the multipliers 3-6 which are obtained a gate delay time later and the output of an accumulator 8 are inputted to the multi-input adder 7 which bus N+1 input terminals. Then the output of the multi-input adder 7 which is obtained the gate delay time later is latched in the accumulator 8 with a latch clock. Thus, N-term sum-of-products arithmetic operation is performed in one cycle of address specification to the data memory 2 and the latching of the accumulator 8. Consequently, the processing where the arithmetic results of the sum-of-products arithmetic operation, etc., are accumulated is speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a parallel product-sum operation circuit such as a digital signal processor which is a stored program type processor for digital signal processing.

(Prior Art and Problems to be Solved by the Invention) In order to be able to process multiply-accumulate operations at high speed, conventional digital signal processors have pipelined one multiplier and one two-man power adder. , the configuration is such that multiplication at a certain time and addition of the multiplication result one cycle before that time and the cumulative result up to two cycles before that time are executed simultaneously.

Therefore, (1) a product-sum operation with a large number of terms requires a processing time linearly proportional to the number of terms;

■In pipeline processing, processing is divided into several stages, so until each calculation stage is filled with data, there are stages that perform meaningless calculations as overhead.

There were other drawbacks.

In addition, in the case of the method of multiplexing arithmetic units, for multiplication, even if the multipliers are provided as many times as the number of product terms and all multiplication results can be obtained at the same time, for addition, it is necessary to have multiple adders operated by two people. However, when the number of operands N is 3 or more, the operation must be divided into log2N steps and added, which has the disadvantage that the effect of multiplexing the arithmetic units cannot be fully utilized.

(Object of the Invention) The present invention has been proposed in view of the above points, and its purpose is to improve the processing of accumulating multiplication results such as product-sum operations, which are frequently performed in digital signal processing. An object of the present invention is to provide a parallel product-sum calculation circuit that can be operated at high speed.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a data memory capable of supplying data at N×2 (N≧2) independent addresses by controlling address paths, and a data memory capable of supplying data at N×2 (N≧2) independent addresses. N multipliers which are composed of combinational circuits and which output a result after a gate delay time when inputted, and which input data from the data memory;
The same (composed of a combinational circuit) includes a multi-input adder with N+1 inputs that inputs data from the multiplier and the accumulator described later, and an accumulator that latches the addition result of the multi-input adder using a latch clock, and has N terms. The gist of the present invention is a parallel product-sum calculation circuit characterized in that a product-sum calculation is executed in one cycle by addressing the data memory and latching the accumulator.

That is, in the present invention, when the addresses of NX2 operands are specified simultaneously, the multiplier simultaneously executes multiple multiplications in parallel, and the multi-input adder adds the results of those multiple multiplications to the value in the accumulator, The main feature is that the addition result is stored in an accumulator using a latch clock, and multinomial product-sum operations can be executed at high speed with one-cycle control using only addressing and latching.

Note that compared to conventional technology, by multiplexing multipliers, multiplications that could originally be executed simultaneously from an algorithmic perspective can be executed in parallel, and the number of adder inputs can be reduced by the number of multipliers). J The difference is that by increasing the number by one, the results of multiple multiplications executed in parallel and the accumulated results up to that point are added at once instead of sequentially.

(Example) Hereinafter, the present invention will be described in detail along with drawings showing examples. Note that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.

FIG. 1 is a block diagram showing an embodiment of a parallel product-sum operation circuit according to the present invention, where 1 is an address path, 2 is a data memory, and 3
,4. ..., 6 is a multiplier, 7 is a multi-input addition type,
8 is an accumulator (accumulation register). This shows a case where N-term product-sum operations are performed simultaneously, and when data is input, N (N22) multipliers 3 to 3 are composed of combinational circuits that output the results after a gate delay time.
6, a multi-input adder M7 with the number of inputs N+1 which is also a combinational circuit, a data memory 2 which can supply data of NX2 independent addresses, and an accumulator 8 which latches the addition result according to the latch clock. . The connection relationship of the configuration is that NX2 data output ports of the data memory 2 are connected to two inputs of each of the N multipliers 3 to 6, and the outputs of the Nil multipliers 3 to 6 are connected to multi-input addition. The output of the multi-input adder WI7 is coupled to the input of the accumulator 8, and the output of the accumulator 8 is coupled to a part of the input of the multi-input adder 7.

To describe the operation of each part when executing an operation, NX2 addresses of data memory 2 are specified at once by address path 1, all operands are simultaneously supplied to N multipliers 3 to 6, and multipliers 3 to 6 are N obtained after a gate delay time of
The multiplication results and the output of the accumulator 8 are input to a multi-input adder N7 having N+1 inputs, and the output obtained after the gate delay time of the multi-input adder l17 is latched into the accumulator 8 by a latch clock. The product-sum operation is executed in one cycle by addressing the data memory 2 and latching the accumulator 8.

FIG. 2 is a block diagram showing another embodiment in which the multi-input adder 7 in the above embodiment is a three-input adder, in which 1 is an address path, 2.2' is a data memory, 3, 4 is a multiplier,
7' is a three-input adder, and 8 is an accumulator. The configuration and operation of this embodiment are the same as those of the embodiment shown in FIG.

Next, a specific example of calculation execution in the embodiment shown in FIG. 2 will be explained.

For example, Σ A, XX, = A, XX, +A2XX2+person, XX,
+Person, XX4+AsXX, +A6XX, +・ When performing operations such as =・, the address path 1 is
Xl, A2. Specify the address of X2 at the same time, transfer A, ,X, from data memory 2 to multiplier 3, and transfer
Simultaneously supplies X2 from ~ to multiplier 4, and multipliers 3 and 4
Now, execute AlX X, , person 2×x2 at the same time. Then, by three-input addition N7', AlX X, + A2
Execute XX2 and store in accumulator 8.

In the next cycle, address path 1 to ^3jX3#A
4. Specify the address of X4 at the same time, and transfer A3. X, from the data memory 2' to the multiplier 4 A4. X4 is supplied at the same time, and in multiplier 3.4 ^
3xX3. Execute A4××4 at the same time.

Then, A, XX3, and A4 are added by the three-input adder 7'.
XX, and AlX stored in accumulator 8
Add X, + A2X X2, accumulator 8
Store in.

Furthermore, in the next cycle, A, XMS, and person. Execute the multiplication of X X6, and combine the two multiplication results with A, X Xi+
A.

XX2+A, Xchi+A, and XX4 are added by a three-input adder 7' and stored in an accumulator 8.

By repeating the above, when executing ΣA, X X, multiplication is executed two terms at a time, and the results are accumulated.

FIG. 3 is a diagram showing the timing of the adder and accumulator in the embodiment shown in FIGS. 1 and 2,
Addressing on the rising edge of the clock feeds the data into the multiplier, and after the gate delay time, the result is available at the adder output. The calculation is executed by latching it into the accumulator at the falling edge of the clock at 9.

(Effects of the Invention) As described above, since the parallel product-sum operation circuit of the present invention is equipped with N (N22) multipliers, it is possible to execute multiple multiplications at the same time, and the number of inputs to the adder can be reduced. Number of multipliers N
Since there is one more N+1, multiple multiplication results obtained at the same time and the accumulated value in the accumulator can be added at once, and so-called convolution operations such as ΣA, XX, etc. can be processed very quickly. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the parallel product-sum calculation circuit of the present invention, FIG. 2 is a block diagram showing another embodiment, and FIG.
FIG. 2 is an explanatory diagram of the operation shown in FIG. 1...address path, 2,2'...data memory, 3-6...multiplier, 7...
Multi-input adder, 7'... Three-input adder, 8...
...Accumulator patent applicant Nippon Telegraph and Telephone Corporation Haka 1 person

Claims (1)

[Claims] It consists of a data memory that can supply data of N×2 (N≧2) independent addresses by controlling the address path, and a combinational circuit that outputs the result after a gate delay time when data is input. N multipliers for input, a multi-input adder with N+1 inputs which is also a combinational circuit and inputs data from the multipliers and the accumulator described later, and the addition result of this multi-input adder is latched by a latch clock. 1. A parallel product-sum operation circuit, comprising: an accumulator, and executes an N-term product-sum operation in one cycle by addressing the data memory and latching the accumulator.