JPS63281588A - Teletext receiver - Google Patents

Abstract

PURPOSE:To display a picture on the reception side with an arbitrary timing irrespective of the timing on the transmission side by adding a program management memory circuit to be used for managing page numbers and adding a timer means. CONSTITUTION:When a program number is selected, a minimum page number is read out from the program management memory circuit 6 for the program number, and this minimum page number is first displayed. Thereafter, at a timing notified by the timer means 7, subsequent page data of program numbers are retrieved and displayed one after one, up to the maximum page, then the operation returns to the minimum page. In such a way, a picture can be displayed with an arbitrary timing on the reception side irrespective of the timing on the transmission side.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a teletext receiver having a large capacity packet memory circuit.

2. Description of the Related Art A conventional example of a teletext receiving device that can store all transmitted packet data page by page in a packet memory circuit, read page data of a selected program from the packet memory circuit, and immediately display it. is shown in Figure 4. In the figure, 1 is a packet data input terminal, 2 is an arithmetic control circuit, 3 is a packet memory circuit, 4 is a memory management circuit, and 5 is a packet data output terminal.

The packet data is read into the arithmetic control circuit 2 via the packet data input terminal 1, and the arithmetic control circuit 2 detects the program number, page number, and number of packets constituting the page from the packet data. and determine whether the page number exists in a row. If it exists in the management memory circuit 4, the storage of packet data is started in the packet memory circuit 3 from the storage start address indicating the start address of the area where packet data is stored. If the same program number and page number do not exist in the management memory circuit 4, the end of the storage area calculated from the program number, page number, storage start address, and number of packets is stored in an unused area of the management memory circuit 4. Write each terminal address. FIG. 5 is a diagram showing the contents and configuration of the management memory circuit 4 in FIG. 4.

In image display, when a program number and a page address are selected, the arithmetic control circuit 2 searches the management memory circuit 4, detects the storage start address of the matching page data, and reads the page data from the packet memory circuit 3. The packet data is output to and displayed on an image display section (not shown) via the data output terminal 5.

Here, if only the program number is selected, there is no page specification, so either wait until the page data of the program number is received, or search the management memory circuit 4 and select the first page of the program number. Then, when page data for that program number is received, the data is displayed.

Problem to be solved by the invention In such a conventional example, when only the program number is selected,
The method of waiting until the page data of the corresponding program number is received has the problem of long waiting time, so the first page is searched and displayed, and then the page data of the corresponding program number is displayed every time it is received. In this method, after displaying one page,
It is good if two pages can be displayed, but if not, pages may be skipped and displayed.

In addition, the displayed screen does not change until the next page data is sent, so if the recipient wants to view the next page, the page number must be reset, which inconveniences the operation of the receiving device. It also had some problems.

Means for Solving the Problems In order to solve the above problems, the teletext receiving apparatus of the present invention has a packet memory circuit that stores all transmitted packet data, a management memory circuit used for managing the packet memory circuit, and a reception device. It consists of a program management memory circuit used to manage page numbers for program numbers, an arithmetic control circuit that controls these circuits, and a timer circuit that notifies the arithmetic control circuit of display timing at certain time intervals.

According to the above-described configuration, the present invention detects a program number and a page number from transmitted packet data by an arithmetic control circuit, and for the detected program number, the page number is set to the smallest page stored in the program management memory circuit. If it is smaller than the number, rewrite the minimum page number. Alternatively, if it is larger than the maximum page number, the maximum page number is rewritten.

When only a program number is selected, the minimum page number for this program number is read out from the program management memory, the minimum page number of the corresponding program number is displayed first, and then sequentially at the timing notified by the timer means. , to search and display the next page data of the corresponding program number, and when the maximum page is searched and displayed, return to the minimum page, so that the screen can be displayed at any timing on the receiving side, regardless of the timing on the sending side. Can be done.

Embodiment FIG. 1 is a circuit diagram of a teletext receiver according to an embodiment of the present invention, and the same parts as those in FIG. In FIG. 1, 6 is a program management memory circuit, and for program numbers r000J to 999J, the minimum page number and maximum page number have an initial value of 1.
'-FFJ is written. Of course, the initial value is f
- Codes other than FFJ are also possible. Further, 7 is a timer circuit that notifies the arithmetic control circuit 2 of display timing at preset fixed time intervals. FIG. 2 is a diagram showing the contents and configuration of the program management memory circuit 6 in FIG. 1.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

Similar to the circuit operation shown in FIG. 4, the arithmetic control circuit 2 detects the program number, page number, and number of packets from the transmitted packet data. Next, the management memory circuit 4 is searched to determine whether the detected program number and page number exist. If it already exists, the packet data is sequentially rewritten in the same area of the packet memory circuit 3.

On the other hand, if the detected program number and page number do not exist in the management memory circuit 4, the program number and page number are written in the management memory circuit 4 and then stored.

Start importing data. Furthermore, the program management memory circuit 6 is searched to determine whether or not the minimum page number and maximum page number are in the initial state for this program number. If it is in the initial state, the detected page number "o4" is written in the minimum page number and maximum page number, such as the program number ro01 J in FIG.

If it is not in the initial state, the detected page number is compared with the minimum page number, and if this page number is smaller than the minimum page number, this page number is written as the minimum page number. Next, if this page number is larger than the minimum page number, it is compared with the maximum page number. If this page number is greater than the maximum page number, this page number is written to the maximum page number. For example, program number "002"
'', the contents of the program management memory circuit 6 shown in FIG. 2 are rewritten as shown in FIG. 3.

In this state, for example, if the recipient selects only the program number ro02J, the arithmetic control circuit 2 refers to the program management memory circuit 6. Since the minimum page number is "o2", the screen data of program number "0O2J" and page number "o2" is searched from the management memory circuit 4, read from the packet memory circuit 3, and the packet data is displayed on the image display section (not shown). figure)
Output and display.

Next, the timing of searching or displaying the next page is notified to the arithmetic control circuit 2 by the output of the timer circuit 7, and the next page number "03" is set. It is determined whether this page number "Q3" is larger than the maximum page number. In this case, since the maximum page number is larger, the management memory circuit 4 is searched as described above, the corresponding screen data is read from the packet memory circuit 3, and the packet data is output to the image display section and displayed. .

In this way, when the page data is displayed sequentially and the page number is set to "11", the maximum page number for the program number "o02" in the program management memory circuit 6 is "1o".
Therefore, since it is larger than the maximum page number, the page number is reset to the minimum page number, and the above-described operation is repeated thereafter.

Effects of the Invention According to the present invention, it is possible to immediately display the smallest page of program screen data stored in the receiving device, reducing waiting time, and sequentially displaying the smallest page regardless of the timing on the sending side. Therefore, if enough time has elapsed for all the transmitted program data to be accumulated in the receiving device, it is possible to efficiently display pages from the first page to the last page while maintaining page continuity, and the effect is remarkable. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a main part of a teletext receiving device which is an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing the contents of a program management memory circuit, and FIG. 4 is a diagram of a conventional teletext receiving device. FIG. 6 is a circuit diagram of the main part of the device. FIG. 6 is a diagram showing the contents and configuration of the management memory circuit in FIG. 4. 1...Packet data input terminal, 2...
・Arithmetic control circuit, 3...Packet memory circuit,
4... Management memory circuit, 6... Baku,
6...Program management memory circuit, 7...Timer circuit. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 2 Figure 3 Figure 5 Procedural amendment December 3, 1988 To the Commissioner of the Japan Patent Office 6 1 Indication of case 1988 Patent application No. 117364 No. 2 Name of the invention Teletext broadcasting receiving device 3 Relationship with the amended case Patent application Address 1006 Kadoma, Kadoma City, Osaka Prefecture Name
(582) Matsushita Electric Industrial Co., Ltd. Representative Tani
Akio I 4 Agent 571 Address 6, Matsushita Electric Industrial Co., Ltd., 1006 Oaza Kadoma, Kadoma City, Osaka Prefecture Contents of amendment (1) "Memory management circuit" on page 2, line 14 of the specification Corrected to "memory circuit". ? ) On page 3, line 12, "Address" has been corrected to "Number." (3) "Memory" on page 6, line 18 has been corrected to "memory circuit."

Claims (1)

[Claims] A packet memory circuit that stores packet data of transmitted teletext; a management memory circuit that is used to manage the packet data; and a program management memory circuit that is used to manage program numbers and page numbers included in the packet data. , comprising an arithmetic control circuit that performs arithmetic control of the packet memory circuit, the management memory circuit, and the program management memory circuit, and a timer circuit that notifies the arithmetic control circuit of timing at a preset constant cycle, The minimum and maximum page numbers received for each program number are written in a management memory circuit, and when a certain program number is selected, the minimum page of the corresponding program number is determined from the program management memory circuit. A teletext receiving device characterized in that after reading from the packet memory circuit, the next page is read at a timing set by the timer circuit, and when the maximum page is read, the text is read again from the minimum page.