JPS63281440A - Manufacture of dielectric isolating substrate - Google Patents

Abstract

PURPOSE:To reduce the quantity of a semiconductor substrate curved by forming an insulating film onto the substrate, to which a groove is shaped, annealing a polycrystalline semiconductor thin-film formed onto the insulating film under an unmelted state and shaping a polycrystalline semiconductor onto a species layer. CONSTITUTION:Isolating grooves 3 are formed through etching, using an SiO2 film 2 by a specified pattern shaped onto a single crystal Si substrate 1 as a mask. The SiO2 film 2 is removed, and an SiO2 film as an insulating film 5 for element isolation is formed again. A buried layer 4 having low resistance is shaped as required before the formation of the SiO2 film as the insulating film 5. A polycrystalline Si layer (laminated) 8 in film thickness of approximately 0.4mum is vapor-grown at low pressure onto the insulating film 5 for element isolation. The polycrystalline Si layer 8 is annealed under an unmelted state. A polycrystalline Si layer 6 as a substrate supporter layer is deposited on the species layer 8 in film thickness of approximately 400mum through vapor growth. Lastly, the surface of the polycrystalline Si layer 6 is polished flatly, and the single crystal Si substrate 1 is isolated by the isolating grooves 3 and the insulating film 5 for element isolation, and single crystal Si regions 7 are shaped.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor substrate for producing an integrated circuit, and in particular to a method of manufacturing a dielectric isolation substrate suitable for integrating high-voltage elements. Regarding the manufacturing method.

[Conventional technology]

In monolithic ICs, methods for electrically insulating and isolating constituent elements, that is, element isolation methods, can be roughly divided into pn
There are a junction isolation method and a dielectric isolation method. The pn junction isolation method uses a reverse biased pn junction depletion layer to
This is a method of isolating between elements, and the dielectric isolation method is 5i
This is a method of separating using an insulating film such as a 02 film.

The dielectric isolation method has the advantages of high isolation voltage, low leakage current, no latch-up, and no need to apply bias voltage for isolation, compared to the pn junction isolation method. Suitable for integrated circuit applications.

FIG. 2 is a flowchart of a conventional process for manufacturing a dielectric isolation substrate. Form a pattern with an S j O2 film 2 on a single crystal Sj substrate 1b), and use this as a mask to form a pattern on a Si
is partially etched away to form isolation grooves 3 with a depth of several tens of μm.
C), on the wafer surface on the side where the separation groove is formed,
An element isolation insulating film 5 made of a S'02 film or the like is formed. Before forming the element isolation insulating film 5, a low-resistance buried layer 4 can be formed if necessary. After forming the element isolation insulating film 5, a polycrystalline 81 layer 6 having a thickness of several hundred μm is grown in a vapor phase as a substrate support on the element isolation insulating film 5 (e).

Furthermore, both surfaces of the substrate are polished so that the surface of the polycrystalline S1 layer becomes flat and the single crystal Si is separated by the separation grooves 3, thereby completing the substrate shown in FIG. Elements are formed in single crystal Si region 7 surrounded by element isolation insulating film 5 .

Regarding the manufacturing method of the conventional dielectric isolation substrate mentioned above,
For example, Journal of Electrochemical Society, Volume 124, January 1977, Pages 5C-
Page 12C (Journal, ofElectro
, S o c, Vo Q, 124. ．． 1 an, 19
77°PP, 5C-PP, 12C), etc.

In the above conventional manufacturing method, the polycrystal S1 of the support is
During deposition at deposition temperatures of 0 to 1250 DEG C., there was a problem in that the substrate curved as shown in FIG.

This curvature adversely affects processing accuracy in the process of polishing the substrate and in the photolithography process when forming individual elements.

As a method to solve this problem of the board being curved, Japanese Patent Laid-Open No. 11.7750/1982
As shown in Japanese Patent No. 210848, an insulating layer is formed on the surface of the semiconductor substrate in which an isolation groove is formed, and a polycrystalline semiconductor layer (hereinafter referred to as a seed layer) is thinly formed on the insulating layer. A known technique is to heat and melt the material with a laser beam to form a single crystal, thereby forming a seed layer and a substrate support layer.

[Problem that the invention seeks to solve]

In the above conventional technology, in order to prevent curvature of the substrate, the seed layer is heated and melted by a laser beam to make the seed layer into a single crystal. Therefore, curvature occurs due to melting and assimilation, and curvature reduction is caused by melting and assimilation. It becomes an obstacle. Further, there was a problem that melting occurred in portions of the underlying substrate other than the seed layer. Further, there is a problem in that the laser beam is scattered by the separation groove formed on the substrate.

An object of the present invention is to solve the above problems and provide a method for manufacturing a dielectric isolation substrate with small curvature.

[Means for solving problems]

The above object is achieved by growing the polycrystalline Si layer serving as the support layer with a sufficiently stable large grain size at the deposition temperature.

More specifically, an insulating film is formed on a semiconductor substrate in which a groove is formed, and a polycrystalline semiconductor thin film (also called a seed layer) formed on this insulating film is annealed in an unmolten state, and then the polycrystalline semiconductor is This is accomplished by forming it on a seed layer.

[Effect]

After forming an insulating film to insulate each element region on a semiconductor substrate, a polycrystalline semiconductor thin film layer (seed layer) is deposited on this surface, and this seed layer is annealed at a temperature that does not melt it. . In this way, the grain size of the seed layer is increased using a phenomenon (sintering phenomenon) in which a plurality of crystal grains are coalesced by heating below their melting points.

In general, it is in an amorphous state like a SiO2 layer! l! on ms,
When a polycrystalline semiconductor (for example, Polysj) is deposited, the grain size of the polycrystalline semiconductor layer is small because there are no grains of a semiconductor material such as Si that will serve as a seed layer for growth in the initial stage of deposition. As the semiconductor material is deposited, each polycrystalline grain is successively grown by vapor phase epitaxial growth using the polycrystalline grains in the middle of deposition as seeds.As a result, the supporting layer is formed as shown in FIG. The later deposited portion becomes a dendritic structure with larger grain sizes.

On the other hand, if a seed layer whose grain size has been increased by annealing in a non-molten state is used as a "seed" for growth as in the present invention, a polycrystalline layer with a larger grain size can be formed at the initial stage of deposition, and this By using this as a growth seed layer, the grain size of the entire support layer during deposition can be further increased and stabilized.This solves the problems of the conventional technology using heat melting with a laser beam. A dielectric isolation substrate with less curvature can be manufactured.

Here, the seed layer must be made sufficiently thin so that the substrate does not curve during grain growth during annealing.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 This will be explained using FIG. FIG. 1 is a diagram showing the manufacturing process of the dielectric isolation substrate of this example, and FIG. 1(a) to (
g) is a vertical cross-sectional view of the substrate in each step.

FIG. 1(,) shows a longitudinal cross-sectional view of a single-crystal Si substrate 1. As shown in FIG.

Next, as shown in FIG. 1(b), an S i 02 film 2 having a predetermined pattern is formed on this single crystal 81 substrate 1''. For patterning the 5iOz film 2, a method such as photolithography is used.

As shown in FIG. 1(c), using this Sj02 film 2 as a mask, a separation groove 3 having a depth of 50 μm at its deepest part is formed by etching. Examples of etching solutions include:
KOH etc. are used. In this case, (
]-00) surface is etched to form a 7-shaped separation groove 3.

Next, as shown in FIG. 1(d), this 5i02 film 2 is removed and a SiO2 film that will become the element isolation insulating film 5 is formed again. Before forming this element isolation insulating film 5, if necessary, ion implantation is performed to form a low-resistance buried layer 4.

Furthermore, as shown in FIG. 1(e), a polycrystalline Si layer (seed layer) 8 with a film thickness of 0.4 μm was deposited on the element isolation insulating film 5 by a low pressure vapor deposition (LPGVD) method. . Next, P (phosphorus) is added to the polycrystalline Si layer (seed layer) 8 at an impurity concentration of approximately 1.
021 pieces/cn? I doped with it. And polycrystalline S
The i-layer (seed layer) 8 was annealed in a non-molten state. That is, annealing (heat treatment) was performed for 1 hour at a temperature lower than the melting point (141.0° C.) of the 84 polycrystalline layers (seed layer) 8, 1200° C. in this example.

Next, as shown in FIG. 1(f), a polycrystalline Si layer 6, which will become a substrate support layer, is deposited on a seed layer 8'' to a thickness of 40 mm by vapor phase growth.
The film was deposited to a thickness of 0 μm.

Finally, as shown in FIG. 1(g), the surface of the polycrystalline Si layer 6 is polished so that it becomes flat, and the single crystal Si substrate 1 is polished to form the isolation groove ^ and the element isolation insulating film 5. so that the single crystal Si region 7 is formed by separating the single crystal Si region 7.
i Polish the surface.

In this figure, the top and bottom surfaces are reversed from those in FIGS. 1(a) to (f).

In this example, by annealing the seed layer in a non-molten state, the grain size of the crystals constituting the seed layer increases to approximately 3 μm, and there is no problem associated with melting, compared to the conventional technology in which the seed layer is annealed in a molten state. , we were able to manufacture a dielectric isolation substrate with less curvature.

In this example, in the step shown in FIG. 1(e), P(
Phosphorus) was doped into the seed layer 8 and annealed, but as a result, the grain size of the crystal grains constituting the seed layer 8 can be increased by annealing at a lower temperature and for a shorter time than when no doping is done. .

In this embodiment, P (phosphorus) is doped, but similar effects can be obtained by doping with other impurities such as As (arsenic).

Example 2 In this example, the main steps are the same as those in Example 1, but in the step shown in FIG. It became possible to increase the crystal grain size of the seed layer 8 formed after the annealing to about 20 μm.

In this example, the seed layer 8 is not doped with P (phosphorus), and the annealing in the non-molten state is performed at a temperature of 12
The test was carried out under the conditions of 50'C for 1 hour and 4 hours.

In Examples 1 and 2 above, annealing using an electric furnace was used as the annealing (heat treatment) method for the seed layer 8.
In addition, lamp annealing, annealing using a strip heater, etc. can also be used.

Furthermore, as a semiconductor forming the dielectric isolation substrate, Si
(silicon), but other semiconductor materials (Ge, Ga, etc.) were used.
Compound semiconductors such as As) can also be used.

〔Effect of the invention〕

According to the present invention, the grain size of the polycrystalline 81 layer can be further increased by annealing the seed layer in a non-molten state, so the amount of curvature of the substrate can be reduced compared to the conventional technology in which the seed layer is annealed in a molten state. At the same time, it is possible to provide a method for manufacturing a dielectric isolation substrate that does not cause problems associated with melting.

[Brief explanation of drawings]

1 is a diagram showing the manufacturing process of a dielectric isolation substrate according to the present invention, FIG. 2 is a diagram showing the manufacturing process of a dielectric isolation substrate using a conventional method without using a seed layer, and FIG. FIG. 4 is a conceptual diagram (longitudinal cross-sectional view) showing a curved state, and FIG. 4 is a diagram (enlarged vertical cross-sectional view) showing the structure of the polycrystalline S1 support layer according to a conventional method without using a seed layer. 1... Single crystal Si substrate, 2... 5jO2 film, 3...
- Isolation groove, 5... Insulating film for element isolation, 6... Polycrystalline S
i layer (support layer) 8 polycrystalline Si layer (seed layer).

Claims (1)

[Claims] 1. A method for manufacturing a dielectric isolation substrate characterized by including the following steps: (1) forming a groove in a predetermined region of a predetermined semiconductor substrate; (2) forming the groove; forming an insulating film on the semiconductor substrate; (3) forming a polycrystalline semiconductor thin film on the insulating film; (4) annealing the polycrystalline semiconductor thin film in a non-molten state; A process of forming a polycrystalline semiconductor on a polycrystalline semiconductor thin film.