JPS63280474A - Structure of superconducting logic circuit device - Google Patents

Abstract

PURPOSE:To increase the circuit operational margin by averting the effect of a parasitic inductance and enhancing the coupling state of control wires by a method wherein an upper layer 1 is formed into the inductor of a logic circuit. CONSTITUTION:A lower electrode 2 comprising a superconducting thin film is connected to a ground plane 5 formed on a substrate 8 through the intermediary of an earth electrode 6 while a tunnel barrier layer for Josephson junctions 3 is formed on the surface of the lower electrode 2. An upper electrode 1 comprising the superconducting thin film is formed and then control wires 4 comprising the superconducting thin film are formed through the intermediary of an interlayer insulating film 11 to form a logic circuit. An inductor required for the logic circuit is formed by extending the upper electrode 1. The inductance of electrodes is increased proportionally to the distance from the ground plane 5. Consequently, when an electrode in a junction part is formed in the lower electrode 2 near the ground plane 5, a parasitic inductance is decreased to increase the operational margin of the logic circuit. In such a constitution, the control wires 4 pass above the upper electrode 1 even in the junction part so that the coupling state of input signals to the logic circuit may be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a superconducting logic circuit device, and particularly to the structure of a superconducting logic circuit device suitable for a Josephson logic circuit.

[Conventional technology]

The structure of conventional superconducting logic circuit devices is
E, Transactions of Solid State Circuit, Nisshi 14. Nα5 (1979) No. 787
Pages 793 (IEEE Trans, of 5o
lid-5tate C1rcuits, vol.
5C-14.

As discussed in Na5 pp, 787-793 (1979), inductance is necessary to configure one circuit (see Figure 2), and the lower electrode 2 of the Josephson junction is extended to form the circuit. This formed the necessary inductor (see Figure 3). In the Josephson junction, as shown in FIG. 3, the upper electrode 1 forms a large electrode covering four Josephson junctions 3. The control line 4 was installed on the lower electrode 2 and the upper electrode 1 which served as an inductor, and applied an input signal to the logic circuit by magnetic coupling.

[Problem that the invention seeks to solve]

The above conventional technology does not take into account the parasitic inductance caused by the upper electrode 1 covering the Josephson junction, and the fact that the input signal cannot be coupled to the circuit at the portion of the control line to which the input signal is applied above the upper electrode. However, there was a problem in that the margin of circuit operation could not be increased.
'An object of the present invention is to increase the margin of circuit operation by eliminating the influence of parasitic inductance and increasing the coupling of control lines.

[Means for solving problems]

The above object is achieved by not using the bottom electrode to form the inductor of the logic circuit, but by extending the top electrode to form the inductance required for the circuit.

[Effect]

The electrode that connects each Josephson junction becomes a lower electrode, which is closer to the ground plane than when connected using a conventional upper electrode, reducing parasitic inductance. In addition, by forming an inductor with the upper electrode and installing a control line above it, there is no part where the input signal is not coupled to the circuit, unlike the conventional upper electrode part, and the degree of coupling of the input signal is increased. , the circuit margin increases.

〔Example〕 Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment 1] FIG. 1 is a diagram showing an embodiment of the present invention. Figure 1 (a
) is a front view of the circuit viewed from above, and Figure 1(b) is a side view of the circuit viewed from the paper. However, in this figure, the dimension in the film thickness direction is exaggerated relative to the dimension in the lateral direction. It is. A ground plane 5 made of a superconducting thin film such as a Nb film is formed on the substrate 8 . A lower electrode 2 made of a superconducting thin film is connected to the ground plane 5 via a ground electrode 6, and an interlayer insulating film 9 is formed in the gap between the lower electrode 2 and the ground plane 5. After forming an interlayer insulating film 10 on the lower electrode 2 and forming an opening for forming the Josephson junction 3 in a part of the interlayer insulating film 10, a tunnel barrier layer for the Josephson junction 3 is formed on the upper surface of the lower electrode 2. form. Thereafter, an upper electrode 1 made of a superconducting thin film is formed.

A control line 4 made of a superconducting thin film is formed on these through an interlayer insulating film 11 to form a logic circuit. In this embodiment, an inductor (also referred to as inductance) necessary for the logic circuit is formed by extending the upper electrode 1. Thereby, the parasitic inductance due to the lower electrode 2 directly under the junction can be reduced. Typically, the inductance of an electrode increases with increasing distance from the ground plane.

Therefore, if the lower electrode 2 close to the ground plane 5 forms the electrode of the junction, the parasitic inductance will be smaller. This parasitic inductance reduces the operating area of the logic circuit, so it must be made as small as possible. In this embodiment, as described above, the parasitic inductance can be made small, which has the effect of increasing the operating margin of the logic circuit. be.

Further, since the control line 4 installed on the upper electrode 1 passes over the upper electrode 1 also at the junction, there is an effect that the degree of coupling of input signals to the logic circuit can be increased.

[Example 2] In the device of Example 2 shown in FIG. 4, in order to further reduce the parasitic inductance of the electrode at the Josephson junction, the entire lower electrode 2 is integrated with the ground electrode 6, and the Josephson This forms a Son junction 3. That is, the entire lower surface of the lower electrode is formed in contact with the ground plane 5 directly below. This has the effect that parasitic inductance can be almost ignored and reduction of the operating area due to parasitic inductance can be prevented.

[Example 3] In the apparatus of Example 3 shown in FIG.
The lower electrode 2 is removed and the Josephson junction 3 is formed directly on the ground plane 5. That is, in this embodiment in which the ground plane 5 also serves as the lower electrode, parasitic inductance is almost eliminated. Therefore, there is an effect that there is no reduction in the operating area, and furthermore, there is an effect that the number of electrodes to be formed is further reduced when manufacturing one circuit, and the number of steps is reduced.

〔Effect of the invention〕

According to the present invention, the parasitic inductance of the Josephson logic circuit device can be reduced, and the degree of coupling of input signals is increased, so that there are effects of expanding the operating margin and increasing the operating speed.

[Brief explanation of drawings]

1(a) and (b) are respectively a front view and a side view of the device according to the first embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of a logic circuit, and FIG. 3(a) and (b) are FIG. 4(a) is a front view and a side view of a prior art device, respectively. 5(b) is a front view and a side view of an apparatus according to a second embodiment of the present invention, respectively, and FIGS. 5(a) and 5(b) are a front view and a side view, respectively, of an apparatus according to a third embodiment of the present invention. 1: Upper electrode, 2: Lower electrode, 3: Josephson junction,
4: Control line, 5 Nigelland plane, 6: Ground electrode, 7
: resistance, 8: substrate, 9, 10, 11: interlayer insulating film.

Claims (1)

[Claims] 1. At least a lower electrode, a Josephson junction, on the substrate;
A structure of a superconducting logic circuit device formed by sequentially laminating an upper electrode, an interlayer insulating film, and a control line, wherein the upper electrode is an inductor of the logic circuit.