JPS63280453A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive accomplishment of high speed operation of a transistor by a method wherein, in the semiconductor device having a heterogeneous semiconductor layer which forms a junction with single crystal silicon on the surface of the single crystal silicon, the heterogeneous semiconductor layer contains an amorphous region and a crystal region, and a part or the whole of said heterogeneous semiconductor layer is formed with the silicon of specific carbon composition. CONSTITUTION:The structure having a transition layer 6, for which carbon content is changed, as a part of an amorphous region in the midway between the amorphous silicon layer 3 containing carbon of 5% or more and located on a silicon single crystal substrate 1, and a polycrystalline silicon layer 5, is provided. Said polycrystalline silicon layer 5 is used to ohmic-contact the metal used for wiring, and the layer 5 may be formed on an Si(1-x)Cx layer 2. A structure having the transition layer 7, in which carbon content is changed, between the silicon substrate 1 and the amorphous silicon layer 3 as a part of an amorphous semiconductor layer, can also be formed. Also, the skipping of a conduction band can be prevented by providing the transition layer 7 as above-mentioned. Also, the above-mentioned two structures can be conbindly used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which one of the constituent materials is a material having a bandgap wider than a silicon single crystal, such as a silicon bipolar transistor having a heterojunction, and a method for manufacturing the same. It is related to.

[Conventional technology]

For example, if a material with a wider bandgap than silicon is used as the emitter material of a silicon bipolar transistor, a wide gap emitter can be formed, resulting in an increase in emitter injection efficiency, and high hFE can be expected even when the impurity concentration of the base layer is high. . When the impurity concentration of the base layer is high, the base resistance decreases, and the base travel time can be shortened by narrowing the base layer width, so it is expected that the speed of the bipolar transistor will increase. Oxygen-doped polycrystalline silicon (S
IPO3), amorphous silicon carbide, etc. are being considered.

[Problem that the invention seeks to solve]

However, these materials have a drawback of high resistance, which hinders the speeding up of transistors. Regarding this,
For example, “I.E.E., Eri et al., Electronic Device Bulletin, E.D.L. Vol. 6, No. 11, p. 311, 1
985 (IEEE, ELIYADLONOVITC
Het al, Electron Device L
etters, fiDL6. No, 6. p, 311.1
985).

In addition, as a wide bandgap heterojunction material with silicon,
GaAs, GaP, and single-crystal SiC have also been tried, but single-crystal materials have a fixed lattice constant, so when forming on single-crystal silicon, the lattice constant is due to a mismatch with the lattice constant of single-crystal silicon. When considering a transistor with a high density of interface states (therefore, the interface recombination current is large and high hyx cannot be expected.Also, each transistor has its own band gap, npn), the conduction band at the hetero interface is Since "skipping" cannot be controlled, the electron current density (I x 10'A/c
m'' or more) cannot be obtained.

The present invention has been made in view of these points, and its objectives are to reduce the interface states of the heterojunction with silicon, to reduce the resistance of the constituent films, and to reduce the bandgap in a wide range. It is an object of the present invention to provide a semiconductor device using a substance that can control the temperature and a method for manufacturing the same.

[Means for solving problems]

In order to achieve such an object, the present invention provides a semiconductor device having a heterogeneous semiconductor layer forming a junction with the single crystal silicon on the surface of the single crystal silicon, wherein the heterogeneous semiconductor layer includes an amorphous region and a crystalline region. , a part or all of the above-mentioned foreign semiconductor layer is formed of silicon having a carbon composition of 5% or more.

Further, in the manufacturing method according to the present invention, the single crystal silicon substrate is heated to 600°C or higher, and at least one of the constituent atoms is
A bond is formed on the surface of single crystal silicon by performing chemical vapor deposition using plasma generated from a first type of molecular gas containing silicon atoms and a second type of molecular gas containing silicon atoms as one of the constituent atoms. This method includes a step of forming a different type of semiconductor.

[Effect]

In the present invention, the energetic "skipping" of the valence band of an npn hetero-bipolar transistor is defined as Q, leV.
The above value can be set, and a bipolar transistor having a sufficiently high hFt can be obtained.

〔Example〕

First, an overview of the configuration of the present invention will be explained.

The semiconductor device according to the present invention has a non-uniform material or structure consisting of a microcrystalline or polycrystalline silicon region and an amorphous region, unlike the conventional technology in which a heterojunction is constructed using a uniform material different from silicon. The main feature is that it is composed of. Microcrystalline or polycrystalline silicon regions have high impurity doping efficiency and can reduce resistance. In addition, the amorphous region contains 5 to 30 at of carbon.
.

Composed of silicon containing %. The forbidden band width of an amorphous material can be controlled over a wide range by changing the carbon content. Furthermore, since the degree of freedom in bonding is large, it has the effect of suppressing the generation of interface states with silicon. This non-uniform material consisting of microcrystalline or polycrystalline silicon regions and amorphous regions has the following composition: Si (, -ゎC
It is written as x.

In addition, the method for manufacturing a semiconductor device according to the present invention involves setting the substrate temperature at 600°C or higher in a molecular gas containing silicon atoms as one of its constituent atoms and a gas containing carbon atoms as one of its constituent atoms, and using plasma-based chemical chemistry. Vapor phase growth (hereinafter referred to as “plasma C”)
This is called VDJ).

Hereinafter, the present invention will be described in detail along with examples.

FIG. 1 is a sectional view showing the most basic embodiment of the present invention. In FIG. 1, 1 is a silicon single crystal substrate, 2
is an S f n-x>CX layer as a heterogeneous semiconductor layer in which a crystalline region and an amorphous region coexist, and X≧0.05 in the amorphous region.

FIGS. 2(a) to (e) show Si (
These are second to sixth embodiments specifically showing the structure of the 1-ゎCX layer 2.

FIG. 2(a) shows 100% in the amorphous silicon layer 3 containing carbon.
It has a structure having a microcrystalline silicon region 4 of up to several hundred regions, and the amorphous silicon layer 3 with X≧0.05 and the microcrystalline silicon region 4 constitute a Si (1-Xl CX layer 2). Since the interface between the substrate 1 and S l (1-Xl CX layer 2 is composed of amorphous material, the forbidden band width is wide (,゛ and there are few interface states. Since the second part is dotted with low-resistance microcrystalline regions 4, Si
(, -ゎcxN2 It is possible to lower the overall resistance of all N2.

FIG. 2(b) is a cross-sectional view showing a structure having an amorphous silicon layer 3 containing 5% or more of carbon and a polycrystalline silicon layer 5 on a silicon single crystal substrate 1, and FIG. 2(C) is a silicon single crystal A transition layer 6 with varying carbon content is located between the amorphous silicon layer 3 containing 5% or more carbon and the polycrystalline silicon layer 5 on the substrate 1.
FIG. 3 is a cross-sectional view showing a structure having the amorphous region as part of the amorphous region. The polycrystalline silicon layer 5 is for making ohmic contact with metal for wiring, and is S i (
1-X) may be formed on CxJii 2. Second
Figure (d) is a cross-sectional view showing a structure in which a transition layer 7 with a varying carbon content is provided between a silicon substrate 1 and an amorphous silicon layer 3 as part of a different semiconductor layer. By providing the transition layer 7 in this way, it is also possible to eliminate "jumps" in the conduction band. A structure combining the structures shown in FIGS. 2(C) and 2(d) above is also possible.

Next, a manufacturing process for realizing the structure shown in FIG. 2(a) will be explained. This method uses plasma CVD. First, the temperature of the silicon substrate 1 is raised to 600°C or higher and H! Introduce gas. Next, a glow discharge is generated and H! The surface of the substrate 1 is cleaned in plasma.

Next, CH, gas, SiH, gas, and H2 gas are
．． Plasma CVD is performed by introducing at 3 Torr.

At this time, a deposition temperature of 600° C. or higher is used. This allows the formation of structures containing microcrystalline or polycrystalline layers. As the gas, Ct H4 may be used instead of CH, or other gases that can be decomposed to supply carbon may also be used.

Further, instead of SiH, a gas capable of supplying silicon, such as 5izH, may be used. Specifically, CHa gas IS CCM (Standard CC/M) and 5
It was deposited by plasma CVD using 53 CCM of iHa gas at a substrate temperature of TOO°C. At this time, PH gas was introduced as a doping gas, and phosphorus was added at 5X10"cm-'
50SC of Hl as a carrier gas.
A commercial was played.

The manufacturing process of the heterogeneous semiconductor layer shown in FIG. 2 (bl) is as follows:
After forming the carbon-containing amorphous silicon layer 3, the CH4 gas was turned off, and then plasma C was applied using only SiHa, H, and gases.
This may be a step of performing VD and depositing the polycrystalline silicon layer 5. Specifically, CH.

Plasma CVD of gas, S i Ha gas, and PH2 gas
After depositing 150 carbon-containing amorphous silicon layers at a substrate temperature of 650°C, the CHa gas was cut off and Si
Plasma CVD of H, gas and PI (s gas and Hz gas)
A polycrystalline silicon layer was deposited by the following steps.

Furthermore, in the case of FIG. 2 (C1), the transition layer 6 can be obtained by performing plasma CVD while decreasing the CHa gas flow rate after forming the amorphous silicon layer 3 containing carbon. , SiH with constant substrate temperature
It can also be formed by changing only the flow rate ratio of CH4 and CH4. For example, when the substrate temperature is 650°C, SiH
When plasma CVD is performed at a flow rate ratio of 4 gas flow rate/CH4 gas flow rate of 0.2, amorphous silicon containing carbon is formed, whereas when the CH gas flow rate is decreased, silicon Microcrystalline nuclei are generated and finally S s
In the case of only Ha, polycrystalline silicon is formed. Specifically, after depositing carbon-containing amorphous silicon at a substrate temperature of 600°C, the CHa gas flow rate was decreased at 0.023CCM/sec, and finally SiH was deposited.

A polycrystalline silicon layer was deposited by plasma CVD using only gas, PHs gas, and Ht gas.

In the case of FIG. 2(d), after flowing a certain amount of SiH4 gas and PH3 gas, the transition layer 7 is obtained by performing plasma CVD while increasing the CH and gas flow rates, and then C
Forming an amorphous silicon layer 3 with a constant H4 gas flow rate,
Finally, S i T (plasma C with only 4 gases and H2 gas)
VD is performed to deposit a polycrystalline silicon layer 5. In this case as well, it can be formed by keeping the substrate temperature constant and changing only the flow rate ratio of SiH4 and CH.

A structure in which the structures of FIGS. 2(C) and (d) are combined is shown in FIG. 2(e) as a sixth embodiment. In the case of Fig. 2(e), after flowing a certain amount of SiH4 gas and PH gas,
C) (a) After obtaining the transition layer 7 by performing plasma CVD while increasing the gas flow rate, forming the amorphous silicon layer 3 while keeping the CH gas flow rate constant, and then forming the amorphous silicon layer 3 while decreasing the CH gas flow rate. The transition layer 6 can be obtained by performing plasma CVD.The process will be specifically described below.

First, after flowing PH3 gas and SiH4 gas to cause glow discharge, plasma CVD is performed while increasing CHa gas at a rate of 0.023 CCM/sec. Next, after the CH4 gas became ISOCM, 150 carbon-containing amorphous silicon layers were deposited at a constant flow rate, and then the CH4 gas was decreased at a rate of 0.023CCM/sec, and finally the s
i A polycrystalline silicon layer was deposited by plasma CVD using only HA gas, PHs gas, and H2 gas, and
) is obtained.

FIG. 3 is a graph showing the resistivity versus deposition temperature of S 1 (1-X) CX having the structure shown in FIG. 2(a) deposited by the above method. The vertical axis is the resistivity determined by the four-probe method, and the horizontal axis is the deposition temperature. In this case, 0.2 was used as the ratio of the cH flow rate to the SiH4 flow rate, and 0.02 was used as the ratio of the PH3 flow rate to the SiH flow rate. The resistivity decreases with increasing deposition temperature. Deposition temperature 70
The presence of tens to hundreds of microcrystalline regions was confirmed in samples heated to 0°C or higher. S f (1-X) deposited in this way
The resistivity of CX can be lowered by more than four orders of magnitude compared to the resistivity of amorphous silicon carbide that has been reported in the past. Further, in this case, the carbon concentration in the film determined by Auger electron spectroscopy has no dependence on the deposition temperature and is 1 Qat.%.

Furthermore, the carbon content can be adjusted arbitrarily by changing the CH4 flow rate. Therefore, the prohibited band width can also be set to any value.

Next, an example will be shown in which the S l <1-x) CX layer/silicon heterostructure of the above embodiment is applied to a pn junction diode. A layer having the structure shown in FIGS. 2A to 2C or 2E was formed on a p-type silicon substrate, and its characteristics were evaluated. All planar diodes with a junction area of 3.14 mm achieved a diode ideality factor of n<1.2.

The diode ideality factor n is expressed by n in the following equation for calculating the forward current I.

1 = to (eqV/ai+? l) where,
Io: Saturation current q: Electronic charge ■; Voltage: Boltzmann's constant T: Absolute temperature.

When carbon atoms are incorporated into the deposited film, they tend to combine with trace amounts of oxygen in the gas, so as a result, carbon atoms also include oxygen atoms.
Although Cx0yJI may be formed, this does not impair the effects of the above embodiment.

Next, the reason why the carbon content was set to 5% or more and the substrate temperature was set to 600° C. or more in manufacturing the different types of semiconductor layers shown in FIGS. 2(a) to 2(e) will be described. When considering a heterobipolar transistor (HBT) (npn) transistor, in order to produce sufficient hFE, the energetic "jump" J of the valence band must be equal to or greater than Q, leV (see FIG. 4). The energy difference between the forbidden band width of the structure shown in Figure 2 (a) obtained from the visible light absorption spectrum and the forbidden band width of single crystal silicon is shown on the vertical axis, and the carbon content is shown on the horizontal axis. Figure 5. From FIG. 5, it can be seen that the carbon content must be 5% or more in order for the energy difference in the forbidden band width to be 0.1 e'V or more.

Next, the reason why the substrate temperature was set to 600° C. or higher will be described. From Figure 3, the resistivity is 1 when the substrate temperature is below 600℃.
03Ωcm or more. At this time, in the structure shown in FIG. 2 (bl), for example, if the amorphous silicon region 3 is 30
0'A/cm'', the voltage drop at the emitter will be 0.3v.

In other words, the substrate temperature was limited to 600° C. because a material with a resistivity of 10″Ωcm or more cannot be used as an emitter because it imposes a large restriction on circuit design.

There is no particular upper limit.

Figure 6 shows 5i(1-X)C in Figures 2(a) to (e).
A case is shown in which an X layer/silicon heterostructure is applied to a bipolar transistor. This is an example in which features are added to the emitter structure based on the conventional NPN transistor structure.

In FIG. 6, 8 is a p-type substrate, 9 is an n'' collector buried layer, 10 is an n collector layer, 11 is an n1 collector compensation region, 12 is a p base layer, and 13 is an emitter layer n''S
i <r-x> Cx layer; 14 is an electrode made of metal such as AI or polycrystalline silicon; 15 is an isolation insulating film such as Sin;

Details of the method for manufacturing such a transistor will be described below. In FIG. 6, there is no particular difference in the method of forming the parts 8 to 12.15 from conventional known methods. However, the p-type base layer 12 has a higher impurity concentration than that of a normal bipolar transistor, and has a 2.5X impurity concentration.
10”atom/cm”
of boron is added by ion implantation. At this time, the base layer thickness was 50 nm. This corresponds to a base impurity concentration of 5×10”/am”. Next, Figure 2 (al~(
After forming the layer having the structure of C) or (e) as the emitter layer 13, unnecessary parts other than the emitter opening are covered with CF4-0.
! The aluminum electrode 14 is removed by a dry etching method using system plasma, and an aluminum electrode 14 is formed by a known method to obtain a transistor.

First, a bipolar transistor (hereinafter referred to as "transistor A") having an emitter layer having the structure shown in FIG. 2(a) as an emitter material was manufactured and its characteristics were evaluated. In this case, the film thickness of 5iu-x>Cz layer 2 was set to 600 layers. For a high base concentration (5X10"/cm3), the hFE of transistor A was 30. In order to clarify the effect of transistor A, an emitter layer was added in addition to transistor A shown in Figure 6. A transistor (hereinafter referred to as "reference transistor a") composed only of a silicon layer having the same phosphorus concentration as transistor A was also fabricated, and the characteristics were compared. Transistor A had an hFE of 30, while reference transistor a had h■ of about 5.

Next, a bipolar transistor (hereinafter referred to as "transistor B") having an emitter layer having the structure shown in FIG. 2(b) as an emitter material was manufactured and its characteristics were evaluated. Second
A value of 40 was obtained for hrt of transistor B under the same high base concentration conditions as in the case of FIG. 3(a). This is because the Schottky barrier between the emitter M13 and the wiring metal 14 has disappeared and ohmic contact has been established, resulting in an increase in electron current density.

Next, a bipolar transistor (hereinafter referred to as "transistor C") having an emitter layer having the structure shown in FIG. 2(C) as an emitter material was manufactured and its characteristics were evaluated. Second
For a high base concentration under the same conditions as in Figure (a), hFE of transistor C was obtained as 100. This is because the barrier between the polycrystalline silicon layer 5 and the carbon-containing amorphous silicon layer 3 has disappeared, and the electron current density has further increased.

Next, a bipolar transistor (hereinafter referred to as "transistor E") having an emitter layer having the structure shown in FIG. 2(e) as an emitter material was manufactured and its characteristics were evaluated. Second
A value of 100 was obtained for the hrx of the transistor E for a high base concentration under the same conditions as in Figure 8). In particular, in the case of transistor E, the off-cent became smaller compared to transistor C because the "jump" in the transmission band disappeared.

Next, the effect of lowering resistance will be shown. When the resistance of the emitter material is high, emitter potential drop becomes a problem. When the resistivity of a conventional amorphous material is 100 cm, the collector current is 1×10'A/cm2, and the emitter film thickness is 300, for example, the emitter potential drop is 0.3V. In the structure of this example, it is possible to set the resistance/rate to 0.1 Ωcm, so the emitter potential drop under the same conditions is 0.03
It becomes V. Therefore, voltage loss between collector and emitter is small and high current density can be achieved.

In this way, hFE is high on a high concentration basis;
A transistor that can have a high current density and operates at high speed can be obtained.

〔Effect of the invention〕

As explained above, in the present invention, by forming part or all of the amorphous region of a heterogeneous semiconductor layer composed of an amorphous region and a crystalline region with silicon having a carbon composition of 5% or more,
Since the emitter resistance can be lowered and the recombination current at the hetero interface can be reduced, when the above-mentioned heterogeneous semiconductor layer is applied to a bipolar transistor, the base layer impurity concentration can be increased while maintaining a high current amplification factor. This has the effect of making it thinner and increasing the speed of the transistor.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor device according to the present invention, FIGS. 2(a) to (e) are cross-sectional views showing second to sixth embodiments of the present invention, and FIG. A graph showing the resistivity versus deposition temperature, Fig. 4 is an explanatory diagram showing energetic "jumps", Fig. 5 is a graph showing the relationship between the energy difference in forbidden band width and carbon content, and Fig. 6 is a graph showing the relationship between the energy difference in the forbidden band width and the carbon content. FIG. 2 is a cross-sectional view showing a bipolar transistor to which the different types of semiconductor layers shown in FIGS. (a) to (e) are applied. ■...Silicon single crystal substrate, 2...Sl (1-X
l CX layer.

Claims (1)

Scope of Claims: (1) In a semiconductor device having a heterogeneous semiconductor layer forming a junction with the single crystal silicon on the surface of single crystal silicon, the heterogeneous semiconductor layer includes an amorphous region and a crystalline region, and the heterogeneous semiconductor layer includes an amorphous region and a crystalline region; A semiconductor device characterized in that part or all of the layer is made of silicon with a carbon composition of 5% or more. (2) The amorphous region forms a junction with single crystal silicon and has a carbon composition of 5%.
2. The semiconductor device according to claim 1, wherein the semiconductor device is an amorphous silicon layer as described above, and the crystalline region is a polycrystalline silicon layer. (3) The heterogeneous semiconductor layer is composed of an amorphous region, a transition layer, and a crystalline region, and the amorphous region is composed of an amorphous silicon layer that forms a junction with single crystal silicon and has a carbon composition of 5% or more,
2. The semiconductor device according to claim 1, wherein the transition layer is formed of silicon whose carbon content decreases as the distance from the amorphous silicon layer increases, and the crystalline region is a polycrystalline silicon layer. (4) The heterogeneous semiconductor layer is composed of a transition layer, an amorphous region, and a crystalline region, and the transition layer is formed of silicon that forms a junction with single crystal silicon and whose carbon content increases as the distance from the junction surface increases. 2. The semiconductor device according to claim 1, wherein the amorphous region is made of an amorphous silicon layer containing 5% or more of carbon, and the crystalline region is a polycrystalline silicon layer. (5) A single-crystal silicon substrate is heated to 600°C or higher, and a first type of molecular gas containing at least carbon atoms as one of its constituent atoms and a second type of molecular gas containing silicon atoms as one of its constituent atoms are generated. 1. A method of manufacturing a semiconductor device, comprising the step of forming a heterogeneous semiconductor to form a junction on a single crystal silicon surface by chemical vapor deposition using plasma. (6) The semiconductor device according to claim 5, wherein the carbon composition and the component ratio between the amorphous region and the crystalline region are controlled by changing the flow rate of the first type of molecular gas. manufacturing method.