JPS63278435A - Start-stop signal input device - Google Patents

Abstract

PURPOSE:To prevent malfunction due to an input noise by using a start bit misdiscrimination circuit so as to discriminate the polarity of a start bit thereby deciding the propriety of operation of a sampling circuit in response to the result. CONSTITUTION:If a noise N takes place, it is recognized by the polarity discrimination of a start bit mis-discrimination prevention circuit 6 in the timing (t) that the polarity of the input signal is not of the normal polarity ('1' of data signal). Then the monostable multivibrator 11 of a start bit mid-discrimination prevention circuit 6 is triggered from the result and a sampling pulse stop signal is given to a sampling pulse generating circuit 5. Thus, the timer in the sampling pulse generating circuit 5 started at a significant moment is reset and no sampling pulse train S is generated. Then no sampling pulse is supplied to the sampling circuit 4 and malfunction due to noise N is not caused.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an asynchronous signal input device for data communication equipment, and more particularly to an asynchronous signal input device having a start bit misjudgment prevention circuit. .

[Conventional technology]

Conventionally, as an asynchronous signal input device for data communication equipment, there has been one shown in FIG.

In the figure, the human power interface line 1 to which the start-stop synchronization signal arrives is connected to the human power interface circuit 2, and the output terminal of the input interface circuit 2 is connected to the input terminal T of the sampling pulse generation circuit 3 and the input terminal T of the sampling circuit 4. Connected to the data input terminal. The sampling pulse generation terminal S of the sampling pulse generation circuit 3 is connected to the clock input terminal C of the sampling circuit 4.
The sampled asynchronous signal is output from the sampling output terminal Q.

Note that the sampling pulse generation terminal S is also supplied to other circuits (not shown) in the data communication equipment.

[Problem that the invention seeks to solve]

The above-mentioned conventional asynchronous signal input device is vulnerable to noise generated in the human interface line 1, and misdetects the noise as the start bit of the asynchronous signal, and uses the signal state after the noise as the input data character. It has the disadvantage that it is output incorrectly as a bit string.

FIG. 6 is a timing chart for explaining this malfunction, and the symbols shown on the left side of the figure correspond to the symbols shown in FIG. 4, and indicate the signal waveforms at the respective positions.

When noise N occurs on the input interface line 1 (FIG. 6(a)), the moment the noise N exceeds a predetermined threshold level in the sampling pulse generation circuit 3, the sampling pulse generation circuit 3 is triggered to generate a sampling pulse train S. (No. 6rIIJ(b)). As a result, the sampling circuit 4 starts the sampling operation and starts sampling the data sampled by the first sampling pulse S1).
Ds...) will be erroneously output as a bit string of a human data character (FIG. 5(C)).

In order to prevent such malfunctions, it is conceivable to provide an integration circuit using a resistor and a capacitor between the input interface line 1 and the input interface circuit 2, but if a large power noise occurs, it is possible to completely prevent malfunctions. It was difficult to remove.

SUMMARY OF THE INVENTION An object of the present invention is to provide an asynchronous signal input device for data communication equipment that can eliminate malfunctions caused by human noise.

[Means for solving problems]

An object of the present invention is to provide a start-stop synchronization signal human-powered device that does not cause malfunction even when large power noise occurs, and the timing of the significant moment of the start bit and the generation of the first sampling pulse generated from the sampling pulse generation circuit. The present invention is characterized by comprising a start bit misjudgment prevention circuit that discriminates the polarity of an input signal between the two and causes the sampling pulse generation circuit to stop generating sampling pulses if the polarity is different from the normal polarity.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A start-stop synchronization signal manual device in a data communication device according to the present invention will be described based on an embodiment.

FIG. 1 is a block diagram showing an embodiment of the present invention, and the same parts as in the conventional example (FIG. 5) are denoted by the same reference numerals and the explanation thereof will be omitted.

In the figure, the output terminal of the input interface circuit 2 is connected to the trigger input terminal T of the sampling pulse generation circuit 5 and the input terminal of the start bit misjudgment prevention circuit 6. The output terminal of the start bit misjudgment prevention circuit 6 is connected to the reset terminal R of the sampling pulse generation circuit 5, and the sampling pulse generation terminal S is connected to the sampling circuit 4.
is connected to the clock input terminal CP of.

The sampling pulse generation circuit 5 is triggered by the significant moment of the start bit included in the input signal to start a timer, and the first sampling pulse S1 is generated from the significant moment to half of the data elapsed time T of one bit (1/
2T), and thereafter a sampling pulse train S (S2, S3, S, . . .) is generated at a period T.

The start bit misjudgment prevention circuit 6 includes a mono multi-by-break (MMV) and a sample hold circuit (S/H).
, a comparator, a reference potential generation source, etc., and an embodiment thereof is shown in FIG.

The output signal of the human interface circuit 2 is supplied to a mono-multi-by-break circuit 7 and a sample hold circuit 8, and holds the input signal level after a predetermined time Ts has elapsed from the significant moment E of the start bit. The output level of the sample hold circuit 8 is supplied as a non-inverting input of a comparator 9, and is compared with a reference potential TH supplied to the inverting input.

The output level of the sample and hold circuit 8 is equal to the reference potential TI (
When it exceeds, the output of comparator 9 is inverted,
Set the S-R71J block flop circuit 10. S
When the output of the -R flip-flop circuit IO is set, a state change occurs at its Q terminal, and a sampling pulse stop signal that triggers the mono multi-by-break 11 and resets the sampling pulse generation circuit 5 is generated.

Note that the reset signal of the S-R flip-flop circuit is
It is supplied from a control circuit (not shown) and resets the SR flip-flop circuit before a new start bit arrives.

The time constant TS of the mono-multi-by-break 7 is determined so that the sampling pulse stop signal is generated before the sampling pulse generation circuit 5 generates the first sampling pulse.

FIG. 3 is a timing chart during normal operation.

When the start bit ST arrives, the timer of the sampling pulse generation circuit 5 is triggered at the significant moment E, and the sampling pulse train S is generated (the third
Figure (b)). The sampling circuit 4 uses this sampling pulse train S to detect the input signal start pitch ST and the following data train D (D+, D2, D, . . .
...) is output (Figure 3 (C)).

At this time, just before the first sampling pulse S3 is generated,
The start bit misjudgment prevention circuit 6 determines the polarity of the input signal at timing t (shown in FIG. 3(b)) and confirms that this polarity is the normal polarity (“0” of the data signal). ing. Therefore, in this case, the start bit misjudgment prevention circuit 6 does not issue a sampling pulse stop signal.

FIG. 4 is a timing chart illustrating the operation when noise N occurs, similar to FIG. 6.

In this case, the polarity determination performed by the start bit erroneous determination prevention circuit 6 at timing t recognizes that the polarity of the input signal is not the normal polarity ("1" of the data signal). As a result, the mono-multi-by-break 11 of the start bit misjudgment prevention circuit 6 is triggered, and a sampling pulse stop signal is issued to the sampling pulse generation circuit 5. Therefore, the timer in the sampling pulse generation circuit 5, which was started after the significant moment, is reset and the sampling pulse train S is not generated (FIG. 4(b)). Therefore, no sampling pulse is supplied to the sampling circuit 4, and malfunctions due to the noise N do not occur.

〔Effect of the invention〕

As explained in detail above, according to the asynchronous signal manual device according to the present invention, the polarity of the start bit is determined by the start bit misjudgment prevention circuit, and it is determined whether the sampling circuit is operable or not according to the result. Therefore, malfunctions due to input noise do not occur.

[Brief explanation of drawings]

ff11 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing details of the start bit misjudgment prevention circuit, FIGS. 3 and 4 are timing charts showing the operation of the embodiment, and FIG. The figure is a block diagram showing a conventional example.
FIG. 6 is a timing chart showing the operation of the conventional example. ■・・・Human interface line, 2・・・・・・
- Human interface circuit, 5... Sampling pulse generation circuit, 6... Start bit misjudgment prevention circuit, E... Significant moment, N... Noise, ST...Start bit. Presenter NEC Co., Ltd.

Claims (1)

[Claims] a sampling pulse generation circuit that starts generating a sampling pulse in response to a significant moment of a start bit included in an input signal; a sampling circuit that samples the input signal in response to the sampling pulse; The polarity of the input signal is determined between the instant and the generation timing of the first sampling pulse generated from the sampling pulse generation circuit, and if this polarity is different from the normal polarity, the sampling pulse generation circuit stops generating the sampling pulse. An asynchronous signal input device comprising: a start bit misjudgment prevention circuit.